From 4503042753a710c3c94b84b9daf829a6330e3d12 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Mon, 4 Aug 2014 15:52:59 +0200 Subject: [PATCH] try new clock domains in nx_data_receiver --- nxyter/source/adc_ad9228.vhd | 109 +++++++++++---- nxyter/source/nx_data_receiver.vhd | 210 +++++++++++++++++----------- nxyter/source/nxyter_components.vhd | 15 +- nxyter/source/nxyter_fee_board.vhd | 2 +- nxyter/trb3_periph.prj | 1 + nxyter/trb3_periph_constraints.lpf | 13 +- nxyter/trb3_periph_multi.p2t | 2 +- nxyter/trb3_periph_nx1.vhd | 52 ++++++- 8 files changed, 274 insertions(+), 130 deletions(-) diff --git a/nxyter/source/adc_ad9228.vhd b/nxyter/source/adc_ad9228.vhd index 6db9ab4..97ef6b3 100644 --- a/nxyter/source/adc_ad9228.vhd +++ b/nxyter/source/adc_ad9228.vhd @@ -49,6 +49,8 @@ entity adc_ad9228 is ERROR_ADC0_OUT : out std_logic; ERROR_ADC1_OUT : out std_logic; + ERROR_UNDEF_ADC0_OUT : out std_logic; + ERROR_UNDEF_ADC1_OUT : out std_logic; DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -70,6 +72,7 @@ architecture Behavioral of adc_ad9228 is type adc_data_t is array(0 to 3) of std_logic_vector(11 downto 0); type BYTE_STATUS is (B_UNDEF, + B_BITSHIFTED, B_ALIGNED, B_SHIFTED ); @@ -86,6 +89,7 @@ architecture Behavioral of adc_ad9228 is signal adc0_frame_clk_ok_hist : std_logic_vector(15 downto 0); signal adc0_frame_locked : std_logic; signal adc0_error : std_logic; + signal adc0_error_undef : std_logic; -- ADC0 signal adc1_data_shift : adc_data_s; @@ -100,7 +104,8 @@ architecture Behavioral of adc_ad9228 is signal adc1_frame_clk_ok_hist : std_logic_vector(15 downto 0); signal adc1_frame_locked : std_logic; signal adc1_error : std_logic; - + signal adc1_error_undef : std_logic; + -- Clock Transfer signal adc0_fifo_empty : std_logic; signal adc0_fifo_full : std_logic; @@ -125,6 +130,8 @@ architecture Behavioral of adc_ad9228 is -- Error signal error_adc0_o : std_logic; signal error_adc1_o : std_logic; + signal error_undef_adc0_o : std_logic; + signal error_undef_adc1_o : std_logic; -- Output signal adc0_data_clk_o : std_logic; @@ -196,23 +203,23 @@ begin ----------------------------------------------------------------------------- DFALSE: if (DEBUG_ENABLE = false) generate - - DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(1) <= DDR_DATA_CLK; - DEBUG_OUT(2) <= adc0_write_enable; - DEBUG_OUT(3) <= adc0_fifo_full; - DEBUG_OUT(4) <= adc0_fifo_empty; - DEBUG_OUT(5) <= adc0_data_clk_m; - DEBUG_OUT(6) <= adc0_read_enable; - DEBUG_OUT(7) <= adc0_read_enable_t; - DEBUG_OUT(8) <= adc0_read_enable_tt; - DEBUG_OUT(9) <= adc0_data_clk_o; - DEBUG_OUT(10) <= adc0_error; - DEBUG_OUT(11) <= adc0_frame_locked; - DEBUG_OUT(12) <= adc0_frame_clk_ok; - DEBUG_OUT(13) <= wait_timer_done; - DEBUG_OUT(14) <= RESET_CLKDIV; - DEBUG_OUT(15) <= RESET_ADC0; + DEBUG_OUT <= (others => '0'); + --DEBUG_OUT(0) <= CLK_IN; + --DEBUG_OUT(1) <= DDR_DATA_CLK; + --DEBUG_OUT(2) <= adc0_write_enable; + --DEBUG_OUT(3) <= adc0_fifo_full; + --DEBUG_OUT(4) <= adc0_fifo_empty; + --DEBUG_OUT(5) <= adc0_data_clk_m; + --DEBUG_OUT(6) <= adc0_read_enable; + --DEBUG_OUT(7) <= adc0_read_enable_t; + --DEBUG_OUT(8) <= adc0_read_enable_tt; + --DEBUG_OUT(9) <= adc0_data_clk_o; + --DEBUG_OUT(10) <= adc0_error; + --DEBUG_OUT(11) <= adc0_frame_locked; + --DEBUG_OUT(12) <= adc0_frame_clk_ok; + --DEBUG_OUT(13) <= wait_timer_done; + --DEBUG_OUT(14) <= RESET_CLKDIV; + --DEBUG_OUT(15) <= RESET_ADC0; end generate DFALSE; DTRUE: if (DEBUG_ENABLE = true) generate @@ -408,6 +415,7 @@ begin adc0_frame_clk_ok_hist <= (others => '0'); adc0_frame_locked <= '0'; adc0_error <= '0'; + adc0_error_undef <= '0'; else -- Store new incoming Data in Shift Registers for I in 0 to 4 loop @@ -444,13 +452,23 @@ begin adc0_data_clk_m <= '0'; adc0_frame_clk_ok <= '1'; adc0_byte_status <= B_ALIGNED; - + when "000000111111" | "001111110000" => -- Input Data is correct adc0_data_clk_m <= '0'; adc0_frame_clk_ok <= '1'; adc0_byte_status <= B_SHIFTED; - + + when "000001111110" | + "000111111000" | + "011111100000" | + "111110000001" | + "111000000111" | + "100000011111" => + adc0_data_clk_m <= '0'; + adc0_frame_clk_ok <= '0'; + adc0_byte_status <= B_BITSHIFTED; + when others => -- Input Data is invalid, Fatal Error of DDR Data, needs reset. adc0_data_clk_m <= '0'; @@ -472,12 +490,21 @@ begin -- Error Status adc0_byte_status_last <= adc0_byte_status; - if ( adc0_byte_status /= adc0_byte_status_last or - adc0_byte_status = B_UNDEF) then + --if (adc0_byte_status /= adc0_byte_status_last and + -- adc0_byte_status /= B_UNDEF and + -- adc0_byte_status_last /= B_UNDEF) then + if (adc0_byte_status = B_BITSHIFTED) then adc0_error <= '1'; else adc0_error <= '0'; end if; + + if (adc0_byte_status = B_UNDEF) then + adc0_error_undef <= '1'; + else + adc0_error_undef <= '0'; + end if; + end if; end if; @@ -570,13 +597,18 @@ begin -- Error Status adc1_byte_status_last <= adc1_byte_status; - if (adc1_byte_status /= adc1_byte_status_last or - adc1_byte_status = B_UNDEF) then + if (adc1_byte_status /= adc1_byte_status_last) then adc1_error <= '1'; else adc1_error <= '0'; end if; + if (adc1_byte_status = B_UNDEF) then + adc1_error_undef <= '1'; + else + adc1_error_undef <= '0'; + end if; + end if; end if; end process PROC_MERGE_DATA_ADC1; @@ -723,6 +755,32 @@ begin RESET_B_IN => '0', PULSE_B_OUT => error_adc1_o ); + + pulse_dtrans_ADC0_ERROR_UNDEF: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => '0', + PULSE_A_IN => adc0_error_undef, + CLK_B_IN => CLK_IN, + RESET_B_IN => '0', + PULSE_B_OUT => error_undef_adc0_o + ); + + pulse_dtrans_ADC1_ERROR_UNDEF: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => DDR_DATA_CLK, + RESET_A_IN => '0', + PULSE_A_IN => adc1_error_undef, + CLK_B_IN => CLK_IN, + RESET_B_IN => '0', + PULSE_B_OUT => error_undef_adc1_o + ); -- Output ADC0_SCLK_OUT <= ADC0_SCLK_IN; @@ -745,5 +803,8 @@ begin ERROR_ADC0_OUT <= error_adc0_o; ERROR_ADC1_OUT <= error_adc1_o; + + ERROR_UNDEF_ADC0_OUT <= error_undef_adc0_o; + ERROR_UNDEF_ADC1_OUT <= error_undef_adc1_o; end Behavioral; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index c204049..1e00c25 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -19,7 +19,7 @@ entity nx_data_receiver is NX_CLOCK_ON_IN : in std_logic; -- nXyter Ports - NX_TIMESTAMP_CLK_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_TIMESTAMP_RESET_OUT : out std_logic; @@ -178,10 +178,12 @@ architecture Behavioral of nx_data_receiver is -- Error signal adc_error_i : std_logic; + signal adc_error_undef_i : std_logic; signal error_o : std_logic; signal error_status_bits : std_logic_vector(15 downto 0); signal adc_notlock_counter : unsigned(27 downto 0); signal adc_error_counter : unsigned(27 downto 0); + signal adc_error_undef_counter : unsigned(27 downto 0); -- Rate Errors signal nx_frame_rate_offline_last : std_logic; @@ -266,6 +268,7 @@ architecture Behavioral of nx_data_receiver is signal nx_online_ii : std_logic; signal nx_online_i : std_logic; signal adc_error : std_logic; + signal adc_error_undef : std_logic; signal startup_reset : std_logic; signal rs_wait_timer_start : std_logic; signal rs_wait_timer_done : std_logic; @@ -321,7 +324,7 @@ architecture Behavioral of nx_data_receiver is -- Reset Domain Transfers signal reset_nx_timestamp_clk_in_ff : std_logic; signal reset_nx_timestamp_clk_in_f : std_logic; - signal RESET_NX_TIMESTAMP_CLK_IN : std_logic; + signal RESET_NX_DATA_CLK_IN : std_logic; signal debug_state : std_logic_vector(3 downto 0); signal debug_frame_on : std_logic; @@ -348,9 +351,14 @@ architecture Behavioral of nx_data_receiver is attribute syn_keep of adc_debug_type_f : signal is true; attribute syn_keep of adc_debug_type : signal is true; + attribute syn_keep of nx_frame_word_delay_f : signal is true; + attribute syn_keep of nx_frame_word_delay : signal is true; + + attribute syn_keep of nx_frame_word_f : signal is true; + attribute syn_keep of nx_frame_word_delay_rr : signal is true; attribute syn_keep of nx_frame_word_delay_r : signal is true; - + attribute syn_preserve : boolean; attribute syn_preserve of reset_nx_timestamp_clk_in_ff : signal is true; attribute syn_preserve of reset_nx_timestamp_clk_in_f : signal is true; @@ -370,9 +378,14 @@ architecture Behavioral of nx_data_receiver is attribute syn_preserve of adc_debug_type_f : signal is true; attribute syn_preserve of adc_debug_type : signal is true; + attribute syn_preserve of nx_frame_word_delay_f : signal is true; + attribute syn_preserve of nx_frame_word_delay : signal is true; + + attribute syn_preserve of nx_frame_word_f : signal is true; + attribute syn_preserve of nx_frame_word_delay_rr : signal is true; attribute syn_preserve of nx_frame_word_delay_r : signal is true; - + begin DFALSE: if (DEBUG_ENABLE = false) generate @@ -459,7 +472,7 @@ begin when "101" => -- AD9228 Handler Debug output - DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(0) <= NX_DATA_CLK_IN; DEBUG_OUT(1) <= '0'; DEBUG_OUT(2) <= nx_frame_clk; DEBUG_OUT(3) <= '0'; @@ -473,7 +486,7 @@ begin DEBUG_OUT(15 downto 12) <= adc_data_clk_last; when "110" => - DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(0) <= NX_DATA_CLK_IN; DEBUG_OUT(1) <= '0'; DEBUG_OUT(2) <= '0'; DEBUG_OUT(3) <= '0'; @@ -519,11 +532,11 @@ begin -- Reset Domain Transfer ----------------------------------------------------------------------------- reset_nx_timestamp_clk_in_ff <= RESET_IN - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); reset_nx_timestamp_clk_in_f <= reset_nx_timestamp_clk_in_ff - when rising_edge(NX_TIMESTAMP_CLK_IN); - RESET_NX_TIMESTAMP_CLK_IN <= reset_nx_timestamp_clk_in_f - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); + RESET_NX_DATA_CLK_IN <= reset_nx_timestamp_clk_in_f + when rising_edge(NX_DATA_CLK_IN); ----------------------------------------------------------------------------- -- PLL Handler @@ -587,8 +600,8 @@ begin CLK_RATIO => 2 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => adc_data_clk, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -600,8 +613,8 @@ begin CLK_RATIO => 2 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => nx_frame_clk, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -613,8 +626,8 @@ begin CLK_RATIO => 2 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => parity_error, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -650,8 +663,8 @@ begin CLK_RATIO => 4 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => adc_reset_sync_s, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -666,9 +679,9 @@ begin ); -- ADC Sampling Clock Generator using a Johnson Counter - PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_SAMPLING_CLK_GENERATOR: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then if (adc_sclk_skip = '0') then johnson_ff_0 <= not johnson_ff_1; johnson_ff_1 <= johnson_ff_0; @@ -679,10 +692,10 @@ begin -- Adjust johnson_counter_sync to show optimal value at 0 - PROC_ADC_SAMPLING_CLK_SYNC: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_SAMPLING_CLK_SYNC: process(NX_DATA_CLK_IN) variable adc_sclk_state : std_logic_vector(1 downto 0); begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then johnson_counter_sync <= std_logic_vector(johnson_counter_sync_r); adc_sclk_state := johnson_ff_1 & johnson_ff_0; adc_sclk_skip <= '0'; @@ -697,10 +710,10 @@ begin end if; end process PROC_ADC_SAMPLING_CLK_SYNC; - PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_RESET: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then adc_sclk_ok_last <= '0'; adc_reset_sync_s <= '0'; else @@ -731,26 +744,26 @@ begin ----------------------------------------------------------------------------- -- First use two FFs for NX_TIMESTAMP_IN - nx_frame_word_ff <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); - nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_TIMESTAMP_CLK_IN); + nx_frame_word_ff <= NX_TIMESTAMP_IN when rising_edge(NX_DATA_CLK_IN); + nx_frame_word_f <= nx_frame_word_ff when rising_edge(NX_DATA_CLK_IN); -- Second delay NX_TIMESTAMP_IN relatively to ADC Clock dynamic_shift_register8x64_1: dynamic_shift_register8x64 port map ( Din => nx_frame_word_f, Addr => nx_shift_register_delay, - Clock => NX_TIMESTAMP_CLK_IN, + Clock => NX_DATA_CLK_IN, ClockEn => '1', - Reset => RESET_NX_TIMESTAMP_CLK_IN, + Reset => RESET_NX_DATA_CLK_IN, Q => nx_frame_word_s ); -- Timestamp Input Delay relative to ADC - PROC_NX_SHIFT_REGISTER_DELAY: process(NX_TIMESTAMP_CLK_IN) + PROC_NX_SHIFT_REGISTER_DELAY: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then nx_timestamp_delay_f <= nx_timestamp_delay_s; - if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then + if( RESET_NX_DATA_CLK_IN = '1' ) then nx_timestamp_delay <= "010"; nx_shift_register_delay <= "011011"; -- 27 else @@ -779,9 +792,9 @@ begin end process PROC_NX_SHIFT_REGISTER_DELAY; -- Merge TS Data 8bit to 32Bit Timestamp Frame - PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) + PROC_8_TO_32_BIT: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then case frame_byte_pos is when "11" => nx_frame_word_t(31 downto 24) <= nx_frame_word_s; nx_frame_clk_t <= '0'; @@ -808,10 +821,10 @@ begin end process PROC_8_TO_32_BIT; -- TS Frame Sync process - PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) + PROC_SYNC_TO_NX_FRAME: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if( RESET_NX_TIMESTAMP_CLK_IN = '1' ) then + if (rising_edge(NX_DATA_CLK_IN)) then + if( RESET_NX_DATA_CLK_IN = '1' ) then frame_byte_pos <= "11"; rs_sync_set <= '0'; rs_sync_reset <= '0'; @@ -847,10 +860,10 @@ begin end process PROC_SYNC_TO_NX_FRAME; -- RS FlipFlop to hold Sync Status - PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) + PROC_RS_FRAME_SYNCED: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then nx_frame_synced <= '0'; else if (rs_sync_reset = '1') then @@ -863,12 +876,12 @@ begin end process PROC_RS_FRAME_SYNCED; -- Check Parity Bit - PROC_PARITY_CHECKER: process(NX_TIMESTAMP_CLK_IN) + PROC_PARITY_CHECKER: process(NX_DATA_CLK_IN) variable parity_bits : std_logic_vector(22 downto 0); variable parity : std_logic; begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then parity_error <= '0'; else if (nx_frame_clk = '1') then @@ -895,9 +908,9 @@ begin ----------------------------------------------------------------------------- -- Delay NX Timestamp relative to ADC Frames ----------------------------------------------------------------------------- - PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_TIMESTAMP_CLK_IN) + PROC_NX_TIMESTAMP_FRAME_DELAY: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then nx_frame_word_delayed_t(0) <= nx_frame_word; nx_frame_clk_delayed_t(0) <= nx_frame_clk; @@ -915,13 +928,13 @@ begin end if; end process PROC_NX_TIMESTAMP_FRAME_DELAY; - PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_TIMESTAMP_CLK_IN) + PROC_NX_FRAME_WORD_DELAY_AUTO_SETUP: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then nx_frame_word_delay <= nx_frame_word_delay_f; adc_data_clk_last(0) <= adc_data_s_clk; - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (RESET_NX_DATA_CLK_IN = '1') then nx_frame_word_delay_f <= "10"; adc_data_clk_last(3 downto 1) <= (others => '0'); frame_word_delay_change <= '0'; @@ -970,27 +983,27 @@ begin ----------------------------------------------------------------------------- adc_reset_handler_cnx_ff <= adc_reset_handler - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); adc_reset_handler_cnx_f <= adc_reset_handler_cnx_ff - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); adc_reset_handler_cnx <= adc_reset_handler_cnx_f - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); - ADC_RESET_AD9228 <= RESET_NX_TIMESTAMP_CLK_IN or + ADC_RESET_AD9228 <= RESET_NX_DATA_CLK_IN or adc_reset_handler_cnx; adc_debug_type_f <= adc_debug_type_r - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); adc_debug_type <= adc_debug_type_f - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); adc_ad9228_1: adc_ad9228 generic map ( DEBUG_ENABLE => false ) port map ( - CLK_IN => NX_TIMESTAMP_CLK_IN, + CLK_IN => NX_DATA_CLK_IN, RESET_IN => ADC_RESET_AD9228, CLK_ADCDAT_IN => ADC_CLK_DAT_IN, @@ -1029,14 +1042,18 @@ begin ERROR_ADC0_OUT => adc_error_i, ERROR_ADC1_OUT => open, + + ERROR_UNDEF_ADC0_OUT => adc_error_undef_i, + ERROR_UNDEF_ADC1_OUT => open, + DEBUG_IN => adc_debug_type, DEBUG_OUT => ADC_DEBUG ); - PROC_ADC_DATA_BIT_SHIFT: process(NX_TIMESTAMP_CLK_IN) + PROC_ADC_DATA_BIT_SHIFT: process(NX_DATA_CLK_IN) variable adcval : unsigned(11 downto 0) := (others => '0'); begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_DATA_CLK_IN)) then if (adc_bit_shift(3) = '1') then adcval := unsigned(adc_data) rol to_integer(adc_bit_shift(2 downto 0)); @@ -1059,16 +1076,16 @@ begin -- Merge Data Streams Timestamps and ADC Value ----------------------------------------------------------------------------- merge_handler_reset_i <= output_handler_reset - when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); merge_handler_reset <= merge_handler_reset_i - when rising_edge(NX_TIMESTAMP_CLK_IN); - disable_adc_f <= disable_adc_r when rising_edge(NX_TIMESTAMP_CLK_IN); - disable_adc <= disable_adc_f when rising_edge(NX_TIMESTAMP_CLK_IN); + when rising_edge(NX_DATA_CLK_IN); + disable_adc_f <= disable_adc_r when rising_edge(NX_DATA_CLK_IN); + disable_adc <= disable_adc_f when rising_edge(NX_DATA_CLK_IN); - PROC_DATA_MERGE_HANDLER: process(NX_TIMESTAMP_CLK_IN) + PROC_DATA_MERGE_HANDLER: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1' or merge_handler_reset = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1' or merge_handler_reset = '1') then merge_timeout_ctr <= (others => '0'); merge_timeout_error <= '0'; merge_error_ctr <= (others => '0'); @@ -1108,7 +1125,7 @@ begin fifo_data_stream_44to44_dc_1: fifo_data_stream_44to44_dc port map ( Data => data_frame, - WrClock => NX_TIMESTAMP_CLK_IN, + WrClock => NX_DATA_CLK_IN, RdClock => CLK_IN, WrEn => fifo_write_enable, RdEn => fifo_read_enable, @@ -1165,8 +1182,8 @@ begin CLK_RATIO => 3 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => rs_sync_reset, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -1325,8 +1342,8 @@ begin CLK_RATIO => 2 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => adc_dt_error_p, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -1338,8 +1355,8 @@ begin CLK_RATIO => 2 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => timestamp_dt_error_p, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, @@ -1372,10 +1389,10 @@ begin end if; end process PROC_EVENT_ERRORS_PER_SECOND; - PROC_DATA_STREAM_DELTA_T: process(NX_TIMESTAMP_CLK_IN) + PROC_DATA_STREAM_DELTA_T: process(NX_DATA_CLK_IN) begin - if (rising_edge(NX_TIMESTAMP_CLK_IN)) then - if (RESET_NX_TIMESTAMP_CLK_IN = '1') then + if (rising_edge(NX_DATA_CLK_IN)) then + if (RESET_NX_DATA_CLK_IN = '1') then new_adc_dt_ctr <= (others => '0'); new_timestamp_dt_ctr <= (others => '0'); new_adc_dt_error_ctr <= (others => '0'); @@ -1660,26 +1677,40 @@ begin CLK_RATIO => 2 ) port map ( - CLK_A_IN => NX_TIMESTAMP_CLK_IN, - RESET_A_IN => RESET_NX_TIMESTAMP_CLK_IN, + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, PULSE_A_IN => adc_error_i, CLK_B_IN => CLK_IN, RESET_B_IN => RESET_IN, PULSE_B_OUT => adc_error ); + pulse_dtrans_ADC_ERROR_UNDEF: pulse_dtrans + generic map ( + CLK_RATIO => 2 + ) + port map ( + CLK_A_IN => NX_DATA_CLK_IN, + RESET_A_IN => RESET_NX_DATA_CLK_IN, + PULSE_A_IN => adc_error_undef_i, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => adc_error_undef + ); + PROC_ERROR_STATUS: process(CLK_IN) variable error_mask : std_logic_vector(15 downto 0); begin if (rising_edge(CLK_IN)) then - adc_sclk_ok_f <= adc_sclk_ok; + adc_sclk_ok_f <= adc_sclk_ok; if (RESET_IN = '1') then - adc_sclk_ok_c100 <= '0'; - error_status_bits <= (others => '0'); - error_o <= '0'; - adc_notlock_counter <= (others => '0'); - adc_error_counter <= (others => '0'); + adc_sclk_ok_c100 <= '0'; + error_status_bits <= (others => '0'); + error_o <= '0'; + adc_notlock_counter <= (others => '0'); + adc_error_counter <= (others => '0'); + adc_error_undef_counter <= (others => '0'); else adc_sclk_ok_c100 <= adc_sclk_ok_f; @@ -1718,6 +1749,10 @@ begin adc_error_counter <= adc_error_counter + 1; end if; + if (adc_error_undef = '1') then + adc_error_undef_counter <= adc_error_undef_counter + 1; + end if; + end if; end if; end process PROC_ERROR_STATUS; @@ -1758,6 +1793,8 @@ begin fifo_full_rr <= fifo_full; fifo_empty_rr <= fifo_empty; nx_frame_synced_rr <= nx_frame_synced; + nx_frame_word_delay_rr <= nx_frame_word_delay_f; + if (RESET_IN = '1') then fifo_full_r <= '0'; fifo_empty_r <= '0'; @@ -1766,6 +1803,7 @@ begin new_timestamp_dt_error_ctr_r <= (others => '0'); adc_notlock_ctr_r <= (others => '0'); merge_error_ctr_r <= (others => '0'); + nx_frame_word_delay_r <= (others => '0'); else fifo_full_r <= fifo_full_rr; fifo_empty_r <= fifo_empty_rr; @@ -1774,6 +1812,7 @@ begin new_timestamp_dt_error_ctr_r <= new_timestamp_dt_error_ctr; adc_notlock_ctr_r <= adc_notlock_ctr; merge_error_ctr_r <= merge_error_ctr; + nx_frame_word_delay_r <= nx_frame_word_delay_rr; end if; end if; end process PROC_SLAVE_BUS_BUFFER; @@ -1903,6 +1942,7 @@ begin when x"0010" => slv_data_out_o(2 downto 0) <= std_logic_vector(nx_timestamp_delay_s); + slv_data_out_o(3) <= '0'; slv_data_out_o(5 downto 4) <= std_logic_vector(nx_frame_word_delay_r); slv_data_out_o(14 downto 6) <= (others => '0'); @@ -1953,6 +1993,12 @@ begin slv_data_out_o(31 downto 28) <= (others => '0'); slv_ack_o <= '1'; + when x"0018" => + slv_data_out_o(27 downto 0) <= + std_logic_vector(adc_error_undef_counter); + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + when x"001e" => slv_data_out_o(2 downto 0) <= debug_mode; slv_data_out_o(31 downto 3) <= (others => '0'); diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 8fc0ae8..afbf9bf 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -214,13 +214,11 @@ end component; component adc_ad9228 generic ( - DEBUG_ENABLE : boolean - ); + DEBUG_ENABLE : boolean); port ( CLK_IN : in std_logic; RESET_IN : in std_logic; CLK_ADCDAT_IN : in std_logic; - ADC0_SCLK_IN : in std_logic; ADC0_SCLK_OUT : out std_logic; ADC0_DATA_A_IN : in std_logic; @@ -229,7 +227,6 @@ component adc_ad9228 ADC0_DATA_D_IN : in std_logic; ADC0_DCLK_IN : in std_logic; ADC0_FCLK_IN : in std_logic; - ADC1_SCLK_IN : in std_logic; ADC1_SCLK_OUT : out std_logic; ADC1_DATA_A_IN : in std_logic; @@ -238,25 +235,23 @@ component adc_ad9228 ADC1_DATA_D_IN : in std_logic; ADC1_DCLK_IN : in std_logic; ADC1_FCLK_IN : in std_logic; - ADC0_DATA_A_OUT : out std_logic_vector(11 downto 0); ADC0_DATA_B_OUT : out std_logic_vector(11 downto 0); ADC0_DATA_C_OUT : out std_logic_vector(11 downto 0); ADC0_DATA_D_OUT : out std_logic_vector(11 downto 0); ADC0_DATA_CLK_OUT : out std_logic; - ADC1_DATA_A_OUT : out std_logic_vector(11 downto 0); ADC1_DATA_B_OUT : out std_logic_vector(11 downto 0); ADC1_DATA_C_OUT : out std_logic_vector(11 downto 0); ADC1_DATA_D_OUT : out std_logic_vector(11 downto 0); ADC1_DATA_CLK_OUT : out std_logic; - ADC0_LOCKED_OUT : out std_logic; ADC1_LOCKED_OUT : out std_logic; ERROR_ADC0_OUT : out std_logic; ERROR_ADC1_OUT : out std_logic; - - DEBUG_IN : in std_logic_vector(3 downto 0); + ERROR_UNDEF_ADC0_OUT : out std_logic; + ERROR_UNDEF_ADC1_OUT : out std_logic; + DEBUG_IN : in std_logic_vector(3 downto 0); DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -454,7 +449,7 @@ component nx_data_receiver TRIGGER_IN : in std_logic; NX_ONLINE_IN : in std_logic; NX_CLOCK_ON_IN : in std_logic; - NX_TIMESTAMP_CLK_IN : in std_logic; + NX_DATA_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_TIMESTAMP_RESET_OUT : out std_logic; ADC_CLK_DAT_IN : in std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index d34c90f..7d381df 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -561,7 +561,7 @@ begin NX_ONLINE_IN => nxyter_online, NX_CLOCK_ON_IN => nxyter_clock_on, - NX_TIMESTAMP_CLK_IN => NX_DATA_CLK_IN, + NX_DATA_CLK_IN => NX_DATA_CLK_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, NX_TIMESTAMP_RESET_OUT => nx_timestamp_reset, diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index ded84f0..4f32fbd 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -157,6 +157,7 @@ add_file -vhdl -lib "work" "cores/fifo_adc_48to48_dc.vhd" add_file -vhdl -lib "work" "cores/fifo_32_data.vhd" add_file -vhdl -lib "work" "cores/dynamic_shift_register8x64.vhd" +add_file -vhdl -lib "work" "../base/code/sedcheck.vhd" add_file -vhdl -lib "work" "trb3_periph.vhd" add_file -vhdl -lib "work" "source/nxyter_components.vhd" diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index f01711f..2ab71f3 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -1,3 +1,6 @@ +####################################################################### + + BLOCK RESETPATHS ; BLOCK ASYNCPATHS ; BLOCK RD_DURING_WR_PATHS ; @@ -32,14 +35,10 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT NX1_DATA_CLK_IN 125 MHz; - #FREQUENCY PORT NX2_DATA_CLK_IN 125 MHz; - USE PRIMARY NET "nx_main_clk_c"; USE PRIMARY NET "clk_100_i_c"; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; - -# USE PRIMARY2EDGE NET "nx_clk_adc_dat"; ################################################################# # Reset Nets @@ -136,11 +135,11 @@ LOCATE UGROUP "THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; # DDR Generic PLL Setup, very important, do never remove! LOCATE COMP "pll_adc_clk_1/PLLInst_0" SITE "PLL_R61C5" ; -PROHIBIT PRIMARY NET "NX1_DATA_CLK_*"; -PROHIBIT SECONDARY NET "NX1_DATA_CLK_*"; +PROHIBIT PRIMARY NET "NX1_DATA_CLK_IN_c"; +PROHIBIT SECONDARY NET "NX1_DATA_CLK_IN_c"; DEFINE PORT GROUP "NX1_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX1_IN" 1.5 ns HOLD 1.5 ns CLKPORT="NX1_DATA_CLK_IN"; +INPUT_SETUP GROUP "NX1_IN" 0.5 ns HOLD 0.5 ns CLKPORT="NX1_DATA_CLK_IN"; UGROUP NXYTER1 BBOX 100 70 BLKNAME nXyter_FEE_board_0; diff --git a/nxyter/trb3_periph_multi.p2t b/nxyter/trb3_periph_multi.p2t index b7195f8..e1711c7 100644 --- a/nxyter/trb3_periph_multi.p2t +++ b/nxyter/trb3_periph_multi.p2t @@ -2,7 +2,7 @@ -i 2 -l 5 -n 20 --t 30 +-t 5 -s 1 -c 1 -e 2 diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nx1.vhd index 16cb420..8b10ee8 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nx1.vhd @@ -252,14 +252,25 @@ architecture trb3_periph_arch of trb3_periph is signal spi_bram_we : std_logic; --FPGA Test + signal time_counter : unsigned(31 downto 0); + -- SED Detection + signal sed_error : std_logic; + signal sed_din : std_logic_vector(31 downto 0); + signal sed_dout : std_logic_vector(31 downto 0); + signal sed_write : std_logic := '0'; + signal sed_read : std_logic := '0'; + signal sed_ack : std_logic := '0'; + signal sed_nack : std_logic := '0'; + signal sed_addr : std_logic_vector(15 downto 0) := (others => '0'); + -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; signal nx_pll_clk_lock : std_logic; signal nx_pll_reset : std_logic; - signal nx_clk_adc_dat : std_logic; + signal NX_CLK_ADC_DAT : std_logic; signal nx_pll_adc_clk_lock : std_logic; signal nx1_adc_sample_clk : std_logic; @@ -279,7 +290,7 @@ architecture trb3_periph_arch of trb3_periph is -- Internal Trigger signal fee1_trigger : std_logic; - + begin --------------------------------------------------------------------------- -- Reset Generation @@ -489,14 +500,16 @@ begin --------------------------------------------------------------------------- THE_BUS_HANDLER : trb_net16_regio_bus_handler generic map( - PORT_NUMBER => 3, + PORT_NUMBER => 4, PORT_ADDRESSES => (0 => x"d000", 1 => x"d100", 2 => x"8000", + 3 => x"d500", others => x"0000"), PORT_ADDR_MASK => (0 => 1, 1 => 6, 2 => 12, + 3 => 4, others => 0) ) port map( @@ -553,6 +566,17 @@ begin BUS_NO_MORE_DATA_IN(2) => nx1_regio_no_more_data_out, BUS_UNKNOWN_ADDR_IN(2) => nx1_regio_unknown_addr_out, + BUS_READ_ENABLE_OUT(3) => sed_read, + BUS_WRITE_ENABLE_OUT(3) => sed_write, + BUS_DATA_OUT(3*32+31 downto 3*32) => sed_din, + BUS_ADDR_OUT(3*16+15 downto 3*16) => sed_addr, + BUS_TIMEOUT_OUT(3) => open, + BUS_DATA_IN(3*32+31 downto 3*32) => sed_dout, + BUS_DATAREADY_IN(3) => sed_ack, + BUS_WRITE_ACK_IN(3) => sed_ack, + BUS_NO_MORE_DATA_IN(3) => '0', + BUS_UNKNOWN_ADDR_IN(3) => sed_nack, + STAT_DEBUG => open ); @@ -638,7 +662,7 @@ begin CLK_IN => clk_100_i, RESET_IN => reset_i, CLK_NX_MAIN_IN => nx_main_clk, - CLK_ADC_IN => nx_clk_adc_dat, + CLK_ADC_IN => NX_CLK_ADC_DAT, PLL_NX_CLK_LOCK_IN => nx_pll_clk_lock, PLL_ADC_DCLK_LOCK_IN => nx_pll_adc_clk_lock, PLL_RESET_OUT => nx_pll_reset, @@ -712,7 +736,25 @@ begin NX1_DEBUG_LINE <= nx1_debug_line_o; FPGA5_COMM(10) <= fee1_trigger; + + --------------------------------------------------------------------------- + -- SED Detection + --------------------------------------------------------------------------- + + THE_SED : entity work.sedcheck + port map( + CLK => clk_100_i, + ERROR_OUT => sed_error, + DATA_IN => sed_din, + DATA_OUT => sed_dout, + WRITE_IN => sed_write, + READ_IN => sed_read, + ACK_OUT => sed_ack, + NACK_OUT => sed_nack, + ADDR_IN => sed_addr + ); + ----------------------------------------------------------------------------- -- nXyter Main and ADC Clocks ----------------------------------------------------------------------------- @@ -743,7 +785,7 @@ begin port map ( CLK => CLK_PCLK_RIGHT, RESET => nx_pll_reset, - CLKOP => nx_clk_adc_dat, + CLKOP => NX_CLK_ADC_DAT, LOCK => nx_pll_adc_clk_lock ); -- 2.43.0