From 450d22400377c90c7efb7783cadee9abf45ff802 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 2 Jun 2020 11:57:14 +0200 Subject: [PATCH] regenerated old fifo --- gbe_trb/ipcores/ecp3/fifo_4096x9.ipx | 9 +++++++++ gbe_trb/ipcores/ecp3/fifo_4096x9.lpc | 9 ++++++--- gbe_trb/ipcores/ecp3/fifo_4096x9.vhd | 14 ++++++++------ 3 files changed, 23 insertions(+), 9 deletions(-) create mode 100644 gbe_trb/ipcores/ecp3/fifo_4096x9.ipx diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9.ipx b/gbe_trb/ipcores/ecp3/fifo_4096x9.ipx new file mode 100644 index 0000000..f59ef32 --- /dev/null +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc b/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc index 6e382a8..b8a09a2 100755 --- a/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC -CoreRevision=5.4 +CoreRevision=5.8 ModuleName=fifo_4096x9 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=09/22/2011 -Time=11:24:06 +Date=05/15/2019 +Time=17:03:47 [Parameters] Verilog=0 @@ -45,3 +45,6 @@ PfDeassert=506 RDataCount=0 WDataCount=0 EnECC=0 + +[Command] +cmd_line= -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type fifodc -addr_width 12 -data_width 9 -num_words 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 diff --git a/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd b/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd index 75ae6c9..4012688 100755 --- a/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd +++ b/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_1.3_Production (92) --- Module Version: 5.4 ---/opt/lattice/diamond/1.3/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 -e +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.3.144 +-- Module Version: 5.8 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n fifo_4096x9 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 4096 -width 9 -depth 4096 -rdata_width 9 -no_enable -pe -1 -pf -1 --- Thu Sep 22 11:24:06 2011 +-- Wed May 15 17:03:47 2019 library IEEE; use IEEE.std_logic_1164.all; @@ -187,8 +187,8 @@ architecture Structure of fifo_4096x9 is signal co4: std_logic; signal iwcount_12: std_logic; signal co6: std_logic; - signal wcount_12: std_logic; signal co5: std_logic; + signal wcount_12: std_logic; signal scuba_vhi: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; @@ -210,8 +210,8 @@ architecture Structure of fifo_4096x9 is signal co4_1: std_logic; signal ircount_12: std_logic; signal co6_1: std_logic; - signal rcount_12: std_logic; signal co5_1: std_logic; + signal rcount_12: std_logic; signal mdout1_1_0: std_logic; signal mdout1_0_0: std_logic; signal mdout1_1_1: std_logic; @@ -569,6 +569,8 @@ architecture Structure of fifo_4096x9 is attribute GSR of FF_1 : label is "ENABLED"; attribute GSR of FF_0 : label is "ENABLED"; attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; begin -- component instantiation statements -- 2.43.0