From 456ae6669bac32a0e3c93873e889f55e038eefff Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Sun, 10 Jul 2022 00:29:33 +0200 Subject: [PATCH] changes to sync reset --- cores/pll_dcdc.ipx | 8 ++ cores/pll_dcdc.lpc | 69 +++++++++++++++ cores/pll_dcdc.vhd | 95 +++++++++++++++++++++ gbe_hub/clock_reset_handler.vhd | 105 +++++++++++++++++++++++ gbe_hub/linkdesignfiles.sh | 21 +++++ gbe_hub/reset_handler.vhd | 105 +++++++++++++++++++++++ gbe_hub/trb3sc_gbe_hub.prj | 37 ++------- gbe_hub/trb3sc_gbe_hub.vhd | 143 +++++++++++++++----------------- pinout/basic_constraints.lpf | 55 ++---------- scripts/compile.pl | 7 +- 10 files changed, 487 insertions(+), 158 deletions(-) create mode 100644 cores/pll_dcdc.ipx create mode 100644 cores/pll_dcdc.lpc create mode 100644 cores/pll_dcdc.vhd create mode 100644 gbe_hub/clock_reset_handler.vhd create mode 100755 gbe_hub/linkdesignfiles.sh create mode 100644 gbe_hub/reset_handler.vhd diff --git a/cores/pll_dcdc.ipx b/cores/pll_dcdc.ipx new file mode 100644 index 0000000..e7baa37 --- /dev/null +++ b/cores/pll_dcdc.ipx @@ -0,0 +1,8 @@ + + + + + + + + diff --git a/cores/pll_dcdc.lpc b/cores/pll_dcdc.lpc new file mode 100644 index 0000000..1cf62ca --- /dev/null +++ b/cores/pll_dcdc.lpc @@ -0,0 +1,69 @@ +[Device] +Family=latticeecp3 +PartType=LFE3-150EA +PartName=LFE3-150EA-8FN1156C +SpeedGrade=8 +Package=FPBGA1156 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_dcdc +SourceFormat=VHDL +ParameterFileVersion=1.0 +Date=07/09/2022 +Time=22:47:20 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=125 +Div=61 +ClkOPBp=0 +Post=128 +U_OFrq=4.098361 +OP_Tol=0.0 +OFrq=4.098361 +DutyTrimP=Rising +DelayMultP=0 +fb_mode=CLKOP +Mult=2 +Phase=0.0 +Duty=8 +DelayMultS=0 +DPD=50% Duty +DutyTrimS=Rising +DelayMultD=0 +ClkOSDelay=0 +PhaseDuty=Static +CLKOK_INPUT=CLKOP +SecD=2 +U_KFrq=50 +OK_Tol=0.0 +KFrq= +ClkRst=0 +PCDR=0 +FINDELA=0 +VcoRate= +Bandwidth=0.428040 +;DelayControl=No +EnCLKOS=0 +ClkOSBp=0 +EnCLKOK=0 +ClkOKBp=0 +enClkOK2=0 + +[Command] +cmd_line= -w -n pll_dcdc -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 4.098361 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw diff --git a/cores/pll_dcdc.vhd b/cores/pll_dcdc.vhd new file mode 100644 index 0000000..df8e5a6 --- /dev/null +++ b/cores/pll_dcdc.vhd @@ -0,0 +1,95 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.12.1.454 +-- Module Version: 5.7 +--/opt/lattice/diamond/3.12/ispfpga/bin/lin64/scuba -w -n pll_dcdc -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 4.098361 -fclkop_tol 0.0 -fb_mode CLOCKTREE -noclkos -noclkok -norst -noclkok2 -bw + +-- Sat Jul 9 22:47:20 2022 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp3; +use ecp3.components.all; +-- synopsys translate_on + +entity pll_dcdc is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); +end pll_dcdc; + +architecture Structure of pll_dcdc is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component EHXPLLF + generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; + DELAY_PWD : in String; DELAY_VAL : in Integer; + CLKOS_TRIM_DELAY : in Integer; + CLKOS_TRIM_POL : in String; + CLKOP_TRIM_DELAY : in Integer; + CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + PHASE_DELAY_CNTL : in String; DUTY : in Integer; + PHASEADJ : in String; CLKOK_DIV : in Integer; + CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; + CLKI_DIV : in Integer; FIN : in String); + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; + FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; + CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; + LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "4.098361"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLF + generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", + PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", + CLKOK_DIV=> 2, CLKOP_DIV=> 128, CLKFB_DIV=> 2, CLKI_DIV=> 61, + FIN=> "125.000000") + port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, + FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, + CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, + CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; + +-- synopsys translate_off +library ecp3; +configuration Structure_CON of pll_dcdc is + for Structure + for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; + for all:VLO use entity ecp3.VLO(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/gbe_hub/clock_reset_handler.vhd b/gbe_hub/clock_reset_handler.vhd new file mode 100644 index 0000000..8a3dc29 --- /dev/null +++ b/gbe_hub/clock_reset_handler.vhd @@ -0,0 +1,105 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_components.all; + use work.trb_net_std.all; + use work.trb3_components.all; + use work.config.all; + +entity clock_reset_handler is + port( + CLK_IN : in std_logic; + GLOBAL_RESET_IN : in std_logic := '0'; + RESET_FROM_NET_IN : in std_logic := '0'; + -- + CLK_OUT : out std_logic; + RESET_OUT : out std_logic; + RESET_N_OUT : out std_logic; + CLEAR_OUT : out std_logic; + CLEAR_N_OUT : out std_logic; + -- + ENPIRION_CLOCK : out std_logic; + LED_RED_OUT : out std_logic; + LED_GREEN_OUT : out std_logic + ); +end entity; + +architecture clock_reset_handler_arch of clock_reset_handler is + +signal timer : unsigned(15 downto 0) := (others => '0'); +signal clear_n_i : std_logic; +signal reset_i : std_logic; +signal clk_enpirion : std_logic; +signal pll_enpirion_locked : std_logic; +signal enpirion_clock_i : std_logic; + +attribute syn_keep : boolean; +attribute syn_preserve : boolean; +attribute syn_keep of clear_n_i : signal is true; +attribute syn_preserve of clear_n_i : signal is true; + +begin + + CLK_OUT <= CLK_IN; + +--------------------------------------------------------------------------- +-- Startup timer, generates inital reset +--------------------------------------------------------------------------- + THE_START_TIMER_PROC: process + begin + wait until rising_edge(CLK_IN); + if( timer(15) = '1' ) then + timer <= timer; + else + timer <= timer + 1; + end if; + end process THE_START_TIMER_PROC; + + -- asserted only at power up! + clear_n_i <= timer(15) when rising_edge(CLK_IN); + + CLEAR_OUT <= not clear_n_i; + + CLEAR_N_OUT <= clear_n_i; + +--------------------------------------------------------------------------- +-- these resets can be triggered +--------------------------------------------------------------------------- + THE_RESET_HANDLER: entity reset_handler + port map( + CLEAR_IN => GLOBAL_RESET_IN, + CLEAR_N_IN => clear_n_i, + CLK_IN => CLK_IN, + PLL_LOCKED_IN => pll_enpirion_locked, + RESET_IN => RESET_FROM_NET_IN, + TRB_RESET_IN => '0', -- unused, + CLEAR_OUT => open, + RESET_OUT => reset_i + ); + + RESET_OUT <= reset_i; + + RESET_N_OUT <= not reset_i; + + THE_ENPIRION_PLL: entity pll_dcdc + port map( + CLK => CLK_IN, + CLKOP => clk_enpirion, + LOCK => pll_enpirion_locked + ); + + THE_ENPIRION_PROC: process( clk_enpirion ) + begin + if( rising_edge(clk_enpirion) ) then + enpirion_clock_i <= not enpirion_clock_i; + end if; + end process THE_ENPIRION_PROC; + + ENPIRION_CLOCK <= enpirion_clock_i; + + LED_RED_OUT <= not reset_i; + LED_GREEN_OUT <= not pll_enpirion_locked; + +end architecture clock_reset_handler_arch; diff --git a/gbe_hub/linkdesignfiles.sh b/gbe_hub/linkdesignfiles.sh new file mode 100755 index 0000000..a07cefa --- /dev/null +++ b/gbe_hub/linkdesignfiles.sh @@ -0,0 +1,21 @@ +#!/bin/bash +#These files should be linked in your workdir for new projects +#they have to be in the directory were all the reports and bitfiles end up! +#usually ./workdir (command line script) or ./$PROJECTNAME (Diamond) + +#it is assumed, that pwd is the first dir in the designs directory, e.g. +#trb3/DESIGN/workdir. If this is not the case pass as first parameter a +#path suffix to get to this level. For instance if you're in +#trb3/DESIGN/project/TOPNAME call "../../../base/linkdesignfiles.sh .." + +if [ $1 ] +then + prefix=$1 +else + prefix="." +fi + +ln -sf $prefix/../../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.txt +ln -sf $prefix/../../../trbnet/gbe_trb_ecp3/media/sgmii_gbe_pcs42.ngo +ln -sf $prefix/../../../trbnet/gbe_trb_ecp3/media/tsmac41.ngo +ln -sf $prefix/../../../trbnet/gbe_trb_ecp3/media/pmi_ram_dpEbnonessdn208256208256p13732cfe.ngo diff --git a/gbe_hub/reset_handler.vhd b/gbe_hub/reset_handler.vhd new file mode 100644 index 0000000..16def7a --- /dev/null +++ b/gbe_hub/reset_handler.vhd @@ -0,0 +1,105 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.std_logic_arith.all; +use ieee.std_logic_unsigned.all; + +library work; + +entity reset_handler is + port( + CLEAR_IN : in std_logic; -- reset input (high active, async) + CLEAR_N_IN : in std_logic; -- reset input (low active, async) + CLK_IN : in std_logic; -- raw master clock, NOT from PLL/DLL! + PLL_LOCKED_IN : in std_logic; -- master PLL lock signal (async) + RESET_IN : in std_logic; -- general reset signal + TRB_RESET_IN : in std_logic; -- TRBnet reset signal + CLEAR_OUT : out std_logic; -- async reset out, USE WITH CARE! + RESET_OUT : out std_logic -- synchronous reset out + ); +end entity reset_handler; + +-- This reset handler tries to generate a stable synchronous reset +-- for FPGA fabric. It waits for the system clock PLL to lock, reacts +-- on two external asynchronous resets, and also allows to reset the +-- FPGA by sending a synchronous TRBnet reset pulse. +-- It is not recommended to reset the system clock PLL/DLL with +-- any of the reset signals generated here. It may deadlock. + +architecture reset_handler_arch of reset_handler is + + -- normal signals + signal async_sampler : std_logic_vector(7 downto 0); -- input shift register + signal comb_async_pulse : std_logic; + signal async_pulse : std_logic; + signal reset_cnt : unsigned(15 downto 0) := (others => '0'); + signal reset : std_logic; + + signal reset_pulse : std_logic_vector(1 downto 0) := (others => '0'); + signal trb_reset_pulse : std_logic_vector(1 downto 0) := (others => '0'); + signal comb_async_rst_n : std_logic; + + attribute syn_preserve : boolean; + attribute syn_preserve of async_sampler : signal is true; + attribute syn_preserve of async_pulse : signal is true; + attribute syn_preserve of reset : signal is true; + attribute syn_preserve of reset_cnt : signal is true; + attribute syn_preserve of comb_async_rst_n : signal is true; + + attribute syn_hier : string; + attribute syn_hier of reset_handler_arch : architecture is "firm"; + +begin + +---------------------------------------------------------------- +-- Combine all async reset sources: CLR, /CLR, PLL_LOCK +---------------------------------------------------------------- + comb_async_rst_n <= not CLEAR_IN and CLEAR_N_IN and PLL_LOCKED_IN; + +---------------------------------------------------------------- +-- sample the async reset line and react only on a long pulse +---------------------------------------------------------------- + THE_ASYNC_SAMPLER_PROC: process( CLK_IN ) + begin + if( rising_edge(CLK_IN) ) then + async_sampler(7 downto 0) <= async_sampler(6 downto 0) & comb_async_rst_n; + async_pulse <= comb_async_pulse; + end if; + end process THE_ASYNC_SAMPLER_PROC; + +-- first two registers are clock domain transfer registers! + comb_async_pulse <= '1' when ( async_sampler(7 downto 2) = b"0000_00" ) else '0'; + +---------------------------------------------------------------- +-- +---------------------------------------------------------------- + THE_SYNC_PROC: process( CLK_IN ) + begin + if( rising_edge(CLK_IN) ) then + reset_pulse <= reset_pulse(0) & RESET_IN; + trb_reset_pulse <= trb_reset_pulse(0) & TRB_RESET_IN; + end if; + end process THE_SYNC_PROC; + +---------------------------------------------------------------- +-- one global reset counter +---------------------------------------------------------------- + THE_GLOBAL_RESET_PROC: process( CLK_IN ) + begin + if( rising_edge(CLK_IN) ) then + if( (async_pulse = '1') or (reset_pulse(1) = '1') or (trb_reset_pulse(1) = '1') ) then + reset_cnt <= (others => '0'); + elsif( reset_cnt(reset_cnt'left) = '0' ) then + reset_cnt <= reset_cnt + 1; + end if; + end if; + end process THE_GLOBAL_RESET_PROC; + + reset <= not reset_cnt(reset_cnt'left); + +---------------------------------------------------------------- +-- Output signals +---------------------------------------------------------------- + CLEAR_OUT <= not comb_async_rst_n; + RESET_OUT <= reset; + +end architecture reset_handler_arch; diff --git a/gbe_hub/trb3sc_gbe_hub.prj b/gbe_hub/trb3sc_gbe_hub.prj index 6dde03e..c2b3a24 100644 --- a/gbe_hub/trb3sc_gbe_hub.prj +++ b/gbe_hub/trb3sc_gbe_hub.prj @@ -50,8 +50,6 @@ impl -active "workdir" #################### - - #Packages add_file -vhdl -lib work "workdir/version.vhd" add_file -vhdl -lib work "config.vhd" @@ -63,18 +61,12 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" #Basic Infrastructure -add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" -add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" -add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" -add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" -add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" -add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" -add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_dcdc.vhd" +add_file -vhdl -lib work "../../trb3sc/gbe_hub/reset_handler.vhd" +add_file -vhdl -lib work "../../trb3sc/gbe_hub/clock_reset_handler.vhd" add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" -add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" - #Fifos add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" @@ -142,10 +134,6 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/main_tx_reset_RS.vh add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader_RS.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_all_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_125M_RS.vhd" -#add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_all_200M_RS.vhd" - #TrbNet Endpoint add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" @@ -222,20 +210,13 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_ add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" -#add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" -#add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" -#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" -#add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" -#add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" -#add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/media/serdes_gbe_4ch_ds.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/rx_rb.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/tx_fifo.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/forwarder.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_lsm.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/scatter_ports.vhd" -add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gather_ports.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/rx_rb.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/tx_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_lsm.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/scatter_ports.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gather_ports.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/rb_4k_9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd" @@ -243,7 +224,6 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/cores/fifo_4k_9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_raw.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb_ecp3/base/gbe_med_fifo.vhd" - add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" @@ -263,7 +243,6 @@ add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" - add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index a951fd7..29fd6d9 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -79,19 +79,18 @@ entity trb3sc_gbe_hub is end entity; architecture trb3sc_arch of trb3sc_gbe_hub is - attribute syn_keep : boolean; - attribute syn_preserve : boolean; + attribute syn_keep : boolean; + attribute syn_preserve : boolean; signal clk_sys : std_logic; - signal clk_full : std_logic; - signal clk_full_osc : std_logic; - signal GSR_N : std_logic; - signal clear : std_logic; + signal clear_i : std_logic; + signal clear_n_i : std_logic; signal reset_i : std_logic; + signal reset_n_i : std_logic; signal do_reboot_i : std_logic; signal reset_via_gbe : std_logic; signal reboot_from_gbe : std_logic; - + signal ctrlbus_rx, bustools_rx, busgbeip_rx, busgbereg_rx, bus_master_out : CTRLBUS_RX; signal ctrlbus_tx, bustools_tx, busgbeip_tx, busgbereg_tx, bus_master_in : CTRLBUS_TX; @@ -180,8 +179,49 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal port_sel : std_logic_vector(3 downto 1); + begin +-- SerDes usage: +-- backplane: A0 uplink on backplane, (A1, A2, A3 unused)MOD1 +-- B0, B1, B2, B3 downlink on hub addon +-- C0, C1, C2, C3 downlink on hub addon +-- D0, D1 downlink on TRB3sc, (D2, D3 unused) +-- +-- SFP: D0 uplink, (D1, D2, D3 unused) +-- A0, A1, A2, A3 downlink on backplane +-- B0, B1, B2, B3 unused +-- C0, C1, C2, C3 unused + +--------------------------------------------------------------------------- +-- Serdes Select +--------------------------------------------------------------------------- + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "11100100"; -- SFP2 on D1, Addon on B3 +-- PCSSW <= "01001110"; -- SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- + THE_CLOCK_RESET_HANDLER: entity clock_reset_handler + port map( + CLK_IN => CLK_SUPPL_PCLK, + GLOBAL_RESET_IN => '0', -- for sync operation + RESET_FROM_NET_IN => '0', -- unused + -- + CLK_OUT => clk_sys, + RESET_OUT => reset_i, + RESET_N_OUT => reset_n_i, + CLEAR_OUT => clear_i, + CLEAR_N_OUT => clear_n_i, + -- + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED(1), + LED_GREEN_OUT => LED_RJ_GREEN(1) + ); + --------------------------------------------------------------------------- -- PCSC is four ports downlink --------------------------------------------------------------------------- @@ -191,10 +231,10 @@ begin ) port map( RESET => reset_i, - GSR_N => GSR_N, - CLK_SYS => clk_sys, - CLK_125 => CLK_SUPPL_PCLK, - CLK_125_RX => open, + RESET_N => reset_n_i, + CLEAR => clear_i, + CLEAR_N => clear_n_i, + CLK_125 => clk_sys, -- SerDes 0 -- UPLINK -- FIFO interface RX FIFO_FULL_IN(0) => ul_rx_fifofull, @@ -277,8 +317,7 @@ begin -- scattering: data from uplink is distributed to downlinks THE_SCATTER: entity scatter_ports port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, + CLK => clk_sys, RESET => reset_i, -- FIFO_FULL_IN(3 downto 1) => dl_tx_fifofull(3 downto 1), @@ -293,8 +332,7 @@ begin THE_GATHER: entity gather_ports port map( - CLK => CLK_SUPPL_PCLK, - CLEAR => clear, + CLK => clk_sys, RESET => reset_i, -- FRAME_AVAIL_IN(3 downto 1) => dl_rx_frame_avail, @@ -339,50 +377,7 @@ begin DBG(30) <= '0'; DBG(31) <= '0'; DBG(32) <= '0'; - DBG(33) <= CLK_SUPPL_PCLK; - ---------------------------------------------------------------------------- --- Clock & Reset Handling ---------------------------------------------------------------------------- -THE_CLOCK_RESET : entity work.clock_reset_handler - port map( - INT_CLK_IN => CLK_CORE_PCLK, - EXT_CLK_IN => CLK_EXT_PLL_LEFT, - GLOBAL_RESET_IN => '0', - RESET_FROM_NET_IN => '0', - RESET_OUT => reset_i, - CLEAR_OUT => open, - GSR_OUT => GSR_N, - FULL_CLK_OUT => clk_full, - SYS_CLK_OUT => clk_sys, - REF_CLK_OUT => clk_full_osc, - ENPIRION_CLOCK => ENPIRION_CLOCK, - LED_RED_OUT => open, --LED_RJ_RED, - LED_GREEN_OUT => open, --LED_RJ_GREEN, - DEBUG_OUT => open - ); - - clear <= not GSR_N; - --- SerDes usage: --- backplane: A0 uplink on backplane, (A1, A2, A3 unused)MOD1 --- B0, B1, B2, B3 downlink on hub addon --- C0, C1, C2, C3 downlink on hub addon --- D0, D1 downlink on TRB3sc, (D2, D3 unused) --- --- SFP: D0 uplink, (D1, D2, D3 unused) --- A0, A1, A2, A3 downlink on backplane --- B0, B1, B2, B3 unused --- C0, C1, C2, C3 unused - ---------------------------------------------------------------------------- --- Serdes Select ---------------------------------------------------------------------------- - PCSSW_ENSMB <= '0'; - PCSSW_EQ <= x"0"; - PCSSW_PE <= x"F"; - PCSSW <= "11100100"; -- SFP2 on D1, Addon on B3 --- PCSSW <= "01001110"; -- SFP2 on B3, AddOn on D1 + DBG(33) <= clk_sys; --------------------------------------------------------------------------- -- GbE wrapper without med interface @@ -411,9 +406,9 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ) port map( CLK_SYS_IN => clk_sys, - CLK_125_IN => CLK_SUPPL_PCLK, + CLK_125_IN => clk_sys, RESET => reset_i, - GSR_N => GSR_N, + GSR_N => reset_n_i, -- Trigger TRIGGER_IN => '0', -- MAC @@ -639,8 +634,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler LED_RJ_GREEN(0) <= not status_raw(0 * 8 + 2); -- A0 LED_RJ_RED(0) <= not status_raw(0 * 8 + 5); - LED_RJ_GREEN(1) <= not '0'; - LED_RJ_RED(1) <= not '0'; +-- LED_RJ_GREEN(1) <= not '0'; +-- LED_RJ_RED(1) <= not '0'; --------------------------------------------------------------------------- @@ -652,10 +647,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ) port map( RESET => reset_i, - GSR_N => GSR_N, - CLK_SYS => clk_sys, - CLK_125 => CLK_SUPPL_PCLK, - CLK_125_RX => open, + GSR_N => reset_n_i, + CLK_125 => clk_sys, -- MAC status and config MAC_READY_CONF_OUT => open, MAC_RECONF_IN => (others => '0'), @@ -712,10 +705,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ) port map( RESET => reset_i, - GSR_N => GSR_N, - CLK_SYS => clk_sys, - CLK_125 => CLK_SUPPL_PCLK, - CLK_125_RX => open, + GSR_N => reset_n_i, + CLK_125 => clk_sys, -- MAC status and config MAC_READY_CONF_OUT(0) => mac_ready_conf, -- open, MAC_RECONF_IN(0) => mac_reconf, -- (others => '0'), @@ -772,10 +763,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler ) port map( RESET => reset_i, - GSR_N => GSR_N, - CLK_SYS => clk_sys, - CLK_125 => CLK_SUPPL_PCLK, - CLK_125_RX => open, + GSR_N => reset_n_i, + CLK_125 => clk_sys, -- MAC status and config MAC_READY_CONF_OUT => open, MAC_RECONF_IN => (others => '0'), @@ -828,8 +817,8 @@ THE_CLOCK_RESET : entity work.clock_reset_handler --------------------------------------------------------------------------- THE_MAIN_TX_RST: main_tx_reset_RS port map ( - CLEAR => clear, - CLK_REF => CLK_SUPPL_PCLK, + CLEAR => clear_i, + CLK_REF => clk_sys, TX_PLL_LOL_IN => tx_pll_lol_i, TX_CLOCK_AVAIL_IN => '1', -- not needed here TX_PCS_RST_CH_C_OUT => tx_pcs_rst_i, diff --git a/pinout/basic_constraints.lpf b/pinout/basic_constraints.lpf index 84cdd83..f9eb0be 100644 --- a/pinout/basic_constraints.lpf +++ b/pinout/basic_constraints.lpf @@ -9,18 +9,17 @@ BLOCK RD_DURING_WR_PATHS ; SYSCONFIG MCCLK_FREQ = 20; -FREQUENCY PORT CLK_CORE_PCLK 200 MHz; -FREQUENCY PORT CLK_CORE_PLL_LEFT 200 MHz; -FREQUENCY PORT CLK_CORE_PLL_RIGHT 200 MHz; +FREQUENCY PORT CLK_CORE_PCLK 200.0 MHz; +FREQUENCY PORT CLK_CORE_PLL_LEFT 200.0 MHz; +FREQUENCY PORT CLK_CORE_PLL_RIGHT 200.0 MHz; -FREQUENCY PORT CLK_SUPPL_PCLK 125 MHz; -FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125 MHz; -FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125 MHz; - -FREQUENCY PORT CLK_EXT_PCLK 200 MHz; -FREQUENCY PORT CLK_EXT_PLL_LEFT 200 MHz; -FREQUENCY PORT CLK_EXT_PLL_RIGHT 200 MHz; +FREQUENCY PORT CLK_SUPPL_PCLK 125.0 MHz; +FREQUENCY PORT CLK_SUPPL_PLL_LEFT 125.0 MHz; +FREQUENCY PORT CLK_SUPPL_PLL_RIGHT 125.0 MHz; +FREQUENCY PORT CLK_EXT_PCLK 200.0 MHz; +FREQUENCY PORT CLK_EXT_PLL_LEFT 200.0 MHz; +FREQUENCY PORT CLK_EXT_PLL_RIGHT 200.0 MHz; #If these signals do not exist, somebody messed around with the design... MULTICYCLE TO CELL "THE_TOOLS/THE_SPI_RELOAD_THE_SPI_MASTER_THE_SPI_SLIM_tx_sreg_oregio[*]" 20 ns; @@ -31,42 +30,6 @@ MULTICYCLE FROM CELL "THE_CLOCK_RESET/clear_n_i" 20 ns; MULTICYCLE FROM CELL "THE_CLOCK_RESET/THE_RESET_HANDLER/final_reset*" 30 ns; GSR_NET NET "GSR_N"; - -BLOCK PATH TO CELL "THE_TOOLS/gen_STATISTICS.THE_STAT_LOGIC/inp_reg*"; -BLOCK PATH FROM CELL "THE_TOOLS/gen_TRIG_LOGIC.THE_TRIG_LOGIC/inp_verylong*"; -BLOCK PATH TO CELL "THE_TOOLS/gen_TRIG_LOGIC.THE_TRIG_LOGIC/out_reg*"; - - -#BLOCK PATH FROM CLKNET "*/sci_read_i"; -#BLOCK PATH FROM CLKNET "*/sci_write_i"; - - -#MULTICYCLE TO CELL "*/sci*" 20 ns; -#MULTICYCLE FROM CELL "*/sci*" 20 ns; -#MULTICYCLE TO CELL "*/PROC_SCI_CTRL.wa*" 20 ns; -#BLOCK PATH TO CELL "*/sci_addr_*"; - -FREQUENCY NET "THE_MEDIA_INT*/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps -FREQUENCY NET "THE_MEDIA_INT*/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps - -# REGION "REGION_SPI" "R19C150D" 20 20 DEVSIZE; -# LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MASTER/SPI_group" REGION "REGION_SPI" ; -# LOCATE UGROUP "THE_TOOLS/THE_SPI_RELOAD/THE_SPI_MEMORY/SPI_group" REGION "REGION_SPI" ; - -#main serdes is PCSB for stand-alone or PCSA for crate operation -LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ; -LOCATE COMP "THE_MEDIA_INTERFACE/gen_pcs3.THE_SERDES/PCSD_INST" SITE "PCSB" ; -LOCATE COMP "THE_MEDIA_INTERFACE/THE_SERDES/PCSD_INST" SITE "PCSB" ; # needed for trb3sc_tdctemplate with DS -#REGION "MEDIA_UPLINK" "R96C107D" 19 24; -#REGION "MEDIA_UPLINK" "R96C55D" 19 24; -#LOCATE UGROUP "THE_MEDIA_INTERFACE/media_interface_group" REGION "MEDIA_UPLINK" ; - -##more space for media interface on backplane master -#LOCATE COMP "THE_MEDIA_INT_MIXED/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ; -#REGION "MEDIA_MIXED" "R95C50D" 20 70; -#LOCATE UGROUP "THE_MEDIA_INT_MIXED/media_interface_group" REGION "MEDIA_MIXED" ; - - BLOCK PATH TO PORT "LED*"; BLOCK PATH TO PORT "SFP*"; BLOCK PATH FROM PORT "SFP*"; diff --git a/scripts/compile.pl b/scripts/compile.pl index 5f46272..5751143 100755 --- a/scripts/compile.pl +++ b/scripts/compile.pl @@ -126,19 +126,14 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; $ENV{'SYNPLIFY_BINARY'}=$config{synplify_binary}; - - - - my $WORKDIR = "workdir"; unless(-d $WORKDIR) { mkdir $WORKDIR or die "can't create workdir '$WORKDIR': $!"; - system ("cd workdir; ../../../trb3/base/linkdesignfiles.sh; cd ..;"); + system ("cd workdir; ../linkdesignfiles.sh; cd ..;"); } system("ln -sfT $lattice_path $WORKDIR/lattice-diamond"); - if($con==1 || $all==1){ #create full lpf file print GREEN, "Generating constraints file...\n\n", RESET; -- 2.43.0