From 45d8d02d7147e75e6394fc03880ecb15ecbed5c0 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Mon, 10 Aug 2020 12:33:31 +0200 Subject: [PATCH] add trb_net_xdna to components so that it is not needed in every project --- trb_net16_endpoint_hades_full.vhd | 2 +- trb_net_components.vhd | 11 +++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index d2d2649..6bf80e7 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -661,7 +661,7 @@ begin REGIO_ONEWIRE_MONITOR_OUT <= '0'; REGIO_ONEWIRE_INOUT <= '0'; - XilinxDNA : entity work.trb_net_xdna + XilinxDNA : trb_net_xdna port map( CLK => CLK, RESET => RESET, diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 3823fe6..c40f48a 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -3598,5 +3598,16 @@ end component; ); end component; + component trb_net_xdna is + port ( + CLK : in std_logic; + RESET : in std_logic; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector( 2 downto 0); + WRITE_OUT : out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0) + ); +end component trb_net_xdna; end package; -- 2.43.0