From 460d7f6636173d560abda0e389f4761555c141d8 Mon Sep 17 00:00:00 2001
From: hadaq <hadaq>
Date: Fri, 4 Nov 2011 14:38:00 +0000
Subject: [PATCH] *** empty log message ***

---
 base/trb3_periph.lpf             | 5 -----
 base/trb3_periph_constraints.lpf | 7 ++++---
 2 files changed, 4 insertions(+), 8 deletions(-)

diff --git a/base/trb3_periph.lpf b/base/trb3_periph.lpf
index f126c9e..37f910c 100644
--- a/base/trb3_periph.lpf
+++ b/base/trb3_periph.lpf
@@ -8,11 +8,6 @@ BLOCK RD_DURING_WR_PATHS ;
 
   SYSCONFIG MCCLK_FREQ = 2.5;
 
-  FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
-  FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 100 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  125 MHz;
-
 #################################################################
 # Clock I/O
 #################################################################
diff --git a/base/trb3_periph_constraints.lpf b/base/trb3_periph_constraints.lpf
index 046f3fd..957482f 100644
--- a/base/trb3_periph_constraints.lpf
+++ b/base/trb3_periph_constraints.lpf
@@ -6,10 +6,11 @@ BLOCK RD_DURING_WR_PATHS ;
 # Basic Settings
 #################################################################
 
+  SYSCONFIG MCCLK_FREQ = 2.5;
   FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz;
   FREQUENCY PORT CLK_PCLK_LEFT  200 MHz;
-  FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz;
-  FREQUENCY PORT CLK_GPLL_LEFT  200 MHz;
+  FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz;
+  FREQUENCY PORT CLK_GPLL_LEFT  100 MHz;
 
   
 #################################################################
@@ -417,4 +418,4 @@ LOCATE UGROUP "FIFO_7" REGION "Region_2" ;
 #LOCATE UGROUP "FC_46" SITE "R98C72D" ;
 #UGROUP "FC_47" BBOX 1 48 
 #BLKNAME GEN_FC_47_FC;
-#LOCATE UGROUP "FC_47" SITE "R102C72D" ;
\ No newline at end of file
+#LOCATE UGROUP "FC_47" SITE "R102C72D" ;
-- 
2.43.0