From 463f1a35c309164c3e0900f652f50e73ab6dbf41 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 16 Oct 2015 18:07:07 +0200 Subject: [PATCH] Updating included features list, adding TRB3sc to board lists --- trb3/IncludedFeaturesTable.tex | 23 ++++++++--------------- trb3/Trb3GeneralRemarks.tex | 9 +++++---- trb3/Trb3scBasics.tex | 5 +++-- trb3/sctrladdresses.tex | 2 +- 4 files changed, 17 insertions(+), 22 deletions(-) diff --git a/trb3/IncludedFeaturesTable.tex b/trb3/IncludedFeaturesTable.tex index fc1b9df..4ee63b3 100644 --- a/trb3/IncludedFeaturesTable.tex +++ b/trb3/IncludedFeaturesTable.tex @@ -19,6 +19,9 @@ CTS registers. \\ & 22 & GbeMultBuf & GbE sctrl data can be split to multiple packets\\ & 23 & GbE & Contains a GbE module \\ & 26 -- 24 & Sfp & Number of SFP configured for TrbNet connections\\ + & 40 & Lcd & LCD Information display included\\ + & 41 & ReferenceTime & Reference Time Path 0: RJ-45 (default) 1: +Through Clock Manager (cbmtof only)\\ & 42 & Spi & Contains SPI on all relevant I/Os depending on AddOn board design\\ & 43 & Uart & Uart on RJ45\_CLOCK(4) (TTL)\\ & 47 -- 44 & InpMonitor & Monitoring of input signals. See register 0xcf8f for number of channels and number of fifos @@ -34,25 +37,17 @@ CTS registers. \\ & 11 -- 8 & DoubleEdge & Double edge setup: 0: single edge only, 1: same channel, 2: alternating channels, 3: same channel with stretcher \\ & 14 -- 12 & RingBuffer & Ring Buffer size: 0:12 words, 1:44 words, 2:76 -words, 3:108 words \\ +words, 3:108 words, 7:dynamic \\ & 15 & TDC & Contains a TDC \\ - & 17 -- 16 & ReadoutModule & Number of readout modules \\ - & 41 & ReferenceTime & Reference Time Path 0: RJ-45 (default) 1: -Through Clock Manager (cbmtof only)\\ - & 42 & Spi & Contains SPI on all relevant I/Os depending on AddOn board design\\ - & 43 & Uart & Contains an Uart\\ - & 47 -- 44 & InpMonitor & See table 1. Pinout should match the one of the TDC\\ - & 51 -- 48 & TrgModule & See table 1. Pinout should match the one of the TDC\\ - & 55 -- 52 & Clock & See table 1\\ + & 18 -- 16 & ReadoutModule & Number of readout modules minus 1 \\ + & 55 -- 40 & & See table 1\\ \hline\hline 3 & \multicolumn{3}{X|}{``MVD'' - For CBM-MVD designs.}\\ & 7 -- 0 & Sensors & Number of sensor inputs \\ & 11 -- 8 & Chains & Number of sensor chains \\ & 16 & Mode & Normal read-out (0), testmode (1) or selectable (2)\\ & 23 -- 20 & Type & Type of sensor. 0: M26\\ - & 42 & Spi & Contains SPI on all relevant I/Os depending on AddOn board design\\ - & 43 & Uart & Contains an Uart\\ - & 55 -- 52 & Clock & See table 1\\ + & 55 -- 40 & & See table 1\\ \hline\hline 4 & \multicolumn{3}{X|}{``ADC'' - For ADC AddOn designs.}\\ & 7 -- 0 & Frequency & ADC sampling frequency in MHz \\ @@ -60,8 +55,6 @@ Through Clock Manager (cbmtof only)\\ & 14 & Baseline & Baseline determination\\ & 15 & Trigger & Trigger generation\\ & 23 -- 16 & Channels & Number of channels\\ - & 42 & Spi & Contains SPI on all relevant I/Os depending on AddOn board design\\ - & 43 & Uart & Contains an Uart\\ - & 55 -- 52 & Clock & See table 1\\ + & 55 -- 40 & & See table 1\\ \hline \end{longtable} diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex index e288b45..015cdc9 100644 --- a/trb3/Trb3GeneralRemarks.tex +++ b/trb3/Trb3GeneralRemarks.tex @@ -131,7 +131,7 @@ All network addresses are of the form ABBC, where: \item BB is a number identifying the TRB in the full system. BB is equal on all 5 FPGA of one board. \end{itemize*} -The FPGA with the CTS has address C000 (in already existing systems also 8000). For data unpacking schemes see also \ref{Data_Unpacking}. +The FPGA with the CTS has address C000. For data unpacking schemes see also \ref{Data_Unpacking}. All boards of a given type are accessible by a broadcast address at the same time. This is set by \signal{Broadcast\_Special\_Addr} in the TrbNet endpoint: @@ -156,12 +156,13 @@ The initial address set with \signal{Regio\_Init\_Address} can be chosen from th \item 0xF305 for the peripheral FPGA \item 0xF30n for a design for FPGA n only \item 0xF3C0 default for a design with CTS - \item 0xF350 default for master Trb3sc - \item 0xF351 default for slave TRB3sc + \item 0xF3CC default for slave TRB3sc + \item 0xF3CD default for TRB3sc with hub AddOn + \item 0xF3CE default for crate master TRB3sc \end{itemize*} -\subsection{Testing Procedure for New Boards} +\subsection{Testing Procedure for New Trb3 Boards} \begin{itemize*} \item Visual Inspection \item Add sticker with serial number diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex index e1566ba..fb8ad43 100644 --- a/trb3/Trb3scBasics.tex +++ b/trb3/Trb3scBasics.tex @@ -46,8 +46,8 @@ HDR\_IO is available for any general purpose I/O. All lines are LVCMOS25. By def 4 & SPI MISO\\ 5 & SPI CLK\\ 6 & SPI CE\\ - 7 & \\ - 8 & \\ + 7 & (LCD DC)\\ + 8 & (LCD Reset)\\ 9 & \\ 10 & \\ 11 & 3.3V\\ @@ -60,6 +60,7 @@ HDR\_IO is available for any general purpose I/O. All lines are LVCMOS25. By def SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 8 is reserved for HDR\_IO. +Optionally, a LCD can be connected. In this case SPI channel 8 is not used. \subsubsection{Serial Links} By default, SFP1 is used for GbE, SFP2 for TrbNet. SFP2 must be removed if the board is to be used on a backplane as slave module. Removing the SFP selects the backpanel as TrbNet input. diff --git a/trb3/sctrladdresses.tex b/trb3/sctrladdresses.tex index cab5c8b..b0d0db7 100644 --- a/trb3/sctrladdresses.tex +++ b/trb3/sctrladdresses.tex @@ -10,7 +10,7 @@ 7000 -- 73FF & RDO & Readout status \\ 8000 -- 83FF & GbE & Ethernet registers \\ A000 -- BFFF & FEE & Thresholds, Pedestals, Settings \\ -B000 -- B3FF & Serdes & Serializer status (on hubs) \\ +B000 -- B7FF & Serdes & Serializer status (on hubs) \\ C000 -- CEFF & TDC & TDC Control and Status [\ref{TDC}] \\ CF00 -- CF7F & Trg & Trigger signal generation [\ref{triggermodule}]\\ CF80 -- CFFF & Inp & Input Monitoring [\ref{triggermodule}]\\ -- 2.43.0