From 467e1583cbed8ae349e49f9eed9f1a631eabd7f3 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Wed, 27 Mar 2013 19:09:03 +0000 Subject: [PATCH] new DQS block, ADC changed --- base/code/adc_ad9222.vhd | 8 ++++++-- base/cores/dqsinput.ipx | 8 ++++---- base/cores/dqsinput.lpc | 16 +++++++++------- base/cores/dqsinput.vhd | 10 ++++++---- base/cores/dqsinput1x4.ipx | 8 ++++---- base/cores/dqsinput1x4.lpc | 8 +++++--- base/cores/dqsinput1x4.vhd | 8 +++++--- base/trb3_periph_nxyter.lpf | 12 ++++++------ 8 files changed, 45 insertions(+), 33 deletions(-) diff --git a/base/code/adc_ad9222.vhd b/base/code/adc_ad9222.vhd index 077677f..eeb9494 100644 --- a/base/code/adc_ad9222.vhd +++ b/base/code/adc_ad9222.vhd @@ -186,8 +186,12 @@ end generate; end generate; end generate; -gen_outputs : for i in 0 to DEVICES-1 generate - FCO_OUT(i*CHANNELS*RESOLUTION+RESOLUTION-1 downto i*CHANNELS*RESOLUTION) <= cdt_data_out(i)(CHANNELS*RESOLUTION+RESOLUTION-1 downto CHANNELS*RESOLUTION); +gen_outputs_2 : if DEVICES = 2 generate + FCO_OUT <= cdt_data_out(1)(CHANNELS*12+11 downto CHANNELS*12) & cdt_data_out(0)(CHANNELS*12+11 downto CHANNELS*12); +end generate; + +gen_outputs_1 : if DEVICES = 1 generate + FCO_OUT <= cdt_data_out(0)(CHANNELS*12+11 downto CHANNELS*12); end generate; DATA_OUT <= data_buffer; diff --git a/base/cores/dqsinput.ipx b/base/cores/dqsinput.ipx index 21cc5c6..ddcdf14 100644 --- a/base/cores/dqsinput.ipx +++ b/base/cores/dqsinput.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/dqsinput.lpc b/base/cores/dqsinput.lpc index 5d74e90..326ccd1 100644 --- a/base/cores/dqsinput.lpc +++ b/base/cores/dqsinput.lpc @@ -12,12 +12,12 @@ VendorName=Lattice Semiconductor Corporation CoreType=LPM CoreStatus=Demo CoreName=DDR_GENERIC -CoreRevision=5.2 +CoreRevision=5.3 ModuleName=dqsinput SourceFormat=VHDL ParameterFileVersion=1.0 -Date=08/14/2012 -Time=16:40:21 +Date=03/27/2013 +Time=19:58:10 [Parameters] Verilog=0 @@ -28,16 +28,18 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 mode=Receive +trioddr=0 io_type=LVDS25 num_int=2 width=5 -freq_in=120 -bandwidth=1200 +freq_in=192 +bandwidth=1920 aligned=Centered pre-configuration=DISABLED mode2=Receive +trioddr2=0 io_type2=LVDS25 -freq_in2=120 +freq_in2=192 gear=2x aligned2=Centered num_int2=2 @@ -57,4 +59,4 @@ val= Phase=TRDLLB/DLLDELB Divider=CLKDIVB Multiplier=2 -PllFreq=60 +PllFreq=96 diff --git a/base/cores/dqsinput.vhd b/base/cores/dqsinput.vhd index 9dee3f3..9be81a0 100644 --- a/base/cores/dqsinput.vhd +++ b/base/cores/dqsinput.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_1.4_Production (87) --- Module Version: 5.2 ---/d/jspc29/lattice/diamond/1.4.2.105/ispfpga/bin/lin/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 120 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) +-- Module Version: 5.3 +--/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n dqsinput -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk dqs -dqs 1 5 -dqs 2 5 -e --- Tue Aug 14 16:40:21 2012 +-- Wed Mar 27 19:58:10 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -208,6 +208,8 @@ architecture Structure of dqsinput is attribute syn_keep : boolean; attribute syn_noprune : boolean; attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; begin -- component instantiation statements diff --git a/base/cores/dqsinput1x4.ipx b/base/cores/dqsinput1x4.ipx index 7b9f89c..4453282 100644 --- a/base/cores/dqsinput1x4.ipx +++ b/base/cores/dqsinput1x4.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/base/cores/dqsinput1x4.lpc b/base/cores/dqsinput1x4.lpc index 7a10cfc..1abcadc 100644 --- a/base/cores/dqsinput1x4.lpc +++ b/base/cores/dqsinput1x4.lpc @@ -17,7 +17,7 @@ ModuleName=dqsinput1x4 SourceFormat=VHDL ParameterFileVersion=1.0 Date=03/27/2013 -Time=18:21:05 +Time=19:56:56 [Parameters] Verilog=0 @@ -28,14 +28,16 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 mode=Receive +trioddr=0 io_type=LVDS25 -num_int=2 +num_int=1 width=5 -freq_in=120 +freq_in=192 bandwidth=1920 aligned=Centered pre-configuration=DISABLED mode2=Receive +trioddr2=0 io_type2=LVDS25 freq_in2=192 gear=2x diff --git a/base/cores/dqsinput1x4.vhd b/base/cores/dqsinput1x4.vhd index dd3fbb9..636ec12 100644 --- a/base/cores/dqsinput1x4.vhd +++ b/base/cores/dqsinput1x4.vhd @@ -1,8 +1,8 @@ --- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) +-- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 5.3 ---/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n dqsinput1x4 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk eclk -e +--/d/jspc29/lattice/diamond/2.1_x64/ispfpga/bin/lin64/scuba -w -n dqsinput1x4 -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type iol -mode in -io_type LVDS25 -width 5 -freq_in 192 -gear 2 -clk eclk -e --- Wed Mar 27 18:21:05 2013 +-- Wed Mar 27 19:56:56 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -102,6 +102,8 @@ architecture Structure of dqsinput1x4 is attribute syn_keep : boolean; attribute syn_noprune : boolean; attribute syn_noprune of Structure : architecture is true; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; begin -- component instantiation statements diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf index 2275f75..955f425 100644 --- a/base/trb3_periph_nxyter.lpf +++ b/base/trb3_periph_nxyter.lpf @@ -6,12 +6,12 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# - SYSCONFIG MCCLK_FREQ = 2.5; - - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; - FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; - FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; +# SYSCONFIG MCCLK_FREQ = 2.5; +# +# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; +# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; +# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; +# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Clock I/O -- 2.43.0