From 47701851906c7f468f7bddba92a0e29bd5d36225 Mon Sep 17 00:00:00 2001
From: Michael Boehmer <mboehmer@ph.tum.de>
Date: Mon, 11 Jul 2022 09:27:56 +0200
Subject: [PATCH] replaced parts of gbe_frame_constr

---
 gbe_trb/base/gbe_logic_wrapper.vhd          | 105 +--
 gbe_trb/base/trb_net16_gbe_frame_constr.vhd | 354 ++--------
 gbe_trb/base/trb_net16_gbe_frame_trans.vhd  | 198 ++----
 gbe_trb/base/trb_net16_gbe_main_control.vhd |   8 +-
 gbe_trb/base/trb_net_gbe_components.vhd     | 148 +----
 gbe_trb/base/tx_fifo.vhd                    |   4 +-
 gbe_trb_ecp3/base/gbe_med_fifo.vhd          |  22 +-
 gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd      | 703 ++++++++++++++++++++
 gbe_trb_ecp3/base/gbe_wrapper_raw.vhd       |  44 +-
 9 files changed, 921 insertions(+), 665 deletions(-)
 create mode 100644 gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd

diff --git a/gbe_trb/base/gbe_logic_wrapper.vhd b/gbe_trb/base/gbe_logic_wrapper.vhd
index fcab6cb..eabf21c 100644
--- a/gbe_trb/base/gbe_logic_wrapper.vhd
+++ b/gbe_trb/base/gbe_logic_wrapper.vhd
@@ -66,7 +66,10 @@ entity gbe_logic_wrapper is
     MAC_RX_STAT_EN_IN        : in  std_logic;
     MAC_RX_EOF_IN            : in  std_logic;
     MAC_RX_ERROR_IN          : in  std_logic;
-
+    -- FIFO TX stuff
+    FT_TX_DATA_OUT           : out std_logic_vector(8 downto 0);
+    FT_TX_WR_OUT             : out std_logic;
+    FT_TX_FIFOFULL_IN        : in  std_logic;
     -- CTS interface
     CTS_NUMBER_IN            : in  std_logic_vector(15 downto 0);
     CTS_CODE_IN              : in  std_logic_vector(7 downto 0);
@@ -217,9 +220,6 @@ architecture RTL of gbe_logic_wrapper is
   signal ft_data            : std_logic_vector(8 downto 0);
   signal ft_tx_empty        : std_logic;
   signal ft_start_of_packet : std_logic;
-  signal ft_bsm_init        : std_logic_vector(3 downto 0);
-  signal ft_bsm_mac         : std_logic_vector(3 downto 0);
-  signal ft_bsm_trans       : std_logic_vector(3 downto 0);
 
   signal gbe_cts_number           : std_logic_vector(15 downto 0);
   signal gbe_cts_code             : std_logic_vector(7 downto 0);
@@ -257,8 +257,6 @@ architecture RTL of gbe_logic_wrapper is
 
   signal dbg_hist, dbg_hist2    : hist_array;
   signal monitor_dropped        : std_logic_vector(31 downto 0);
-  signal dbg_ft                 : std_logic_vector(63 downto 0);
-  signal dbg_q                  : std_logic_vector(15 downto 0);
   signal make_reset             : std_logic;
   signal frame_pause            : std_logic_vector(31 downto 0);
 
@@ -726,75 +724,42 @@ begin
     )
     port map(
       -- ports for user logic
-      RESET                  => global_reset,
-      CLK                    => CLK_SYS_IN,
-      LINK_OK_IN             => '1',
+      RESET                   => global_reset,
+      CLK                     => CLK_SYS_IN,
+      LINK_OK_IN              => '1',
       --
-      WR_EN_IN               => fc_wr_en,
-      DATA_IN                => fc_data,
-      START_OF_DATA_IN       => fc_sod,
-      END_OF_DATA_IN         => fc_eod,
-      IP_F_SIZE_IN           => fc_ip_size,
-      UDP_P_SIZE_IN          => fc_udp_size,
-      HEADERS_READY_OUT      => fc_h_ready,
-      READY_OUT              => fc_ready,
-      DEST_MAC_ADDRESS_IN    => fc_dest_mac,
-      DEST_IP_ADDRESS_IN     => fc_dest_ip,
-      DEST_UDP_PORT_IN       => fc_dest_udp,
-      SRC_MAC_ADDRESS_IN     => fc_src_mac,
-      SRC_IP_ADDRESS_IN      => fc_src_ip,
-      SRC_UDP_PORT_IN        => fc_src_udp,
-      FRAME_TYPE_IN          => fc_type,
-      IHL_VERSION_IN         => fc_ihl_version,
-      TOS_IN                 => fc_tos,
-      IDENTIFICATION_IN      => fc_ident,
-      FLAGS_OFFSET_IN        => fc_flags_offset,
-      TTL_IN                 => fc_ttl,
-      PROTOCOL_IN            => fc_protocol,
-      FRAME_DELAY_IN         => frame_pause, --(others => '0'),
-      RD_CLK                 => CLK_125_IN,
-      FT_DATA_OUT            => ft_data,
-      FT_TX_EMPTY_OUT        => ft_tx_empty,
-      FT_TX_RD_EN_IN         => MAC_TX_READ_IN,
-      FT_START_OF_PACKET_OUT => ft_start_of_packet,
-      FT_TX_DONE_IN          => MAC_TX_DONE_IN,
-      FT_TX_DISCFRM_IN       => MAC_TX_DISCRFRM_IN,
-      MONITOR_TX_BYTES_OUT   => monitor_tx_bytes,
-      MONITOR_TX_FRAMES_OUT  => monitor_tx_frames
+      WR_EN_IN                => fc_wr_en,
+      DATA_IN                 => fc_data,
+      START_OF_DATA_IN        => fc_sod,
+      END_OF_DATA_IN          => fc_eod,
+      IP_F_SIZE_IN            => fc_ip_size,
+      UDP_P_SIZE_IN           => fc_udp_size,
+      HEADERS_READY_OUT       => fc_h_ready,
+      READY_OUT               => fc_ready,
+      DEST_MAC_ADDRESS_IN     => fc_dest_mac,
+      DEST_IP_ADDRESS_IN      => fc_dest_ip,
+      DEST_UDP_PORT_IN        => fc_dest_udp,
+      SRC_MAC_ADDRESS_IN      => fc_src_mac,
+      SRC_IP_ADDRESS_IN       => fc_src_ip,
+      SRC_UDP_PORT_IN         => fc_src_udp,
+      FRAME_TYPE_IN           => fc_type,
+      IHL_VERSION_IN          => fc_ihl_version,
+      TOS_IN                  => fc_tos,
+      IDENTIFICATION_IN       => fc_ident,
+      FLAGS_OFFSET_IN         => fc_flags_offset,
+      TTL_IN                  => fc_ttl,
+      PROTOCOL_IN             => fc_protocol,
+      FRAME_DELAY_IN          => frame_pause,
+      RD_CLK                  => CLK_125_IN,
+      FT_TX_DATA_OUT          => FT_TX_DATA_OUT, -- BUG
+      FT_TX_WR_OUT            => FT_TX_WR_OUT, -- BUG
+      FT_TX_FIFOFULL_IN       => FT_TX_FIFOFULL_IN, -- BUG
+      MONITOR_TX_BYTES_OUT    => monitor_tx_bytes,
+      MONITOR_TX_FRAMES_OUT   => monitor_tx_frames
     );
     
   frame_pause <= x"0000" & CFG_THROTTLE_PAUSE_IN;
 
-  MAC_TX_DATA_OUT <= ft_data(7 downto 0);
-
-  dbg_q(15 downto 9) <= (others => '0');
-
-  FRAME_TRANSMITTER : trb_net16_gbe_frame_trans
-    port map(
-      CLK                => CLK_SYS_IN,
-      RESET              => global_reset,
-      LINK_OK_IN         => link_ok,
-      TX_MAC_CLK         => CLK_125_IN,
-      TX_EMPTY_IN        => ft_tx_empty,
-      START_OF_PACKET_IN => ft_start_of_packet,
-      DATA_ENDFLAG_IN    => ft_data(8),
-      TX_FIFOAVAIL_OUT   => MAC_FIFOAVAIL_OUT,
-      TX_FIFOEOF_OUT     => MAC_FIFOEOF_OUT,
-      TX_FIFOEMPTY_OUT   => MAC_FIFOEMPTY_OUT,
-      TX_DONE_IN         => MAC_TX_DONE_IN,
-      TX_STAT_EN_IN      => MAC_TX_STAT_EN_IN,
-      TX_STATVEC_IN      => MAC_TX_STATS_IN,
-      TX_DISCFRM_IN      => MAC_TX_DISCRFRM_IN,
-      -- Debug
-      BSM_INIT_OUT       => ft_bsm_init,
-      BSM_MAC_OUT        => ft_bsm_mac,
-      BSM_TRANS_OUT      => ft_bsm_trans,
-      DBG_RD_DONE_OUT    => open,
-      DBG_INIT_DONE_OUT  => open,
-      DBG_ENABLED_OUT    => open,
-      DEBUG_OUT          => dbg_ft
-    );
-
   rx_enable_gen : if (RX_PATH_ENABLE = 1) generate
     RECEIVE_CONTROLLER : trb_net16_gbe_receive_control
       port map(
diff --git a/gbe_trb/base/trb_net16_gbe_frame_constr.vhd b/gbe_trb/base/trb_net16_gbe_frame_constr.vhd
index bf65129..6e91125 100755
--- a/gbe_trb/base/trb_net16_gbe_frame_constr.vhd
+++ b/gbe_trb/base/trb_net16_gbe_frame_constr.vhd
@@ -14,41 +14,38 @@ entity trb_net16_gbe_frame_constr is
 	);
 port( 
 	-- ports for user logic
-	RESET                   : in    std_logic;
-	CLK                     : in    std_logic;
-	LINK_OK_IN              : in    std_logic;  -- gk 03.08.10
+	RESET                   : in  std_logic;
+	CLK                     : in  std_logic;
+	LINK_OK_IN              : in  std_logic;  -- gk 03.08.10
 	--
-	WR_EN_IN                : in    std_logic;
-	DATA_IN                 : in    std_logic_vector(7 downto 0);
-	START_OF_DATA_IN        : in    std_logic;
-	END_OF_DATA_IN          : in    std_logic;
-	IP_F_SIZE_IN            : in    std_logic_vector(15 downto 0);
-	UDP_P_SIZE_IN           : in    std_logic_vector(15 downto 0); -- needed for fragmentation
-	HEADERS_READY_OUT       : out   std_logic;
-	READY_OUT               : out   std_logic;
-	DEST_MAC_ADDRESS_IN     : in    std_logic_vector(47 downto 0);
-	DEST_IP_ADDRESS_IN      : in    std_logic_vector(31 downto 0);
-	DEST_UDP_PORT_IN        : in    std_logic_vector(15 downto 0);
-	SRC_MAC_ADDRESS_IN      : in    std_logic_vector(47 downto 0);
-	SRC_IP_ADDRESS_IN       : in    std_logic_vector(31 downto 0);
-	SRC_UDP_PORT_IN         : in    std_logic_vector(15 downto 0);
-	FRAME_TYPE_IN           : in    std_logic_vector(15 downto 0);
-	IHL_VERSION_IN          : in    std_logic_vector(7 downto 0);
-	TOS_IN                  : in    std_logic_vector(7 downto 0);
-	IDENTIFICATION_IN       : in    std_logic_vector(15 downto 0);
-	FLAGS_OFFSET_IN         : in    std_logic_vector(15 downto 0);
-	TTL_IN                  : in    std_logic_vector(7 downto 0);
-	PROTOCOL_IN             : in    std_logic_vector(7 downto 0);
-	FRAME_DELAY_IN          : in    std_logic_vector(31 downto 0);  -- gk 09.12.10
+	WR_EN_IN                : in  std_logic;
+	DATA_IN                 : in  std_logic_vector(7 downto 0);
+	START_OF_DATA_IN        : in  std_logic;
+	END_OF_DATA_IN          : in  std_logic;
+	IP_F_SIZE_IN            : in  std_logic_vector(15 downto 0);
+	UDP_P_SIZE_IN           : in  std_logic_vector(15 downto 0); -- needed for fragmentation
+	HEADERS_READY_OUT       : out std_logic;
+	READY_OUT               : out std_logic;
+	DEST_MAC_ADDRESS_IN     : in  std_logic_vector(47 downto 0);
+	DEST_IP_ADDRESS_IN      : in  std_logic_vector(31 downto 0);
+	DEST_UDP_PORT_IN        : in  std_logic_vector(15 downto 0);
+	SRC_MAC_ADDRESS_IN      : in  std_logic_vector(47 downto 0);
+	SRC_IP_ADDRESS_IN       : in  std_logic_vector(31 downto 0);
+	SRC_UDP_PORT_IN         : in  std_logic_vector(15 downto 0);
+	FRAME_TYPE_IN           : in  std_logic_vector(15 downto 0);
+	IHL_VERSION_IN          : in  std_logic_vector(7 downto 0);
+	TOS_IN                  : in  std_logic_vector(7 downto 0);
+	IDENTIFICATION_IN       : in  std_logic_vector(15 downto 0);
+	FLAGS_OFFSET_IN         : in  std_logic_vector(15 downto 0);
+	TTL_IN                  : in  std_logic_vector(7 downto 0);
+	PROTOCOL_IN             : in  std_logic_vector(7 downto 0);
+	FRAME_DELAY_IN          : in  std_logic_vector(31 downto 0);  -- gk 09.12.10
 	-- ports for packetTransmitter
-	RD_CLK                  : in    std_logic; -- 125MHz clock!!!
-	FT_DATA_OUT             : out   std_logic_vector(8 downto 0);
-	FT_TX_EMPTY_OUT         : out   std_logic;
-	FT_TX_RD_EN_IN          : in    std_logic;
-	FT_START_OF_PACKET_OUT  : out   std_logic;
-	FT_TX_DONE_IN           : in    std_logic;
-	FT_TX_DISCFRM_IN	: in	std_logic;
-	
+	RD_CLK                  : in  std_logic; -- 125MHz clock!!!
+	FT_TX_DATA_OUT          : out std_logic_vector(8 downto 0);
+	FT_TX_WR_OUT            : out std_logic;
+	FT_TX_FIFOFULL_IN       : in  std_logic;
+	--
 	MONITOR_TX_BYTES_OUT    : out std_logic_vector(31 downto 0);
 	MONITOR_TX_FRAMES_OUT   : out std_logic_vector(31 downto 0)
 );
@@ -56,77 +53,34 @@ end trb_net16_gbe_frame_constr;
 
 architecture trb_net16_gbe_frame_constr of trb_net16_gbe_frame_constr is
 
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_frame_constr : architecture  is "GBE_LINK_group";
-
-component fifo_4096x9 is --fifo_8kx9 is
-port( 
-	Data    : in    std_logic_vector(8 downto 0);
-	WrClock : in    std_logic;
-	RdClock : in    std_logic;
-	WrEn    : in    std_logic;
-	RdEn    : in    std_logic;
-	Reset   : in    std_logic;
-	RPReset : in    std_logic;
-	Q       : out   std_logic_vector(8 downto 0);
-	Empty   : out   std_logic;
-	Full    : out   std_logic
-);
-end component;
-
-component fifo_8kx9 is
-port( 
-	Data    : in    std_logic_vector(8 downto 0);
-	WrClock : in    std_logic;
-	RdClock : in    std_logic;
-	WrEn    : in    std_logic;
-	RdEn    : in    std_logic;
-	Reset   : in    std_logic;
-	RPReset : in    std_logic;
-	Q       : out   std_logic_vector(8 downto 0);
-	Empty   : out   std_logic;
-	Full    : out   std_logic
-);
-end component;
-
 attribute syn_encoding      : string;
 
 type constructStates    is  (IDLE, DEST_MAC_ADDR, SRC_MAC_ADDR, FRAME_TYPE_S, VERSION,
-							 TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,
-							 SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,
-							 UDP_CS, SAVE_DATA, CLEANUP, DELAY);
+                TOS_S, IP_LENGTH, IDENT, FLAGS, TTL_S, PROTO, HEADER_CS,
+                SRC_IP_ADDR, DEST_IP_ADDR, SRC_PORT, DEST_PORT, UDP_LENGTH,
+                UDP_CS, SAVE_DATA, CLEANUP, DELAY);
 signal constructCurrentState, constructNextState : constructStates;
 signal bsm_constr           : std_logic_vector(7 downto 0);
 attribute syn_encoding of constructCurrentState: signal is "onehot";
 
-type transmitStates     is  (T_IDLE, T_LOAD, T_TRANSMIT, T_PAUSE, T_CLEANUP);
-signal transmitCurrentState, transmitNextState : transmitStates;
-attribute syn_encoding of transmitCurrentState : signal is "onehot";
-
-signal bsm_trans            : std_logic_vector(3 downto 0);
-
 signal headers_int_counter  : integer range 0 to 6;
 signal fpf_data             : std_logic_vector(7 downto 0);
 signal fpf_empty            : std_logic;
 signal fpf_full             : std_logic;
 signal fpf_wr_en            : std_logic;
 signal fpf_rd_en            : std_logic;
+signal fpf_rd_en_q          : std_logic;
 signal fpf_q                : std_logic_vector(8 downto 0);
 signal ip_size              : std_logic_vector(15 downto 0);
 signal ip_checksum          : std_logic_vector(31 downto 0);
 signal udp_size             : std_logic_vector(15 downto 0);
 signal udp_checksum         : std_logic_vector(15 downto 0);
-signal ft_sop               : std_logic;
 signal put_udp_headers      : std_logic;
-signal ready_frames_ctr     : std_logic_vector(15 downto 0) := x"0000";
-signal sent_frames_ctr      : std_logic_vector(15 downto 0) := x"0000";
-signal debug                : std_logic_vector(63 downto 0);
 signal ready                : std_logic;
 signal headers_ready        : std_logic;
 
 signal cur_max : integer range 0 to 10;
 
-signal ready_frames_ctr_q   : std_logic_vector(15 downto 0) := x"0000";
 signal ip_cs_temp_right     : std_logic_vector(15 downto 0); -- gk 29.03.10
 
 signal fpf_reset            : std_logic;  -- gk 01.01.01
@@ -144,36 +98,35 @@ begin
 
 -- Fakes
 udp_checksum  <= x"0000";  -- no checksum test needed
---debug         <= (others => '0');
 
 process(CLK)
 begin
-	if rising_edge(CLK) then
-		if constructCurrentState = IDLE then
-			ready <= '1';
-		else
-			ready <= '0';
-		end if;
-		
-		if (constructCurrentState = SAVE_DATA) then
-			headers_ready <= '1';
-		else
-			headers_ready <= '0';
-		end if;
-	end if;
+if rising_edge(CLK) then
+  if constructCurrentState = IDLE then
+    ready <= '1';
+  else
+    ready <= '0';
+  end if;
+
+  if (constructCurrentState = SAVE_DATA) then
+    headers_ready <= '1';
+  else
+    headers_ready <= '0';
+  end if;
+end if;
 end process;
-					 
+      
 sizeProc: process(CLK)
 begin
-	if rising_edge(CLK) then
-		if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then
-			ip_size  <= IP_F_SIZE_IN + x"14" + x"8";
-			udp_size <= UDP_P_SIZE_IN + x"8";
-		else
-			ip_size  <= IP_F_SIZE_IN + x"14";
-			udp_size <= UDP_P_SIZE_IN;
-		end if;
-	end if;
+  if rising_edge(CLK) then
+    if( put_udp_headers = '1' ) and (DEST_UDP_PORT_IN /= x"0000") then
+      ip_size  <= IP_F_SIZE_IN + x"14" + x"8";
+      udp_size <= UDP_P_SIZE_IN + x"8";
+    else
+      ip_size  <= IP_F_SIZE_IN + x"14";
+      udp_size <= UDP_P_SIZE_IN;
+    end if;
+  end if;
 end process sizeProc;
 
 ipCsProc : process(CLK)
@@ -400,8 +353,6 @@ begin
 	end if;
 end process headersIntProc;
 
-
-
 putUdpHeadersProc : process(CLK)
 begin
 	if rising_edge(CLK) then
@@ -457,193 +408,22 @@ begin
 	end case;
 end process fpfDataProc;
 
-syncProc : process(CLK)
+syncProc : process( CLK )
 begin
-	if rising_edge(CLK) then
-		fpf_data_q  <= fpf_data;
-		fpf_wr_en_q <= fpf_wr_en;
-		fpf_eod     <= END_OF_DATA_IN;
-	end if;
+  if rising_edge(CLK) then
+    fpf_data_q  <= fpf_data;
+    fpf_wr_en_q <= fpf_wr_en;
+    fpf_eod     <= END_OF_DATA_IN;
+  end if;
 end process syncProc;
-		
-
-
-readyFramesCtrProc: process( CLK )
-begin
-	if rising_edge(CLK) then
-		if (LINK_OK_IN = '0') then  -- gk 01.10.10
-			ready_frames_ctr <= (others => '0');
-		elsif (constructCurrentState = CLEANUP) then
-			ready_frames_ctr <= ready_frames_ctr + 1;
-		else
-			ready_frames_ctr <= ready_frames_ctr;
-		end if;
-	end if;
-end process readyFramesCtrProc;
-
-fpfResetProc : process(CLK)
-begin
-	if rising_edge(CLK) then
-		if (LINK_OK_IN = '0' or RESET = '1') then
-			fpf_reset <= '1';
-		else
-			fpf_reset <= '0';
-		end if;
-	end if;
-end process fpfResetProc;
---fpf_reset <= '1' when (RESET = '1') or (LINK_OK_IN = '0') else '0';  -- gk 01.10.10
-
-
-fpf_4k_gen : if FRAME_BUFFER_SIZE = 1 generate
-	FINAL_PACKET_FIFO: fifo_4096x9
-	port map( 
-		Data(7 downto 0)    => fpf_data_q,
-		Data(8)             => fpf_eod, --END_OF_DATA_IN,
-		WrClock             => CLK,
-		RdClock             => RD_CLK,
-		WrEn                => fpf_wr_en_q,
-		RdEn                => fpf_rd_en, --FT_TX_RD_EN_IN,
-		Reset               => fpf_reset,
-		RPReset             => fpf_reset,
-		Q                   => fpf_q,
-		Empty               => fpf_empty,
-		Full                => fpf_full
-	);
-end generate fpf_4k_gen;
-
-fpf_8k_gen : if FRAME_BUFFER_SIZE = 2 generate
-	FINAL_PACKET_FIFO: fifo_8kx9
-	port map( 
-		Data(7 downto 0)    => fpf_data_q,
-		Data(8)             => fpf_eod, --END_OF_DATA_IN,
-		WrClock             => CLK,
-		RdClock             => RD_CLK,
-		WrEn                => fpf_wr_en_q,
-		RdEn                => fpf_rd_en, --FT_TX_RD_EN_IN,
-		Reset               => fpf_reset,
-		RPReset             => fpf_reset,
-		Q                   => fpf_q,
-		Empty               => fpf_empty,
-		Full                => fpf_full
-	);
-end generate fpf_8k_gen;
-
-fpf_rd_en <= '1' when ((link_ok_125 = '1') and (FT_TX_RD_EN_IN = '1'))
-		    or (link_ok_125 = '0')  -- clear the fifo if link is down
-		    else '0';
-
-transferToRdClock : signal_sync
-	generic map(
-	  DEPTH => 2,
-	  WIDTH => 16
-	  )
-	port map(
-	  RESET    => RESET,
-	  D_IN     => ready_frames_ctr,
-	  CLK0     => RD_CLK, --CLK,
-	  CLK1     => RD_CLK,
-	  D_OUT    => ready_frames_ctr_q
-	  );
-
-process(RD_CLK)
-begin
-	if rising_edge(RD_CLK) then
-		link_ok_q <= LINK_OK_IN;
-		link_ok_125 <= link_ok_q;
-	end if;
-end process;
-
-transmitMachineProc: process( RD_CLK, RESET )
-begin
-	if RESET = '1' then
-		transmitCurrentState <= T_IDLE;
-	elsif( rising_edge(RD_CLK) ) then
-		if (link_ok_125 = '0') then  -- gk 01.10.10
-			transmitCurrentState <= T_IDLE;
-		else
-			transmitCurrentState <= transmitNextState;
-		end if;
-	end if;
-end process transmitMachineProc;
-
-transmitMachine: process( transmitCurrentState, fpf_q, FT_TX_DONE_IN, sent_frames_ctr, link_ok_125, ready_frames_ctr_q, FT_TX_DISCFRM_IN )
-begin
-	case transmitCurrentState is
-		when T_IDLE =>
-			bsm_trans <= x"0";
-			if( (sent_frames_ctr /= ready_frames_ctr_q) ) then
-				transmitNextState <= T_LOAD;
-			else
-				transmitNextState <= T_IDLE;
-			end if;
-		when T_LOAD =>
-			bsm_trans <= x"1";
-			if( fpf_q(8) = '1' ) then
-				transmitNextState <= T_TRANSMIT;
-			else
-				transmitNextState <= T_LOAD;
-			end if;
-		when T_TRANSMIT =>
-			bsm_trans <= x"2";
-			-- gk 03.08.10
-			if ((link_ok_125 = '1') and ((FT_TX_DONE_IN = '1') or (FT_TX_DISCFRM_IN = '1')))then
-				transmitNextState <= T_CLEANUP;
-			elsif (link_ok_125 = '0') then
-				transmitNextState <= T_PAUSE;
-			else
-				transmitNextState <= T_TRANSMIT;
-			end if;
-		when T_PAUSE =>
-			transmitNextState <= T_CLEANUP;
-		when T_CLEANUP =>
-			bsm_trans <= x"3";
-			transmitNextState <= T_IDLE;
-		when others =>
-			bsm_trans <= x"f";
-			transmitNextState <= T_IDLE;
-	end case;
-end process transmitMachine;
-
-
 
-sopProc: process( RD_CLK )
-begin
-	if rising_edge(RD_CLK) then
-		if (link_ok_125 = '0') then  -- gk 01.10.10
-			ft_sop <= '0';
-		elsif ((transmitCurrentState = T_IDLE) and (sent_frames_ctr /= ready_frames_ctr_q)) then
-			ft_sop <= '1';
-		else
-			ft_sop <= '0';
-		end if;
-	end if;
-end process sopProc;
+FT_TX_DATA_OUT(7 downto 0) <= fpf_data_q;
+FT_TX_DATA_OUT(8)          <= fpf_eod;
+FT_TX_WR_OUT               <= fpf_wr_en_q;
 
-sentFramesCtrProc: process( RD_CLK )
-begin
-	if rising_edge(RD_CLK) then
-		if (LINK_OK_IN = '0') then  -- gk 01.10.10
-			sent_frames_ctr <= (others => '0');
-			mon_sent_frames <= (others => '0');
-		elsif( FT_TX_DONE_IN = '1' ) or (FT_TX_DISCFRM_IN = '1') then
-			sent_frames_ctr <= sent_frames_ctr + 1;
-			mon_sent_frames <= mon_sent_frames + x"1";
-		else
-			sent_frames_ctr <= sent_frames_ctr;
-			mon_sent_frames <= mon_sent_frames;
-		end if;
-	end if;
-end process sentFramesCtrProc;
-
-
-
-FT_DATA_OUT            <= fpf_q;
-FT_TX_EMPTY_OUT        <= fpf_empty;
-FT_START_OF_PACKET_OUT <= ft_sop;
 READY_OUT              <= ready;
 HEADERS_READY_OUT      <= headers_ready;
 
-	
 MONITOR_TX_BYTES_OUT    <= mon_sent_bytes;
 MONITOR_TX_FRAMES_OUT   <= mon_sent_frames;
 
@@ -660,4 +440,4 @@ begin
 	end if;
 end process;
 
-end trb_net16_gbe_frame_constr;
\ No newline at end of file
+end trb_net16_gbe_frame_constr;
diff --git a/gbe_trb/base/trb_net16_gbe_frame_trans.vhd b/gbe_trb/base/trb_net16_gbe_frame_trans.vhd
index 19dade8..dfa50c1 100755
--- a/gbe_trb/base/trb_net16_gbe_frame_trans.vhd
+++ b/gbe_trb/base/trb_net16_gbe_frame_trans.vhd
@@ -10,118 +10,70 @@ use work.trb_net16_hub_func.all;
 
 entity trb_net16_gbe_frame_trans is
 port (
-	CLK					: in	std_logic;
-	RESET				: in	std_logic;
-	LINK_OK_IN              : in    std_logic;  -- gk 03.08.10
-	TX_MAC_CLK			: in	std_logic;
-	TX_EMPTY_IN			: in	std_logic;
-	START_OF_PACKET_IN	: in	std_logic;
-	DATA_ENDFLAG_IN		: in	std_logic; -- (8) is end flag, rest is only for TSMAC
-
-	TX_FIFOAVAIL_OUT	: out	std_logic;
-	TX_FIFOEOF_OUT		: out	std_logic;
-	TX_FIFOEMPTY_OUT	: out	std_logic;
-	TX_DONE_IN			: in	std_logic;
-	TX_STAT_EN_IN		: in	std_logic;
-	TX_STATVEC_IN		: in	std_logic_vector(30 downto 0);
-	TX_DISCFRM_IN		:	in std_logic;
-	-- Debug
-	BSM_INIT_OUT		: out	std_logic_vector(3 downto 0);
-	BSM_MAC_OUT			: out	std_logic_vector(3 downto 0);
-	BSM_TRANS_OUT		: out	std_logic_vector(3 downto 0);
-	DBG_RD_DONE_OUT		: out	std_logic;
-	DBG_INIT_DONE_OUT	: out	std_logic;
-	DBG_ENABLED_OUT		: out	std_logic;
-	DEBUG_OUT			: out	std_logic_vector(63 downto 0)
+  CLK                : in  std_logic;
+  RESET              : in  std_logic;
+  LINK_OK_IN         : in  std_logic;  -- gk 03.08.10
+  TX_MAC_CLK         : in  std_logic;
+  TX_EMPTY_IN        : in  std_logic;
+  START_OF_PACKET_IN : in  std_logic;
+  DATA_ENDFLAG_IN    : in  std_logic; -- (8) is end flag, rest is only for TSMAC
+  
+  TX_FIFOAVAIL_OUT   : out std_logic;
+  TX_FIFOEOF_OUT     : out std_logic;
+  TX_FIFOEMPTY_OUT   : out std_logic;
+  TX_DONE_IN         : in  std_logic;
+  TX_STAT_EN_IN      : in  std_logic;
+  TX_STATVEC_IN      : in  std_logic_vector(30 downto 0);
+  TX_DISCFRM_IN      : in  std_logic;
+  -- Debug
+  BSM_INIT_OUT       : out std_logic_vector(3 downto 0);
+  BSM_MAC_OUT        : out std_logic_vector(3 downto 0);
+  BSM_TRANS_OUT      : out std_logic_vector(3 downto 0);
+  DBG_RD_DONE_OUT    : out std_logic;
+  DBG_INIT_DONE_OUT  : out std_logic;
+  DBG_ENABLED_OUT    : out std_logic;
+  DEBUG_OUT          : out std_logic_vector(63 downto 0)
 );
 end trb_net16_gbe_frame_trans;
 
--- FifoRd ?!?
-
 architecture trb_net16_gbe_frame_trans of trb_net16_gbe_frame_trans is
 
---attribute HGROUP : string;
---attribute HGROUP of trb_net16_gbe_frame_trans : architecture  is "GBE_BUF_group";
-
-component mac_init_mem is
-port (
-	Address		: in	std_logic_vector(5 downto 0); 
-	OutClock	: in	std_logic; 
-	OutClockEn	: in	std_logic; 
-	Reset		: in	std_logic; 
-	Q			: out	std_logic_vector(7 downto 0)
-);
-end component;
-
 attribute syn_encoding	: string;
 
-type macInitStates is (I_IDLE, I_INCRADDRESS, I_PAUSE, I_WRITE, I_PAUSE2, I_READ, I_PAUSE3, I_ENDED);
-signal macInitState, macInitNextState : macInitStates;
-attribute syn_encoding of macInitState: signal is "onehot";
-signal bsm_init			: std_logic_vector(3 downto 0);
-	
-type macStates is (M_RESETING, M_IDLE, M_INIT);
-signal macCurrentState, macNextState : macStates;
-attribute syn_encoding of macCurrentState : signal is "onehot";
-signal bsm_mac			: std_logic_vector(3 downto 0);
-	
 type transmitStates is (T_IDLE, T_TRANSMIT, T_WAITFORFIFO);
 signal transmitCurrentState, transmitNextState : transmitStates;
 attribute syn_encoding of transmitCurrentState: signal is "onehot";
-signal bsm_trans		: std_logic_vector(3 downto 0);
-
-signal tx_fifoavail_i	: std_logic;
-signal tx_fifoeof_i		: std_logic;
-
--- host interface signals
-signal hcs_n_i			: std_logic;
-signal hwrite_n_i		: std_logic;
-signal hread_n_i 		: std_logic;
-
--- MAC INITIALIZATION signals
-signal macInitMemAddr	: std_logic_vector(5 downto 0);
-signal macInitMemQ		: std_logic_vector(7 downto 0);
-signal macInitMemEn		: std_logic;
-signal reading_done		: std_logic;
-signal init_done		: std_logic;
-signal enabled			: std_logic;
-signal addrSig			: std_logic_vector(5 downto 0);
-signal addr2			: std_logic_vector(5 downto 0);
-signal resetAddr		: std_logic;
-
-signal FifoEmpty		: std_logic;
-signal debug			: std_logic_vector(63 downto 0);
-signal sent_ctr                 : std_logic_vector(31 downto 0);
-signal link_ok_125      : std_logic;
+signal bsm_trans      : std_logic_vector(3 downto 0);
+
+signal tx_fifoavail_i : std_logic;
+signal tx_fifoeof_i   : std_logic;
+
+signal fifoempty      : std_logic;
+signal link_ok_125    : std_logic;
 
 begin
 
 linkOkSync : pulse_sync
 port map(
-	CLK_A_IN    => CLK,
-	RESET_A_IN  => RESET,
-	PULSE_A_IN  => LINK_OK_IN,
-	CLK_B_IN    => TX_MAC_CLK,
-	RESET_B_IN  => RESET,
-	PULSE_B_OUT => link_ok_125
+  CLK_A_IN    => CLK,
+  RESET_A_IN  => RESET,
+  PULSE_A_IN  => LINK_OK_IN,
+  CLK_B_IN    => TX_MAC_CLK,
+  RESET_B_IN  => RESET,
+  PULSE_B_OUT => link_ok_125
 );
 
--- Fakes
-debug(63 downto 32) <= (others => '0');
---debug(31 downto 0)  <= sent_ctr;
-
-
-TransmitStateMachineProc : process (TX_MAC_CLK, reset)
+TransmitStateMachineProc : process( TX_MAC_CLK, RESET )
 begin
-	if RESET = '1' then
-		transmitCurrentState <= T_IDLE;
-	elsif rising_edge(TX_MAC_CLK) then
-		if (LINK_OK_IN = '0') then -- gk 01.10.10
-			transmitCurrentState <= T_IDLE;
-		else
-			transmitCurrentState <= transmitNextState;
-		end if;
-	end if;
+  if RESET = '1' then
+    transmitCurrentState <= T_IDLE;
+  elsif rising_edge(TX_MAC_CLK) then
+    if (LINK_OK_IN = '0') then -- gk 01.10.10
+      transmitCurrentState <= T_IDLE;
+    else
+      transmitCurrentState <= transmitNextState;
+   end if;
+ end if;
 end process TransmitStatemachineProc;
 
 TransmitStateMachine : process (transmitCurrentState, START_OF_PACKET_IN, DATA_ENDFLAG_IN, TX_DONE_IN, TX_DISCFRM_IN)
@@ -167,60 +119,34 @@ begin
 	end if;
 end process FifoAvailProc;
 
-FifoEmptyProc : process(transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, LINK_OK_IN)
+FifoEmptyProc : process( transmitCurrentState, START_OF_PACKET_IN, TX_EMPTY_IN, LINK_OK_IN )
 begin
-	if (LINK_OK_IN = '0') then -- gk 01.10.10
-		FifoEmpty <= '1';
-	elsif    (transmitCurrentState = T_WAITFORFIFO) then
-		FifoEmpty <= '1';
-	elsif (transmitCurrentState = T_TRANSMIT) then
-		FifoEmpty <= TX_EMPTY_IN;
+	if   ( LINK_OK_IN = '0' ) then -- gk 01.10.10
+		fifoempty <= '1';
+	elsif( transmitCurrentState = T_WAITFORFIFO ) then
+		fifoempty <= '1';
+	elsif( transmitCurrentState = T_TRANSMIT ) then
+		fifoempty <= TX_EMPTY_IN;
 	elsif (((transmitCurrentState = T_IDLE) or (transmitCurrentState = T_WAITFORFIFO)) and (START_OF_PACKET_IN = '1')) then
-		FifoEmpty <= '0';
+		fifoempty <= '0';
 	else
-		FifoEmpty <= '1';
+		fifoempty <= '1';
 	end if;
 end process FifoEmptyProc;
 
 tx_fifoeof_i <= '1' when ((DATA_ENDFLAG_IN = '1') and (transmitCurrentState = T_TRANSMIT)) 
 					else '0';
-					
-SENT_CTR_PROC : process(TX_MAC_CLK, RESET)
-begin
-	if (RESET = '1') then
-			sent_ctr <= (others => '0');
-	elsif rising_edge(TX_MAC_CLK) then
-		if (TX_DONE_IN = '1') and (TX_STAT_EN_IN = '1') and (TX_STATVEC_IN(0) = '1')  then
-			sent_ctr <= sent_ctr + x"1";
-		else
-			sent_ctr <= sent_ctr;
-		end if;
-	end if;
-end process SENT_CTR_PROC;
-
-sync1 : signal_sync
-generic map(
-	WIDTH => 32,
-	DEPTH => 2
-)
-port map (
-	RESET => RESET,
-	CLK0  => CLK,
-	CLK1  => CLK,
-	D_IN  => sent_ctr,
-	D_OUT => debug(31 downto 0)
-);
 
 TX_FIFOAVAIL_OUT   <= tx_fifoavail_i;
 TX_FIFOEOF_OUT     <= tx_fifoeof_i;
-TX_FIFOEMPTY_OUT   <= FifoEmpty;
+TX_FIFOEMPTY_OUT   <= fifoempty;
 
-BSM_INIT_OUT       <= bsm_init;
-BSM_MAC_OUT        <= bsm_mac;
+BSM_INIT_OUT       <= (others => '0');
+BSM_MAC_OUT        <= (others => '0');
 BSM_TRANS_OUT      <= bsm_trans;
-DBG_RD_DONE_OUT    <= reading_done;
-DBG_INIT_DONE_OUT  <= init_done;
-DBG_ENABLED_OUT    <= enabled;
-DEBUG_OUT          <= debug;
+DBG_RD_DONE_OUT    <= '0';
+DBG_INIT_DONE_OUT  <= '0';
+DBG_ENABLED_OUT    <= '0';
+DEBUG_OUT          <= (others => '0');
 
 end trb_net16_gbe_frame_trans;
diff --git a/gbe_trb/base/trb_net16_gbe_main_control.vhd b/gbe_trb/base/trb_net16_gbe_main_control.vhd
index 32baf47..3c8bb08 100644
--- a/gbe_trb/base/trb_net16_gbe_main_control.vhd
+++ b/gbe_trb/base/trb_net16_gbe_main_control.vhd
@@ -704,7 +704,7 @@ begin
           link_next_state <= INACTIVE;
         else
           if (link_ok_timeout_ctr = x"ffff") then
-            link_next_state <= ENABLE_MAC; --FINALIZE;
+            link_next_state <= ENABLE_MAC;
           else
             link_next_state <= TIMEOUT;
           end if;
@@ -715,7 +715,7 @@ begin
         if (PCS_AN_COMPLETE_IN = '0') then
           link_next_state <= INACTIVE;
         elsif (MAC_READY_CONF_IN = '1') then
-          link_next_state <= FINALIZE; --INACTIVE;
+          link_next_state <= FINALIZE;
         else
           link_next_state <= ENABLE_MAC;
         end if;
@@ -725,7 +725,7 @@ begin
         if (PCS_AN_COMPLETE_IN = '0') then
           link_next_state <= INACTIVE;
         else
-          link_next_state <= WAIT_FOR_BOOT; --ACTIVE;
+          link_next_state <= WAIT_FOR_BOOT;
         end if;
 
       when WAIT_FOR_BOOT =>
@@ -788,7 +788,7 @@ begin
     end if;
   end process LINK_OK_CTR_PROC;
 
-  link_ok <= '1';
+  link_ok <= '1'; -- BUG - what the fuck?
 
   WAIT_CTR_PROC : process(CLK)
   begin
diff --git a/gbe_trb/base/trb_net_gbe_components.vhd b/gbe_trb/base/trb_net_gbe_components.vhd
index d4d2297..ea79091 100644
--- a/gbe_trb/base/trb_net_gbe_components.vhd
+++ b/gbe_trb/base/trb_net_gbe_components.vhd
@@ -304,138 +304,6 @@ port (
 );
 end component;
 
---component trb_net16_gbe_protocol_selector is
---generic(
---		RX_PATH_ENABLE : integer range 0 to 1 := 1;
---		DO_SIMULATION  : integer range 0 to 1 := 0;
---		
---		INCLUDE_READOUT  : std_logic := '0';
---		INCLUDE_SLOWCTRL : std_logic := '0';
---		INCLUDE_DHCP     : std_logic := '0';
---		INCLUDE_ARP      : std_logic := '0';
---		INCLUDE_PING     : std_logic := '0';
---		
---		READOUT_BUFFER_SIZE : integer range 1 to 4;
---		SLOWCTRL_BUFFER_SIZE : integer range 1 to 4 
---	);
---port (
---	CLK			: in	std_logic;  -- system clock
---	RESET			: in	std_logic;
---	RESET_FOR_DHCP : in std_logic;
---
----- signals to/from main controller
---	PS_DATA_IN		: in	std_logic_vector(8 downto 0); 
---	PS_WR_EN_IN		: in	std_logic;
---	PS_PROTO_SELECT_IN	: in	std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
---	PS_BUSY_OUT		: out	std_logic_vector(c_MAX_PROTOCOLS - 1 downto 0);
---	PS_FRAME_SIZE_IN	: in	std_logic_vector(15 downto 0);
---	PS_RESPONSE_READY_OUT	: out	std_logic;
---	
---	PS_SRC_MAC_ADDRESS_IN	: in	std_logic_vector(47 downto 0);
---	PS_DEST_MAC_ADDRESS_IN  : in	std_logic_vector(47 downto 0);
---	PS_SRC_IP_ADDRESS_IN	: in	std_logic_vector(31 downto 0);
---	PS_DEST_IP_ADDRESS_IN	: in	std_logic_vector(31 downto 0);
---	PS_SRC_UDP_PORT_IN	: in	std_logic_vector(15 downto 0);
---	PS_DEST_UDP_PORT_IN	: in	std_logic_vector(15 downto 0);
---	
----- singals to/from transmi controller with constructed response
---	TC_DATA_OUT		: out	std_logic_vector(8 downto 0);
---	TC_RD_EN_IN		: in	std_logic;
---	TC_FRAME_SIZE_OUT	: out	std_logic_vector(15 downto 0);
---	TC_FRAME_TYPE_OUT	: out	std_logic_vector(15 downto 0);
---	TC_IP_PROTOCOL_OUT	: out	std_logic_vector(7 downto 0);
---	TC_IDENT_OUT        : out   std_logic_vector(15 downto 0);
---	TC_DEST_MAC_OUT		: out	std_logic_vector(47 downto 0);
---	TC_DEST_IP_OUT		: out	std_logic_vector(31 downto 0);
---	TC_DEST_UDP_OUT		: out	std_logic_vector(15 downto 0);
---	TC_SRC_MAC_OUT		: out	std_logic_vector(47 downto 0);
---	TC_SRC_IP_OUT		: out	std_logic_vector(31 downto 0);
---	TC_SRC_UDP_OUT		: out	std_logic_vector(15 downto 0);
---	MC_BUSY_IN          : in	std_logic;
---	
---	-- misc signals for response constructors
---	MY_MAC_IN			: in	std_logic_vector(47 downto 0);
---	MY_IP_OUT			: out	std_logic_vector(31 downto 0);	
---	DHCP_START_IN		: in	std_logic;
---	DHCP_DONE_OUT		: out	std_logic;
---		
---	GSC_CLK_IN               : in std_logic;
---	GSC_INIT_DATAREADY_OUT   : out std_logic;
---	GSC_INIT_DATA_OUT        : out std_logic_vector(15 downto 0);
---	GSC_INIT_PACKET_NUM_OUT  : out std_logic_vector(2 downto 0);
---	GSC_INIT_READ_IN         : in std_logic;
---	GSC_REPLY_DATAREADY_IN   : in std_logic;
---	GSC_REPLY_DATA_IN        : in std_logic_vector(15 downto 0);
---	GSC_REPLY_PACKET_NUM_IN  : in std_logic_vector(2 downto 0);
---	GSC_REPLY_READ_OUT       : out std_logic;
---	GSC_BUSY_IN              : in std_logic;
---	
---	MAKE_RESET_OUT           : out std_logic;
---	
---	-- signal for data readout
---	-- CTS interface
---	CTS_NUMBER_IN				: in	std_logic_vector (15 downto 0);
---	CTS_CODE_IN					: in	std_logic_vector (7  downto 0);
---	CTS_INFORMATION_IN			: in	std_logic_vector (7  downto 0);
---	CTS_READOUT_TYPE_IN			: in	std_logic_vector (3  downto 0);
---	CTS_START_READOUT_IN		: in	std_logic;
---	CTS_DATA_OUT				: out	std_logic_vector (31 downto 0);
---	CTS_DATAREADY_OUT			: out	std_logic;
---	CTS_READOUT_FINISHED_OUT	: out	std_logic;
---	CTS_READ_IN					: in	std_logic;
---	CTS_LENGTH_OUT				: out	std_logic_vector (15 downto 0);
---	CTS_ERROR_PATTERN_OUT		: out	std_logic_vector (31 downto 0);
---	-- Data payload interface
---	FEE_DATA_IN					: in	std_logic_vector (15 downto 0);
---	FEE_DATAREADY_IN			: in	std_logic;
---	FEE_READ_OUT				: out	std_logic;
---	FEE_STATUS_BITS_IN			: in	std_logic_vector (31 downto 0);
---	FEE_BUSY_IN					: in	std_logic;
---	-- ip configurator
---	SLV_ADDR_IN                  : in std_logic_vector(7 downto 0);
---	SLV_READ_IN                  : in std_logic;
---	SLV_WRITE_IN                 : in std_logic;
---	SLV_BUSY_OUT                 : out std_logic;
---	SLV_ACK_OUT                  : out std_logic;
---	SLV_DATA_IN                  : in std_logic_vector(31 downto 0);
---	SLV_DATA_OUT                 : out std_logic_vector(31 downto 0);
---	
---	CFG_GBE_ENABLE_IN            : in std_logic;                    
---	CFG_IPU_ENABLE_IN            : in std_logic;                    
---	CFG_MULT_ENABLE_IN           : in std_logic;                    
---	CFG_SUBEVENT_ID_IN			 : in std_logic_vector(31 downto 0);
---	CFG_SUBEVENT_DEC_IN          : in std_logic_vector(31 downto 0);
---	CFG_QUEUE_DEC_IN             : in std_logic_vector(31 downto 0);
---	CFG_READOUT_CTR_IN           : in std_logic_vector(23 downto 0);
---	CFG_READOUT_CTR_VALID_IN     : in std_logic;
---	CFG_INSERT_TTYPE_IN          : in std_logic;
---	CFG_MAX_SUB_IN               : in std_logic_vector(15 downto 0);
---	CFG_MAX_QUEUE_IN             : in std_logic_vector(15 downto 0);
---	CFG_MAX_SUBS_IN_QUEUE_IN     : in std_logic_vector(15 downto 0);
---	CFG_MAX_SINGLE_SUB_IN        : in std_logic_vector(15 downto 0);
---	  
---	CFG_ADDITIONAL_HDR_IN        : in std_logic;
---	CFG_MAX_REPLY_SIZE_IN        : in std_logic_vector(31 downto 0);
---	
---	-- input for statistics from outside	
---	STAT_DATA_IN             : in std_logic_vector(31 downto 0);
---	STAT_ADDR_IN             : in std_logic_vector(7 downto 0);
---	STAT_DATA_RDY_IN         : in std_logic;
---	STAT_DATA_ACK_OUT        : out std_logic;
---	
---	MONITOR_SELECT_REC_OUT	      : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	MONITOR_SELECT_REC_BYTES_OUT  : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	MONITOR_SELECT_SENT_BYTES_OUT : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	MONITOR_SELECT_SENT_OUT	      : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	MONITOR_SELECT_DROP_IN_OUT    : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	MONITOR_SELECT_DROP_OUT_OUT   : out	std_logic_vector(c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	MONITOR_SELECT_GEN_DBG_OUT    : out	std_logic_vector(2*c_MAX_PROTOCOLS * 32 - 1 downto 0);
---	
---	DATA_HIST_OUT : out hist_array;
---	SCTRL_HIST_OUT : out hist_array 	
---);
---end component;
-
 component trb_net16_gbe_mac_control is
 port (
 	CLK			: in	std_logic;  -- system clock
@@ -886,12 +754,16 @@ port(
 	FRAME_DELAY_IN		: in	std_logic_vector(31 downto 0);
 	-- ports for packetTransmitter
 	RD_CLK                  : in    std_logic; -- 125MHz clock!!!
-	FT_DATA_OUT             : out   std_logic_vector(8 downto 0);
-	FT_TX_EMPTY_OUT         : out   std_logic;
-	FT_TX_RD_EN_IN          : in    std_logic;
-	FT_START_OF_PACKET_OUT  : out   std_logic;
-	FT_TX_DONE_IN           : in    std_logic;
-	FT_TX_DISCFRM_IN	: in	std_logic;
+----------------------------
+	FT_TX_DATA_OUT          : out std_logic_vector(8 downto 0);
+	FT_TX_WR_OUT            : out std_logic;
+	FT_TX_FIFOFULL_IN       : in  std_logic;
+--	FT_DATA_OUT             : out   std_logic_vector(8 downto 0);
+--	FT_TX_EMPTY_OUT         : out   std_logic;
+--	FT_TX_RD_EN_IN          : in    std_logic;
+--	FT_START_OF_PACKET_OUT  : out   std_logic;
+--	FT_TX_DONE_IN           : in    std_logic;
+--	FT_TX_DISCFRM_IN	: in	std_logic;
 	
 	MONITOR_TX_BYTES_OUT    : out std_logic_vector(31 downto 0);
 	MONITOR_TX_FRAMES_OUT   : out std_logic_vector(31 downto 0)
diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd
index 678143b..adcd0b9 100644
--- a/gbe_trb/base/tx_fifo.vhd
+++ b/gbe_trb/base/tx_fifo.vhd
@@ -57,7 +57,7 @@ architecture tx_fifo_arch of tx_fifo is
 
 begin
 
-  -- FrameActice signal - used to inhibt acceptance of runt frames
+  -- FrameActice signal - used to inhibit acceptance of runt frames
   THE_FRAME_ACTIVE_PROC: process( CLK )
   begin
     if( rising_edge(CLK) ) then
@@ -81,7 +81,7 @@ begin
     WREN          => fifo_wr,
     RDEN          => MAC_TX_READ_IN,
     RESET         => RESET,
-    Q(8)          => mac_fifoeof,
+    Q(8)          => mac_fifoeof, -- potential bug!!!!
     Q(7 downto 0) => MAC_TX_DATA_OUT,
     EMPTY         => MAC_FIFOEMPTY_OUT, 
     FULL          => open,
diff --git a/gbe_trb_ecp3/base/gbe_med_fifo.vhd b/gbe_trb_ecp3/base/gbe_med_fifo.vhd
index ef120d7..9a99548 100644
--- a/gbe_trb_ecp3/base/gbe_med_fifo.vhd
+++ b/gbe_trb_ecp3/base/gbe_med_fifo.vhd
@@ -21,17 +21,17 @@ entity gbe_med_fifo is
     CLK_125               : in  std_logic;
     -- FIFO interface RX
     FIFO_DATA_OUT         : out std_logic_vector(4 * 9 - 1 downto 0);
-    FIFO_FULL_IN          : in  std_logic_vector(3 downto 0);
+    FIFO_FULL_IN          : in  std_logic_vector(3 downto 0)          := (others => '0');
     FIFO_WR_OUT           : out std_logic_vector(3 downto 0);
-    FRAME_REQ_IN          : in  std_logic_vector(3 downto 0);
+    FRAME_REQ_IN          : in  std_logic_vector(3 downto 0)          := (others => '0');
     FRAME_ACK_OUT         : out std_logic_vector(3 downto 0);
     FRAME_AVAIL_OUT       : out std_logic_vector(3 downto 0);
     FRAME_START_OUT       : out std_logic_vector(3 downto 0);
     -- FIFO interface TX
     FIFO_FULL_OUT         : out std_logic_vector(3 downto 0);
-    FIFO_WR_IN            : in  std_logic_vector(3 downto 0);
-    FIFO_DATA_IN          : in  std_logic_vector(4 * 9 - 1 downto 0);
-    FRAME_START_IN        : in  std_logic_vector(3 downto 0);
+    FIFO_WR_IN            : in  std_logic_vector(3 downto 0)          := (others => '0');
+    FIFO_DATA_IN          : in  std_logic_vector(4 * 9 - 1 downto 0)  := (others => '0');
+    FRAME_START_IN        : in  std_logic_vector(3 downto 0)          := (others => '0');
     -- SFP Connection
     SD_PRSNT_N_IN         : in  std_logic_vector(3 downto 0)          := (others => '0');
     SD_LOS_IN             : in  std_logic_vector(3 downto 0)          := (others => '0');
@@ -41,6 +41,8 @@ entity gbe_med_fifo is
     TX_PCS_RST_IN         : in  std_logic;
     RX_LINK_READY_OUT     : out std_logic_vector(3 downto 0);
     TX_LINK_READY_IN      : in  std_logic;
+    PCS_AN_READY_OUT      : out std_logic_vector(3 downto 0); -- for internal SCTRL
+    LINK_ACTIVE_OUT       : out std_logic_vector(3 downto 0); -- for internal SCTRL
     -- Debug
     STATUS_OUT            : out std_logic_vector(4 * 8 - 1 downto 0);
     DEBUG_OUT             : out std_logic_vector(63 downto 0)
@@ -236,9 +238,9 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is
   signal led_activity_x                           : std_logic_vector(3 downto 0);
   signal led_activity                             : std_logic_vector(4 * 2 - 1 downto 0);
 
-  attribute HGROUP : string;
+--  attribute HGROUP : string;
 --  attribute BBOX   : string;
-  attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group";
+--  attribute HGROUP of gbe_med_fifo_arch : architecture is "gbe_med_fifo_group";
 --  attribute BBOX   of ddmtd_arch : architecture is "2,2";
 
 begin
@@ -623,6 +625,9 @@ begin
         --
         DEBUG             => open
       );
+      
+      PCS_AN_READY_OUT(i) <= an_complete(i); -- needed for internal SCTRL
+      LINK_ACTIVE_OUT(i)  <= link_active(i);
           
       -- LED connections, can be simplified by CE signal, to get rid of local counter instances
       led_activity_x(i)  <= pcs_rx_en(i) or pcs_tx_en(i);
@@ -658,6 +663,9 @@ begin
       rx_pcs_rst_q(i)    <= '1';
       rx_serdes_rst_q(i) <= '1';
 
+      PCS_AN_READY_OUT(i) <= '0';
+      LINK_ACTIVE_OUT(i)  <= '0';
+      
       -- Status signals
       STATUS_OUT(i * 8 + 7) <= '0';                            -- unused
       STATUS_OUT(i * 8 + 6) <= '0';                            -- link is active
diff --git a/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd b/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
new file mode 100644
index 0000000..64d2a90
--- /dev/null
+++ b/gbe_trb_ecp3/base/gbe_wrapper_fifo.vhd
@@ -0,0 +1,703 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.std_logic_ARITH.all;
+use IEEE.std_logic_UNSIGNED.all;
+
+library work;
+use work.trb_net_std.all;
+use work.trb_net_components.all;
+
+use work.trb_net_gbe_components.all;
+use work.trb_net_gbe_protocols.all;
+
+
+entity gbe_wrapper_fifo is
+  generic(
+    DO_SIMULATION             : integer range 0 to 1         := 0;
+    INCLUDE_DEBUG             : integer range 0 to 1         := 0;
+    USE_INTERNAL_TRBNET_DUMMY : integer range 0 to 1         := 0; -- only for debugging
+    USE_EXTERNAL_TRBNET_DUMMY : integer range 0 to 1         := 0; -- only for debugging
+    RX_PATH_ENABLE            : integer range 0 to 1         := 1; -- 
+    FIXED_SIZE_MODE           : integer range 0 to 1         := 1; -- only for debugging
+    INCREMENTAL_MODE          : integer range 0 to 1         := 0; -- only for debugging
+    FIXED_SIZE                : integer range 0 to 65535     := 10; -- only for debugging
+    FIXED_DELAY_MODE          : integer range 0 to 1         := 1; -- only for debugging
+    UP_DOWN_MODE              : integer range 0 to 1         := 0; -- only for debugging
+    UP_DOWN_LIMIT             : integer range 0 to 16777215  := 0; -- only for debugging
+    FIXED_DELAY               : integer range 0 to 16777215  := 16777215; -- only for debugging
+    LINK_HAS_PING             : std_logic                    := '1';
+    LINK_HAS_ARP              : std_logic                    := '1';
+    LINK_HAS_DHCP             : std_logic                    := '1';
+    LINK_HAS_READOUT          : std_logic                    := '1';
+    LINK_HAS_SLOWCTRL         : std_logic                    := '1';
+    LINK_HAS_FWD              : std_logic                    := '1'
+  );
+  port(
+    CLK_SYS_IN                : in  std_logic;
+    CLK_125_IN                : in  std_logic;
+    RESET                     : in  std_logic;
+    GSR_N                     : in  std_logic;
+    -- we connect to FIFO interface directly
+    -- FIFO interface RX
+    FIFO_DATA_OUT             : out std_logic_vector(8 downto 0);
+    FIFO_FULL_IN              : in  std_logic;
+    FIFO_WR_OUT               : out std_logic;
+    FRAME_REQ_IN              : in  std_logic;
+    FRAME_ACK_OUT             : out std_logic;
+    FRAME_AVAIL_OUT           : out std_logic;
+    FRAME_START_OUT           : out std_logic;
+    -- FIFO interface TX
+    FIFO_FULL_OUT             : out std_logic;
+    FIFO_WR_IN                : in  std_logic;
+    FIFO_DATA_IN              : in  std_logic_vector(8 downto 0);
+    FRAME_START_IN            : in  std_logic;
+    --
+    PCS_AN_READY_IN           : in  std_logic;
+    LINK_ACTIVE_IN            : in  std_logic;
+    --                        
+    TRIGGER_IN                : in  std_logic; -- for debug purpose only
+    -- CTS interface          
+    CTS_NUMBER_IN             : in  std_logic_vector(15 downto 0) := (others => '0');
+    CTS_CODE_IN               : in  std_logic_vector(7 downto 0)  := (others => '0');
+    CTS_INFORMATION_IN        : in  std_logic_vector(7 downto 0)  := (others => '0');
+    CTS_READOUT_TYPE_IN       : in  std_logic_vector(3 downto 0)  := (others => '0');
+    CTS_START_READOUT_IN      : in  std_logic                     := '0';
+    CTS_DATA_OUT              : out std_logic_vector(31 downto 0);
+    CTS_DATAREADY_OUT         : out std_logic;
+    CTS_READOUT_FINISHED_OUT  : out std_logic;
+    CTS_READ_IN               : in  std_logic                     := '0';
+    CTS_LENGTH_OUT            : out std_logic_vector(15 downto 0);
+    CTS_ERROR_PATTERN_OUT     : out std_logic_vector(31 downto 0);
+    -- Data payload interface 
+    FEE_DATA_IN               : in  std_logic_vector(15 downto 0) := (others => '0');
+    FEE_DATAREADY_IN          : in  std_logic                     := '0';
+    FEE_READ_OUT              : out std_logic;
+    FEE_STATUS_BITS_IN        : in  std_logic_vector(31 downto 0) := (others => '0');
+    FEE_BUSY_IN               : in  std_logic                     := '0';
+    -- SlowControl            
+    MY_TRBNET_ADDRESS_IN      : in  std_logic_vector(15 downto 0);
+    ISSUE_REBOOT_OUT          : out std_logic;
+    MC_UNIQUE_ID_IN           : in  std_logic_vector(63 downto 0);
+    GSC_CLK_IN                : in  std_logic;
+    GSC_INIT_DATAREADY_OUT    : out std_logic;
+    GSC_INIT_DATA_OUT         : out std_logic_vector(15 downto 0);
+    GSC_INIT_PACKET_NUM_OUT   : out std_logic_vector(2 downto 0);
+    GSC_INIT_READ_IN          : in  std_logic;
+    GSC_REPLY_DATAREADY_IN    : in  std_logic;
+    GSC_REPLY_DATA_IN         : in  std_logic_vector(15 downto 0);
+    GSC_REPLY_PACKET_NUM_IN   : in  std_logic_vector(2 downto 0);
+    GSC_REPLY_READ_OUT        : out std_logic;
+    GSC_BUSY_IN               : in  std_logic;
+    -- IP configuration       
+    BUS_IP_RX                 : in  CTRLBUS_RX;
+    BUS_IP_TX                 : out CTRLBUS_TX;
+    -- Registers config       
+    BUS_REG_RX                : in  CTRLBUS_RX;
+    BUS_REG_TX                : out CTRLBUS_TX;
+    -- Forwarder              
+    FWD_DST_MAC_IN            : in  std_logic_vector(47 downto 0) := (others => '0');
+    FWD_DST_IP_IN             : in  std_logic_vector(31 downto 0) := (others => '0');
+    FWD_DST_UDP_IN            : in  std_logic_vector(15 downto 0) := (others => '0');
+    FWD_DATA_IN               : in  std_logic_vector(7 downto 0) := (others => '0');
+    FWD_DATA_VALID_IN         : in  std_logic := '0';
+    FWD_SOP_IN                : in  std_logic := '0';
+    FWD_EOP_IN                : in  std_logic := '0';
+    FWD_READY_OUT             : out std_logic;
+    FWD_FULL_OUT              : out std_logic;
+    --                        
+    MAKE_RESET_OUT            : out std_logic;
+    --                        
+    STATUS_OUT                : out std_logic_vector(15 downto 0);
+    DEBUG_OUT                 : out std_logic_vector(127 downto 0)
+  );
+end entity gbe_wrapper_fifo;
+
+architecture RTL of gbe_wrapper_fifo is
+
+  signal cfg_gbe_enable             : std_logic;
+  signal cfg_ipu_enable             : std_logic;
+  signal cfg_mult_enable            : std_logic;
+  signal cfg_subevent_id            : std_logic_vector(31 downto 0);
+  signal cfg_subevent_dec           : std_logic_vector(31 downto 0);
+  signal cfg_queue_dec              : std_logic_vector(31 downto 0);
+  signal cfg_readout_ctr            : std_logic_vector(23 downto 0);
+  signal cfg_readout_ctr_valid      : std_logic;
+  signal cfg_insert_ttype           : std_logic;
+  signal cfg_max_sub                : std_logic_vector(15 downto 0);
+  signal cfg_max_queue              : std_logic_vector(15 downto 0);
+  signal cfg_max_subs_in_queue      : std_logic_vector(15 downto 0);
+  signal cfg_max_single_sub         : std_logic_vector(15 downto 0);
+  signal cfg_additional_hdr         : std_logic;
+  signal cfg_soft_rst               : std_logic;
+  signal cfg_allow_rx               : std_logic;
+  signal cfg_max_frame              : std_logic_vector(15 downto 0);
+
+  signal dbg_hist, dbg_hist2        : hist_array;
+
+  signal mac_0                      : std_logic_vector(47 downto 0);
+  signal cfg_max_reply              : std_logic_vector(31 downto 0);
+
+  signal mlt_cts_number             : std_logic_vector(15 downto 0);
+  signal mlt_cts_code               : std_logic_vector(7 downto 0);
+  signal mlt_cts_information        : std_logic_vector(7 downto 0);
+  signal mlt_cts_readout_type       : std_logic_vector(3 downto 0);
+  signal mlt_cts_start_readout      : std_logic_vector(0 downto 0);
+  signal mlt_cts_data               : std_logic_vector(31 downto 0);
+  signal mlt_cts_dataready          : std_logic_vector(0 downto 0);
+  signal mlt_cts_readout_finished   : std_logic_vector(0 downto 0);
+  signal mlt_cts_read               : std_logic_vector(0 downto 0);
+  signal mlt_cts_length             : std_logic_vector(15 downto 0);
+  signal mlt_cts_error_pattern      : std_logic_vector(31 downto 0);
+  signal mlt_fee_data               : std_logic_vector(15 downto 0);
+  signal mlt_fee_dataready          : std_logic_vector(0 downto 0);
+  signal mlt_fee_read               : std_logic_vector(0 downto 0);
+  signal mlt_fee_status             : std_logic_vector(31 downto 0);
+  signal mlt_fee_busy               : std_logic_vector(0 downto 0);
+
+  signal mlt_gsc_clk                : std_logic;
+  signal mlt_gsc_init_dataready     : std_logic;
+  signal mlt_gsc_init_data          : std_logic_vector(15 downto 0);
+  signal mlt_gsc_init_packet        : std_logic_vector(2 downto 0);
+  signal mlt_gsc_init_read          : std_logic;
+  signal mlt_gsc_reply_dataready    : std_logic;
+  signal mlt_gsc_reply_data         : std_logic_vector(15 downto 0);
+  signal mlt_gsc_reply_packet       : std_logic_vector(2 downto 0);
+  signal mlt_gsc_reply_read         : std_logic;
+  signal mlt_gsc_busy               : std_logic;
+
+  signal local_cts_number           : std_logic_vector(15 downto 0);
+  signal local_cts_code             : std_logic_vector(7 downto 0);
+  signal local_cts_information      : std_logic_vector(7 downto 0);
+  signal local_cts_readout_type     : std_logic_vector(3 downto 0);
+  signal local_cts_start_readout    : std_logic;
+  signal local_cts_readout_finished : std_logic;
+  signal local_cts_status_bits      : std_logic_vector(31 downto 0);
+  signal local_fee_data             : std_logic_vector(15 downto 0);
+  signal local_fee_dataready        : std_logic;
+  signal local_fee_read             : std_logic;
+  signal local_fee_status_bits      : std_logic_vector(31 downto 0);
+  signal local_fee_busy             : std_logic;
+  signal dhcp_done                  : std_logic;
+  signal all_links_ready            : std_logic;
+  signal monitor_rx_frames          : std_logic_vector(31 downto 0);
+  signal monitor_rx_bytes           : std_logic_vector(31 downto 0);
+  signal monitor_tx_frames          : std_logic_vector(31 downto 0);
+  signal monitor_tx_bytes           : std_logic_vector(31 downto 0);
+  signal monitor_tx_packets         : std_logic_vector(31 downto 0);
+  signal monitor_dropped            : std_logic_vector(31 downto 0);
+  signal sum_rx_frames              : std_logic_vector(31 downto 0);
+  signal sum_rx_bytes               : std_logic_vector(31 downto 0);
+  signal sum_tx_frames              : std_logic_vector(31 downto 0);
+  signal sum_tx_bytes               : std_logic_vector(31 downto 0);
+  signal sum_tx_packets             : std_logic_vector(31 downto 0);
+  signal sum_dropped                : std_logic_vector(31 downto 0);
+
+  signal busip0                                               : CTRLBUS_TX;
+
+  signal dummy_event                                        : std_logic_vector(15 downto 0);
+  signal dummy_mode                                         : std_logic;
+  signal make_reset0                                        : std_logic := '0';
+  signal monitor_gen_dbg                                    : std_logic_vector(c_MAX_PROTOCOLS * 64 - 1 downto 0);
+
+  signal cfg_autothrottle   : std_logic;
+  signal cfg_throttle_pause : std_logic_vector(15 downto 0);
+  
+  signal issue_reboot : std_logic;
+  signal my_ip        : std_logic_vector(127 downto 0);
+  signal debug        : std_logic_vector(127 downto 0);
+  
+  signal frame_active     : std_Logic;
+  signal frame_written    : std_logic;
+  signal rx_fifo_wr       : std_logic;
+  signal frame_requested  : std_logic;
+  signal fifo_empty       : std_logic;
+  signal fifo_data        : std_logic_vector(8 downto 0);
+  signal tx_data_read     : std_Logic;
+  signal normal_read_ack  : std_logic;
+  signal empty_read_ack   : std_Logic;
+  signal fifo_wr_int      : std_logic;
+  signal sof_int          : std_logic;
+  signal tx_done_int      : std_logic_vector(7 downto 0);
+  
+  signal ft_tx_data       : std_logic_vector(8 downto 0);
+  signal ft_tx_wr         : std_logic;
+  signal ft_tx_fifofull   : std_logic;
+  
+begin
+
+  -------------------------------------------------------------------------------------------------
+  -- FrameActice signal - used to inhibit acceptance of runt frames
+  THE_FRAME_ACTIVE_PROC: process( CLK_125_IN )
+  begin
+    if( rising_edge(CLK_125_IN) ) then
+      if   ( RESET = '1' ) then
+        frame_active <= '0';
+      elsif( FRAME_START_IN = '1' ) then
+        frame_active <= LINK_ACTIVE_IN;
+      elsif( frame_written = '1' ) then
+        frame_active <= '0';
+      end if;
+    end if;
+  end process THE_FRAME_ACTIVE_PROC;
+
+  -- one frame written to FIFO
+  frame_written <= '1' when (FIFO_DATA_IN(8) = '1') and (FIFO_WR_IN = '1') and (frame_active = '1') else '0';
+
+  rx_fifo_wr <= FIFO_WR_IN and frame_active;
+  -------------------------------------------------------------------------------------------------
+  THE_FRAME_TX: entity rx_rb 
+  port map(
+    CLK                 => CLK_125_IN,
+    RESET               => RESET,
+    -- MAC interface (RX)
+    MAC_RX_DATA_IN      => ft_tx_data(7 downto 0),
+    MAC_RX_WR_IN        => ft_tx_wr,
+    MAC_RX_EOF_IN       => ft_tx_data(8),
+    MAC_RX_ERROR_IN     => '0',
+    MAC_RX_FIFOFULL_OUT => ft_tx_fifofull,
+    -- FIFO interface (TX)
+    FIFO_FULL_IN        => FIFO_FULL_IN,
+    FIFO_WR_OUT         => FIFO_WR_OUT,
+    FIFO_Q_OUT          => FIFO_DATA_OUT,
+    FRAME_REQ_IN        => FRAME_REQ_IN,
+    FRAME_ACK_OUT       => FRAME_ACK_OUT,
+    FRAME_AVAIL_OUT     => FRAME_AVAIL_OUT,
+    FRAME_START_OUT     => FRAME_START_OUT,
+    --
+    DEBUG               => open
+  );
+
+  -------------------------------------------------------------------------------------------------
+  -- debug(127 downto 64) are local
+  -- debug(63 downto 0) are media interface
+  DEBUG_OUT <= debug;
+
+  mac_0 <= MC_UNIQUE_ID_IN(15 downto 8) & MC_UNIQUE_ID_IN(23 downto 16) & MC_UNIQUE_ID_IN(31 downto 24) & x"0" & MC_UNIQUE_ID_IN(35 downto 32) & x"7ada";
+
+  all_links_ready <= '1' when dhcp_done = '1' else '0';
+
+  MAKE_RESET_OUT <= '1' when  make_reset0 = '1' else '0';
+  
+  ISSUE_REBOOT_OUT <= '0' when issue_reboot = '0' else '1';
+
+  STATUS_OUT(7 downto 0)  <= (others => '0');
+  STATUS_OUT(8)           <= dhcp_done; -- DHCP has completed
+  STATUS_OUT(15 downto 9) <= (others => '0');
+  
+  gbe_inst : entity work.gbe_logic_wrapper
+  generic map(DO_SIMULATION           => DO_SIMULATION,
+            INCLUDE_DEBUG             => INCLUDE_DEBUG,
+            USE_INTERNAL_TRBNET_DUMMY => USE_INTERNAL_TRBNET_DUMMY,
+            RX_PATH_ENABLE            => RX_PATH_ENABLE,
+            INCLUDE_READOUT           => LINK_HAS_READOUT,
+            INCLUDE_SLOWCTRL          => LINK_HAS_SLOWCTRL,
+            INCLUDE_DHCP              => LINK_HAS_DHCP,
+            INCLUDE_ARP               => LINK_HAS_ARP,
+            INCLUDE_PING              => LINK_HAS_PING,
+            INCLUDE_FWD               => LINK_HAS_FWD,
+            FRAME_BUFFER_SIZE         => 1,
+            READOUT_BUFFER_SIZE       => 4,
+            SLOWCTRL_BUFFER_SIZE      => 2,
+            FIXED_SIZE_MODE           => FIXED_SIZE_MODE,
+            INCREMENTAL_MODE          => INCREMENTAL_MODE,
+            FIXED_SIZE                => FIXED_SIZE,
+            FIXED_DELAY_MODE          => FIXED_DELAY_MODE,
+            UP_DOWN_MODE              => UP_DOWN_MODE,
+            UP_DOWN_LIMIT             => UP_DOWN_LIMIT,
+            FIXED_DELAY               => FIXED_DELAY)
+  port map(
+    CLK_SYS_IN               => CLK_SYS_IN,
+    CLK_125_IN               => CLK_125_IN,
+    CLK_RX_125_IN            => CLK_125_IN,
+    RESET                    => RESET,
+    GSR_N                    => GSR_N,
+    MY_MAC_IN                => mac_0,
+    DHCP_DONE_OUT            => dhcp_done,
+    MY_IP_OUT                => my_ip(31 downto 0),
+    MY_TRBNET_ADDRESS_IN     => MY_TRBNET_ADDRESS_IN,
+    ISSUE_REBOOT_OUT         => issue_reboot,
+    MAC_READY_CONF_IN        => LINK_ACTIVE_IN, -- NEEDED
+    MAC_RECONF_OUT           => open, -- NEEDED
+    MAC_AN_READY_IN          => PCS_AN_READY_IN, -- NEEDED
+    MAC_FIFOAVAIL_OUT        => open, -- NEEDED
+    MAC_FIFOEOF_OUT          => open, -- NEEDED
+    MAC_FIFOEMPTY_OUT        => open, -- NEEDED
+    MAC_RX_FIFOFULL_OUT      => FIFO_FULL_OUT, -- NEEDED -- BUG: check level
+    MAC_TX_DATA_OUT          => open, -- NEEDED
+    MAC_TX_READ_IN           => '0', -- NEEDED
+    MAC_TX_DISCRFRM_IN       => '0', -- NEEDED
+    MAC_TX_STAT_EN_IN        => '0', -- NEEDED
+    MAC_TX_STATS_IN          => (others => '0'), -- NEEDED
+    MAC_TX_DONE_IN           => '0', -- NEEDED
+    MAC_RX_FIFO_ERR_IN       => '0', -- NEEDED
+    MAC_RX_STATS_IN          => (others => '0'), -- done
+    MAC_RX_DATA_IN           => FIFO_DATA_IN(7 downto 0), -- NEEDED
+    MAC_RX_WRITE_IN          => rx_fifo_wr, -- NEEDED
+    MAC_RX_STAT_EN_IN        => '0', -- NEEDED
+    MAC_RX_EOF_IN            => FIFO_DATA_IN(8), -- NEEDED
+    MAC_RX_ERROR_IN          => '0', -- NEEDED
+----
+    -- FIFO TX stuff
+    FT_TX_DATA_OUT           => ft_tx_data,
+    FT_TX_WR_OUT             => ft_tx_wr,
+    FT_TX_FIFOFULL_IN        => ft_tx_fifofull,
+----
+    CTS_NUMBER_IN            => mlt_cts_number,
+    CTS_CODE_IN              => mlt_cts_code,
+    CTS_INFORMATION_IN       => mlt_cts_information,
+    CTS_READOUT_TYPE_IN      => mlt_cts_readout_type,
+    CTS_START_READOUT_IN     => mlt_cts_start_readout(0),
+    CTS_DATA_OUT             => mlt_cts_data,
+    CTS_DATAREADY_OUT        => mlt_cts_dataready(0),
+    CTS_READOUT_FINISHED_OUT => mlt_cts_readout_finished(0),
+    CTS_READ_IN              => mlt_cts_read(0),
+    CTS_LENGTH_OUT           => mlt_cts_length,
+    CTS_ERROR_PATTERN_OUT    => mlt_cts_error_pattern,
+    FEE_DATA_IN              => mlt_fee_data,
+    FEE_DATAREADY_IN         => mlt_fee_dataready(0),
+    FEE_READ_OUT             => mlt_fee_read(0),
+    FEE_STATUS_BITS_IN       => mlt_fee_status,
+    FEE_BUSY_IN              => mlt_fee_busy(0),
+    GSC_CLK_IN               => mlt_gsc_clk,
+    GSC_INIT_DATAREADY_OUT   => mlt_gsc_init_dataready,
+    GSC_INIT_DATA_OUT        => mlt_gsc_init_data,
+    GSC_INIT_PACKET_NUM_OUT  => mlt_gsc_init_packet,
+    GSC_INIT_READ_IN         => mlt_gsc_init_read,
+    GSC_REPLY_DATAREADY_IN   => mlt_gsc_reply_dataready,
+    GSC_REPLY_DATA_IN        => mlt_gsc_reply_data,
+    GSC_REPLY_PACKET_NUM_IN  => mlt_gsc_reply_packet,
+    GSC_REPLY_READ_OUT       => mlt_gsc_reply_read,
+    GSC_BUSY_IN              => mlt_gsc_busy,
+    SLV_ADDR_IN              => BUS_IP_RX.addr(7 downto 0),
+    SLV_READ_IN              => BUS_IP_RX.read,
+    SLV_WRITE_IN             => BUS_IP_RX.write,
+    SLV_BUSY_OUT             => busip0.nack,
+    SLV_ACK_OUT              => busip0.ack,
+    SLV_DATA_IN              => BUS_IP_RX.data,
+    SLV_DATA_OUT             => busip0.data,
+    CFG_GBE_ENABLE_IN        => cfg_gbe_enable,
+    CFG_IPU_ENABLE_IN        => cfg_ipu_enable,
+    CFG_MULT_ENABLE_IN       => cfg_mult_enable,
+    CFG_MAX_FRAME_IN         => cfg_max_frame,
+    CFG_ALLOW_RX_IN          => cfg_allow_rx,
+    CFG_SOFT_RESET_IN        => cfg_soft_rst,
+    CFG_SUBEVENT_ID_IN       => cfg_subevent_id,
+    CFG_SUBEVENT_DEC_IN      => cfg_subevent_dec,
+    CFG_QUEUE_DEC_IN         => cfg_queue_dec,
+    CFG_READOUT_CTR_IN       => cfg_readout_ctr,
+    CFG_READOUT_CTR_VALID_IN => cfg_readout_ctr_valid,
+    CFG_INSERT_TTYPE_IN      => cfg_insert_ttype,
+    CFG_MAX_SUB_IN           => cfg_max_sub,
+    CFG_MAX_QUEUE_IN         => cfg_max_queue,
+    CFG_MAX_SUBS_IN_QUEUE_IN => cfg_max_subs_in_queue,
+    CFG_MAX_SINGLE_SUB_IN    => cfg_max_single_sub,
+    CFG_ADDITIONAL_HDR_IN    => cfg_additional_hdr,
+    CFG_MAX_REPLY_SIZE_IN    => cfg_max_reply,
+    CFG_AUTO_THROTTLE_IN     => cfg_autothrottle,
+    CFG_THROTTLE_PAUSE_IN    => cfg_throttle_pause,
+    FWD_DST_MAC_IN           => FWD_DST_MAC_IN,
+    FWD_DST_IP_IN            => FWD_DST_IP_IN,
+    FWD_DST_UDP_IN           => FWD_DST_UDP_IN,
+    FWD_DATA_IN              => FWD_DATA_IN,
+    FWD_DATA_VALID_IN        => FWD_DATA_VALID_IN,
+    FWD_SOP_IN               => FWD_SOP_IN,
+    FWD_EOP_IN               => FWD_EOP_IN,
+    FWD_READY_OUT            => FWD_READY_OUT,
+    FWD_FULL_OUT             => FWD_FULL_OUT,
+    MONITOR_RX_FRAMES_OUT    => monitor_rx_frames,
+    MONITOR_RX_BYTES_OUT     => monitor_rx_bytes,
+    MONITOR_TX_FRAMES_OUT    => monitor_tx_frames,
+    MONITOR_TX_BYTES_OUT     => monitor_tx_bytes,
+    MONITOR_TX_PACKETS_OUT   => monitor_tx_packets,
+    MONITOR_DROPPED_OUT      => monitor_dropped,
+    MONITOR_GEN_DBG_OUT      => monitor_gen_dbg,
+    MAKE_RESET_OUT           => make_reset0
+  );
+
+  BUS_IP_TX.ack  <= busip0.ack  when rising_edge(CLK_SYS_IN);
+  BUS_IP_TX.nack <= busip0.nack when rising_edge(CLK_SYS_IN);
+  BUS_IP_TX.data <= busip0.data when rising_edge(CLK_SYS_IN);
+
+  real_ipu_gen : if USE_EXTERNAL_TRBNET_DUMMY = 0 generate
+    ipu_mult : entity work.gbe_ipu_multiplexer
+      generic map(
+        DO_SIMULATION       => DO_SIMULATION,
+        INCLUDE_DEBUG       => INCLUDE_DEBUG,
+        LINK_HAS_READOUT    => "000" & LINK_HAS_READOUT,
+        NUMBER_OF_GBE_LINKS => 1
+      )
+      port map(
+        CLK_SYS_IN                  => CLK_SYS_IN,
+        RESET                       => RESET,
+        CTS_NUMBER_IN               => CTS_NUMBER_IN,
+        CTS_CODE_IN                 => CTS_CODE_IN,
+        CTS_INFORMATION_IN          => CTS_INFORMATION_IN,
+        CTS_READOUT_TYPE_IN         => CTS_READOUT_TYPE_IN,
+        CTS_START_READOUT_IN        => CTS_START_READOUT_IN,
+        CTS_DATA_OUT                => CTS_DATA_OUT,
+        CTS_DATAREADY_OUT           => CTS_DATAREADY_OUT,
+        CTS_READOUT_FINISHED_OUT    => CTS_READOUT_FINISHED_OUT,
+        CTS_READ_IN                 => CTS_READ_IN,
+        CTS_LENGTH_OUT              => CTS_LENGTH_OUT,
+        CTS_ERROR_PATTERN_OUT       => CTS_ERROR_PATTERN_OUT,
+        FEE_DATA_IN                 => FEE_DATA_IN,
+        FEE_DATAREADY_IN            => FEE_DATAREADY_IN,
+        FEE_READ_OUT                => FEE_READ_OUT,
+        FEE_STATUS_BITS_IN          => FEE_STATUS_BITS_IN,
+        FEE_BUSY_IN                 => FEE_BUSY_IN,
+        MLT_CTS_NUMBER_OUT          => mlt_cts_number,
+        MLT_CTS_CODE_OUT            => mlt_cts_code,
+        MLT_CTS_INFORMATION_OUT     => mlt_cts_information,
+        MLT_CTS_READOUT_TYPE_OUT    => mlt_cts_readout_type,
+        MLT_CTS_START_READOUT_OUT   => mlt_cts_start_readout,
+        MLT_CTS_DATA_IN             => mlt_cts_data,
+        MLT_CTS_DATAREADY_IN        => mlt_cts_dataready,
+        MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+        MLT_CTS_READ_OUT            => mlt_cts_read,
+        MLT_CTS_LENGTH_IN           => mlt_cts_length,
+        MLT_CTS_ERROR_PATTERN_IN    => mlt_cts_error_pattern,
+        MLT_FEE_DATA_OUT            => mlt_fee_data,
+        MLT_FEE_DATAREADY_OUT       => mlt_fee_dataready,
+        MLT_FEE_READ_IN             => mlt_fee_read,
+        MLT_FEE_STATUS_BITS_OUT     => mlt_fee_status,
+        MLT_FEE_BUSY_OUT            => mlt_fee_busy,
+        DEBUG_OUT                   => open
+      );
+  end generate real_ipu_gen;
+
+  dummy_ipu_gen : if (USE_EXTERNAL_TRBNET_DUMMY = 1) generate
+    ipu_mult : entity work.gbe_ipu_multiplexer
+    generic map(
+      DO_SIMULATION       => DO_SIMULATION,
+      INCLUDE_DEBUG       => INCLUDE_DEBUG,
+      LINK_HAS_READOUT    => LINK_HAS_READOUT,
+      NUMBER_OF_GBE_LINKS => 1
+    )
+    port map(
+      CLK_SYS_IN                  => CLK_SYS_IN,
+      RESET                       => RESET,
+      CTS_NUMBER_IN               => local_cts_number,
+      CTS_CODE_IN                 => local_cts_code,
+      CTS_INFORMATION_IN          => local_cts_information,
+      CTS_READOUT_TYPE_IN         => local_cts_readout_type,
+      CTS_START_READOUT_IN        => local_cts_start_readout,
+      CTS_DATA_OUT                => open,
+      CTS_DATAREADY_OUT           => open,
+      CTS_READOUT_FINISHED_OUT    => local_cts_readout_finished,
+      CTS_READ_IN                 => '1',
+      CTS_LENGTH_OUT              => open,
+      CTS_ERROR_PATTERN_OUT       => local_cts_status_bits,
+      FEE_DATA_IN                 => local_fee_data,
+      FEE_DATAREADY_IN            => local_fee_dataready,
+      FEE_READ_OUT                => local_fee_read,
+      FEE_STATUS_BITS_IN          => local_fee_status_bits,
+      FEE_BUSY_IN                 => local_fee_busy,
+      MLT_CTS_NUMBER_OUT          => mlt_cts_number,
+      MLT_CTS_CODE_OUT            => mlt_cts_code,
+      MLT_CTS_INFORMATION_OUT     => mlt_cts_information,
+      MLT_CTS_READOUT_TYPE_OUT    => mlt_cts_readout_type,
+      MLT_CTS_START_READOUT_OUT   => mlt_cts_start_readout,
+      MLT_CTS_DATA_IN             => mlt_cts_data,
+      MLT_CTS_DATAREADY_IN        => mlt_cts_dataready,
+      MLT_CTS_READOUT_FINISHED_IN => mlt_cts_readout_finished,
+      MLT_CTS_READ_OUT            => mlt_cts_read,
+      MLT_CTS_LENGTH_IN           => mlt_cts_length,
+      MLT_CTS_ERROR_PATTERN_IN    => mlt_cts_error_pattern,
+      MLT_FEE_DATA_OUT            => mlt_fee_data,
+      MLT_FEE_DATAREADY_OUT       => mlt_fee_dataready,
+      MLT_FEE_READ_IN             => mlt_fee_read,
+      MLT_FEE_STATUS_BITS_OUT     => mlt_fee_status,
+      MLT_FEE_BUSY_OUT            => mlt_fee_busy,
+      DEBUG_OUT                   => open
+    );
+
+    dummy : entity work.gbe_ipu_dummy
+    generic map(
+      DO_SIMULATION    => DO_SIMULATION,
+      FIXED_SIZE_MODE  => FIXED_SIZE_MODE,
+      INCREMENTAL_MODE => INCREMENTAL_MODE,
+      FIXED_SIZE       => FIXED_SIZE,
+      UP_DOWN_MODE     => UP_DOWN_MODE,
+      UP_DOWN_LIMIT    => UP_DOWN_LIMIT,
+      FIXED_DELAY_MODE => FIXED_DELAY_MODE,
+      FIXED_DELAY      => FIXED_DELAY
+    )
+    port map(
+      clk                     => CLK_SYS_IN,
+      rst                     => RESET,
+      GBE_READY_IN            => all_links_ready,
+      CFG_EVENT_SIZE_IN       => dummy_event,
+      CFG_TRIGGERED_MODE_IN   => '0',
+      TRIGGER_IN              => TRIGGER_IN,
+      CTS_NUMBER_OUT          => local_cts_number,
+      CTS_CODE_OUT            => local_cts_code,
+      CTS_INFORMATION_OUT     => local_cts_information,
+      CTS_READOUT_TYPE_OUT    => local_cts_readout_type,
+      CTS_START_READOUT_OUT   => local_cts_start_readout,
+      CTS_DATA_IN             => (others => '0'),
+      CTS_DATAREADY_IN        => '0',
+      CTS_READOUT_FINISHED_IN => local_cts_readout_finished,
+      CTS_READ_OUT            => open,
+      CTS_LENGTH_IN           => (others => '0'),
+      CTS_ERROR_PATTERN_IN    => local_cts_status_bits,
+      -- Data payload interface
+      FEE_DATA_OUT            => local_fee_data,
+      FEE_DATAREADY_OUT       => local_fee_dataready,
+      FEE_READ_IN             => local_fee_read,
+      FEE_STATUS_BITS_OUT     => local_fee_status_bits,
+      FEE_BUSY_OUT            => local_fee_busy
+    );
+
+    -- handler for triggers
+    DUMMY_HANDLER : entity work.trb_net16_gbe_ipu_interface
+    port map(
+      CLK_IPU                  => CLK_SYS_IN,
+      CLK_GBE                  => CLK_125_IN,
+      RESET                    => RESET,
+      --Event information coming from CTS
+      CTS_NUMBER_IN            => CTS_NUMBER_IN,
+      CTS_CODE_IN              => CTS_CODE_IN,
+      CTS_INFORMATION_IN       => CTS_INFORMATION_IN,
+      CTS_READOUT_TYPE_IN      => CTS_READOUT_TYPE_IN,
+      CTS_START_READOUT_IN     => CTS_START_READOUT_IN,
+      --Information sent to CTS
+      --status data, equipped with DHDR
+      CTS_DATA_OUT             => CTS_DATA_OUT,
+      CTS_DATAREADY_OUT        => CTS_DATAREADY_OUT,
+      CTS_READOUT_FINISHED_OUT => CTS_READOUT_FINISHED_OUT,
+      CTS_READ_IN              => CTS_READ_IN,
+      CTS_LENGTH_OUT           => CTS_LENGTH_OUT,
+      CTS_ERROR_PATTERN_OUT    => CTS_ERROR_PATTERN_OUT,
+      -- Data from Frontends
+      FEE_DATA_IN              => FEE_DATA_IN,
+      FEE_DATAREADY_IN         => FEE_DATAREADY_IN,
+      FEE_READ_OUT             => FEE_READ_OUT,
+      FEE_STATUS_BITS_IN       => FEE_STATUS_BITS_IN,
+      FEE_BUSY_IN              => FEE_BUSY_IN,
+      -- slow control interface
+      START_CONFIG_OUT         => open,
+      BANK_SELECT_OUT          => open,
+      CONFIG_DONE_IN           => '1',
+      DATA_GBE_ENABLE_IN       => '1',
+      DATA_IPU_ENABLE_IN       => '1',
+      MULT_EVT_ENABLE_IN       => '1',
+      MAX_SUBEVENT_SIZE_IN     => (others => '0'),
+      MAX_QUEUE_SIZE_IN        => (others => '0'),
+      MAX_SUBS_IN_QUEUE_IN     => (others => '0'),
+      MAX_SINGLE_SUB_SIZE_IN   => (others => '0'),
+      READOUT_CTR_IN           => (others => '0'),
+      READOUT_CTR_VALID_IN     => '0',
+      CFG_AUTO_THROTTLE_IN     => '0',
+      CFG_THROTTLE_PAUSE_IN    => (others => '0'),
+      -- PacketConstructor interface
+      PC_WR_EN_OUT             => open,
+      PC_DATA_OUT              => open,
+      PC_READY_IN              => '1',
+      PC_SOS_OUT               => open,
+      PC_EOS_OUT               => open,
+      PC_EOQ_OUT               => open,
+      PC_SUB_SIZE_OUT          => open,
+      PC_TRIG_NR_OUT           => open,
+      PC_TRIGGER_TYPE_OUT      => open,
+      MONITOR_OUT              => open,
+      DEBUG_OUT                => open
+    );
+  end generate dummy_ipu_gen;
+
+  SETUP : gbe_setup
+  port map(
+    CLK                          => CLK_SYS_IN,
+    RESET                        => RESET,
+    -- interface to regio bus
+    BUS_ADDR_IN                  => BUS_REG_RX.addr(7 downto 0),
+    BUS_DATA_IN                  => BUS_REG_RX.data,
+    BUS_DATA_OUT                 => BUS_REG_TX.data,
+    BUS_WRITE_EN_IN              => BUS_REG_RX.write,
+    BUS_READ_EN_IN               => BUS_REG_RX.read,
+    BUS_ACK_OUT                  => BUS_REG_TX.ack,
+    -- output to gbe_buf
+    GBE_SUBEVENT_ID_OUT          => cfg_subevent_id,
+    GBE_SUBEVENT_DEC_OUT         => cfg_subevent_dec,
+    GBE_QUEUE_DEC_OUT            => cfg_queue_dec,
+    GBE_MAX_FRAME_OUT            => cfg_max_frame,
+    GBE_USE_GBE_OUT              => cfg_gbe_enable,
+    GBE_USE_TRBNET_OUT           => cfg_ipu_enable,
+    GBE_USE_MULTIEVENTS_OUT      => cfg_mult_enable,
+    GBE_READOUT_CTR_OUT          => cfg_readout_ctr,
+    GBE_READOUT_CTR_VALID_OUT    => cfg_readout_ctr_valid,
+    GBE_ALLOW_RX_OUT             => cfg_allow_rx,
+    GBE_ADDITIONAL_HDR_OUT       => cfg_additional_hdr,
+    GBE_INSERT_TTYPE_OUT         => cfg_insert_ttype,
+    GBE_SOFT_RESET_OUT           => cfg_soft_rst,
+    GBE_MAX_REPLY_OUT            => cfg_max_reply,
+    GBE_MAX_SUB_OUT              => cfg_max_sub,
+    GBE_MAX_QUEUE_OUT            => cfg_max_queue,
+    GBE_MAX_SUBS_IN_QUEUE_OUT    => cfg_max_subs_in_queue,
+    GBE_MAX_SINGLE_SUB_OUT       => cfg_max_single_sub,
+    GBE_AUTOTHROTTLE_OUT         => cfg_autothrottle,
+    GBE_THROTTLE_PAUSE_OUT       => cfg_throttle_pause,
+    MONITOR_RX_BYTES_IN          => sum_rx_bytes,
+    MONITOR_RX_FRAMES_IN         => sum_rx_frames,
+    MONITOR_TX_BYTES_IN          => sum_tx_bytes,
+    MONITOR_TX_FRAMES_IN         => sum_tx_frames,
+    MONITOR_TX_PACKETS_IN        => sum_tx_packets,
+    MONITOR_DROPPED_IN           => sum_dropped,
+    MONITOR_SELECT_REC_IN        => (others => '0'),
+    MONITOR_SELECT_REC_BYTES_IN  => (others => '0'),
+    MONITOR_SELECT_SENT_BYTES_IN => (others => '0'),
+    MONITOR_SELECT_SENT_IN       => (others => '0'),
+    MONITOR_SELECT_DROP_IN_IN    => (others => '0'),
+    MONITOR_SELECT_DROP_OUT_IN   => (others => '0'),
+    MONITOR_SELECT_GEN_DBG_IN    => monitor_gen_dbg,
+    MONITOR_IP_IN                => my_ip,
+    DUMMY_EVENT_SIZE_OUT         => dummy_event,
+    DUMMY_TRIGGERED_MODE_OUT     => dummy_mode,
+    DATA_HIST_IN                 => (others => (others => '0')),
+    SCTRL_HIST_IN                => (others => (others => '0'))
+  );
+
+  NOSCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL = '0') generate
+    GSC_INIT_DATAREADY_OUT  <= '0';
+    GSC_INIT_DATA_OUT       <= (others => '0');
+    GSC_INIT_PACKET_NUM_OUT <= (others => '0');
+    GSC_REPLY_READ_OUT      <= '1';
+    mlt_gsc_clk             <= (others => '0');
+    mlt_gsc_init_read       <= (others => '0');
+    mlt_gsc_reply_dataready <= (others => '0');
+    mlt_gsc_reply_data      <= (others => '0');
+    mlt_gsc_reply_packet    <= (others => '0');
+    mlt_gsc_busy            <= (others => '0');
+  end generate NOSCTRL_MAP_GEN;
+
+  SCTRL_MAP_GEN : if (LINK_HAS_SLOWCTRL /= '0') generate
+    ACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL = '1') generate
+      mlt_gsc_clk              <= GSC_CLK_IN;
+      GSC_INIT_DATAREADY_OUT   <= mlt_gsc_init_dataready;
+      GSC_INIT_DATA_OUT        <= mlt_gsc_init_data;
+      GSC_INIT_PACKET_NUM_OUT  <= mlt_gsc_init_packet;
+      mlt_gsc_init_read        <= GSC_INIT_READ_IN;
+      mlt_gsc_reply_dataready  <= GSC_REPLY_DATAREADY_IN;
+      mlt_gsc_reply_data       <= GSC_REPLY_DATA_IN;
+      mlt_gsc_reply_packet     <= GSC_REPLY_PACKET_NUM_IN;
+      GSC_REPLY_READ_OUT       <= mlt_gsc_reply_read;
+      mlt_gsc_busy             <= GSC_BUSY_IN;
+    end generate ACTIVE_MAP_GEN;
+
+    INACTIVE_MAP_GEN : if (LINK_HAS_SLOWCTRL = '0') generate
+      mlt_gsc_clk              <= '0';
+      mlt_gsc_init_read        <= '0';
+      mlt_gsc_reply_dataready  <= '0';
+      mlt_gsc_reply_data       <= (others => '0');
+      mlt_gsc_reply_packet     <= (others => '0');
+      mlt_gsc_busy             <= '0';
+    end generate INACTIVE_MAP_GEN;
+  end generate SCTRL_MAP_GEN;
+
+  sum_rx_bytes   <= monitor_rx_bytes;
+  sum_rx_frames  <= monitor_rx_frames;
+  sum_tx_bytes   <= monitor_tx_bytes;
+  sum_tx_frames  <= monitor_tx_frames;
+  sum_tx_packets <= monitor_tx_packets;
+  sum_dropped    <= monitor_dropped;
+
+end architecture RTL;
diff --git a/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd b/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd
index 53bf2a8..e36e26b 100644
--- a/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd
+++ b/gbe_trb_ecp3/base/gbe_wrapper_raw.vhd
@@ -39,29 +39,31 @@ entity gbe_wrapper_raw is
     GSR_N                     : in  std_logic;
     -- we connect to the MAC of gbe_med_raw directly
     -- MAC status and config
-    MAC_READY_CONF_IN     : in  std_logic;
-    MAC_RECONF_OUT        : out std_logic;
-    MAC_AN_READY_IN       : in  std_logic;
+    MAC_READY_CONF_IN     : in  std_logic; -- gbe_main_control
+    MAC_RECONF_OUT        : out std_logic; -- gbe_main_control
+    MAC_AN_READY_IN       : in  std_logic; -- gbe_main_control
     -- MAC data interface
-    MAC_FIFOAVAIL_OUT     : out  std_logic;
-    MAC_FIFOEOF_OUT       : out  std_logic;
-    MAC_FIFOEMPTY_OUT     : out  std_logic;
-    MAC_RX_FIFOFULL_OUT   : out  std_logic;
+    MAC_FIFOAVAIL_OUT     : out  std_logic; -- gbe_frame_trans -- frame ready for transmission
+    MAC_FIFOEOF_OUT       : out  std_logic; -- gbe_frame_trans -- end of transmission frame
+    MAC_FIFOEMPTY_OUT     : out  std_logic; -- gbe_frame_trans -- frame transmission FIFO empty
+    MAC_RX_FIFOFULL_OUT   : out  std_logic; -- gbe_frame_receiver --- FIFO full for MAC error handling
     -- MAC TX interface
-    MAC_TX_DATA_OUT       : out std_logic_vector(7 downto 0);
-    MAC_TX_READ_IN        : in  std_logic;
-    MAC_TX_DISCRFRM_IN    : in  std_logic;
-    MAC_TX_STAT_EN_IN     : in  std_logic;
-    MAC_TX_STATS_IN       : in  std_logic_vector(30 downto 0);
-    MAC_TX_DONE_IN        : in  std_logic;
+    MAC_TX_DATA_OUT       : out std_logic_vector(7 downto 0); -- gbe_frame_constr -- TX frame data
+    MAC_TX_READ_IN        : in  std_logic; -- gbe_frame_constr -- TX frame data read
+    MAC_TX_DISCRFRM_IN    : in  std_logic; -- gbe_frame_constr -- end of transmission in case of error 
+                                           -- gbe_frame_trans  -- end of transmission in case of error
+    MAC_TX_STATS_IN       : in  std_logic_vector(30 downto 0); -- gbe_frame_trans -- (0) used for statistics 
+    MAC_TX_STAT_EN_IN     : in  std_logic; -- gbe_frame_trans -- used for statistics
+    MAC_TX_DONE_IN        : in  std_logic; -- gbe_frame_constr -- end of transmission / statistics
+                                           -- gbe_frame_trans -- end of transmission / statistics
     -- MAC RX interface
-    MAC_RX_FIFO_ERR_IN    : in  std_logic;
-    MAC_RX_STATS_IN       : in  std_logic_vector(31 downto 0);
-    MAC_RX_DATA_IN        : in  std_logic_vector(7 downto 0);
-    MAC_RX_WRITE_IN       : in  std_logic;
-    MAC_RX_STAT_EN_IN     : in  std_logic;
-    MAC_RX_EOF_IN         : in  std_logic;
-    MAC_RX_ERROR_IN       : in  std_logic;
+    MAC_RX_FIFO_ERR_IN    : in  std_logic; -- gbe_frame_receiver -- UNUSED
+    MAC_RX_STATS_IN       : in  std_logic_vector(31 downto 0); -- gbe_frame_receiver -- UNUSED
+    MAC_RX_DATA_IN        : in  std_logic_vector(7 downto 0); -- gbe_frame_receiver -- RX frame data 
+    MAC_RX_WRITE_IN       : in  std_logic; -- gbe_frame_receiver -- data handling
+    MAC_RX_STAT_EN_IN     : in  std_logic; -- gbe_frame_receiver -- UNUSED
+    MAC_RX_EOF_IN         : in  std_logic; -- gbe_frame_receiver -- data parsing
+    MAC_RX_ERROR_IN       : in  std_logic; -- gbe_frame_receiver -- statistics
     --                        
     TRIGGER_IN                : in  std_logic; -- for debug purpose only
     -- CTS interface          
@@ -274,7 +276,7 @@ begin
     MAC_TX_DATA_OUT          => MAC_TX_DATA_OUT,
     MAC_TX_READ_IN           => MAC_TX_READ_IN,
     MAC_TX_DISCRFRM_IN       => MAC_TX_DISCRFRM_IN,
-    MAC_TX_STAT_EN_IN        => MAC_TX_STAT_EN_IN,
+    MAC_TX_STAT_EN_IN        => MAC_TX_STAT_EN_IN, -- BUG: signal not existing!
     MAC_TX_STATS_IN          => MAC_TX_STATS_IN,
     MAC_TX_DONE_IN           => MAC_TX_DONE_IN,
     MAC_RX_FIFO_ERR_IN       => MAC_RX_FIFO_ERR_IN,
-- 
2.43.0