From 483f06b4210ae678308d188d920329ba8a66aef9 Mon Sep 17 00:00:00 2001 From: "a.weber" Date: Tue, 14 Aug 2018 13:25:24 +0200 Subject: [PATCH] First working Calibration;All FPGAs as one; Chnls are separat calibrated -AW --- combiner_calib/combiner.vhd | 82 ++++++++++++++++++++++++++----------- 1 file changed, 59 insertions(+), 23 deletions(-) diff --git a/combiner_calib/combiner.vhd b/combiner_calib/combiner.vhd index 355bf9c..012f5c6 100644 --- a/combiner_calib/combiner.vhd +++ b/combiner_calib/combiner.vhd @@ -185,10 +185,10 @@ architecture arch of combiner is signal sse_fee_addr : std_logic_vector(15 downto 0); signal pckr_Data_type : std_logic_vector( 3 downto 0); - signal cts_data : std_logic_vector(31 downto 0); + signal cts_data : std_logic_vector(31 downto 0) := x"F0F1F2F3"; signal cts_length : std_logic_vector(15 downto 0); signal cts_read : std_logic; - signal cts_dataready : std_logic; + signal cts_dataready : std_logic := '0'; signal cts_finished : std_logic; signal pckr_fifo_full : std_logic; @@ -208,7 +208,7 @@ architecture arch of combiner is signal DEBUG_EvtLength : unsigned(15 downto 0); signal already_asked : std_logic := '0'; - signal rd_enabled : std_logic := '0'; + signal rd_enabled : std_logic := '1'; signal my_network_address : std_logic_vector(15 downto 0); --------------------------- @@ -225,6 +225,10 @@ architecture arch of combiner is signal MUX_cal_dout_stat : std_logic_vector(31 downto 0); signal MUX_cal_sw : std_logic := '0'; + signal DEBUG_read_enable_fifo_vnt : std_logic_vector(31 downto 0); + signal DEBUG_read_enable_fifo_cnt : std_logic_vector(31 downto 0); + signal DEBUG_read_enable_fifo_vnt1 : std_logic_vector(31 downto 0); + signal DEBUG_read_enable_fifo_cnt2 : std_logic_vector(31 downto 0); component FIFO_36x64 is port ( Data: in std_logic_vector(35 downto 0); @@ -828,39 +832,40 @@ back_slave_ready_i <= BACK_SLAVE_READY; ----------------------------------------------------------------------- THE_DATAPACKER_FSM_TX : process --data buffer is necessary - variable EvInf_TX : std_logic_vector(31 downto 0); - variable EvLength_TX : std_logic_vector(15 downto 0); + variable EvInf_TX : std_logic_vector(31 downto 0); + variable EvLength_TX : std_logic_vector(15 downto 0); variable EvLength_TX_cntr : unsigned(15 downto 0); - variable Header_ready : std_logic:='0'; - variable Data_Fifo : std_logic_vector(35 downto 0); - variable pckr_TX_data : std_logic_vector(31 downto 0); + variable Header_ready : std_logic:='0'; + variable Data_Fifo : std_logic_vector(35 downto 0); + variable pckr_TX_data : std_logic_vector(31 downto 0); variable pckr_TX_data_type : std_logic_vector( 3 downto 0); - variable buf_fifo_0 : std_logic_vector(35 downto 0); - variable buf_fifo_1 : std_logic_vector(35 downto 0); - variable buf_fifo_2 : std_logic_vector(35 downto 0); - variable buf_fifo_cnt : std_logic_vector( 1 downto 0) := "00"; - variable enable_fifo_rdEn : std_logic; + variable buf_fifo_0 : std_logic_vector(35 downto 0); + variable buf_fifo_1 : std_logic_vector(35 downto 0); + variable buf_fifo_2 : std_logic_vector(35 downto 0); + variable buf_fifo_cnt : std_logic_vector( 1 downto 0) := "00"; + variable enable_fifo_rdEn : std_logic; variable pckr_TX_data_ready : std_logic; - variable dataready : std_logic; + variable dataready : std_logic; begin wait until rising_edge(clk_sys); - cts_finished <= '0'; - fifo_rdEn <= '0'; + fifo_rdEn <= '0'; fifo_rdEn_r <= fifo_rdEn; fifo_rdEn_2r <= fifo_rdEn_r; --2r is readySignal dataready := '0'; - + --is executed if reset_i = '1' then pckr_TX_state <= EVNT; already_asked <= '0'; else + if already_asked = '0' then if cts_dataready = '0' then already_asked <= '1'; rd_enabled <= '0'; + DEBUG_read_enable_fifo_cnt <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_cnt) + 1); end if; end if; @@ -868,10 +873,13 @@ back_slave_ready_i <= BACK_SLAVE_READY; if pckr_fifo_empty = '0' and rd_enabled = '0' then fifo_rdEn <= '1'; rd_enabled <= '1'; + else + end if; if fifo_rdEn_2r = '1' then dataready := '1'; already_asked <= '0'; + DEBUG_read_enable_fifo_cnt2 <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_cnt2) + 1); pckr_TX_data := fifo_data_out(31 downto 0); pckr_TX_data_type := fifo_data_out(35 downto 32); end if; @@ -882,11 +890,12 @@ back_slave_ready_i <= BACK_SLAVE_READY; when EVNT => if cts_start_readout = '1' then if dataready = '1' then + DEBUG_read_enable_fifo_vnt1 <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_vnt1) + 1); if pckr_TX_data_type = x"1" then --EvInf_TX := pckr_TX_data; cts_data <= pckr_TX_data; end if; --maybe a flag that x"1" is set before x"2" comes? - + if pckr_TX_data_type = x"2" then cts_length <= pckr_TX_data(31 downto 16); EvLength_TX_cntr := pckr_TX_data(31 downto 16); @@ -895,8 +904,9 @@ back_slave_ready_i <= BACK_SLAVE_READY; end if; --cts_data <= EvInf_TX; --cts_length <= EvLength_TX; - + if Header_ready = '1' then + DEBUG_read_enable_fifo_vnt <= std_logic_vector(unsigned(DEBUG_read_enable_fifo_vnt) + 1); cts_dataready <= '1'; if cts_read = '1' and cts_dataready = '1' then pckr_TX_state <= DATA; @@ -938,10 +948,10 @@ back_slave_ready_i <= BACK_SLAVE_READY; end case; - DEBUG_enable_fifo_rdEn <= enable_fifo_rdEn; - - end if; - end process; + DEBUG_enable_fifo_rdEn <= enable_fifo_rdEn; + DEBUG_cts_dataready <= dataready; + end if; + end process; @@ -1047,6 +1057,32 @@ back_slave_ready_i <= BACK_SLAVE_READY; busdebug_tx.data( 0) <= MUX_cal_sw; busdebug_tx.data(31 downto 1) <= (others => '0'); end if; + if busdebug_rx.addr( 7 downto 0) = x"0D" then + busdebug_tx.data(23 downto 0) <= DEBUG_read_enable_fifo_vnt(23 downto 0); + busdebug_tx.data(24) <= cts_dataready; + busdebug_tx.data(27 downto 25) <= (others => '0'); + busdebug_tx.data(28) <= already_asked; + busdebug_tx.data(31 downto 29) <= (others => '0'); + end if; + if busdebug_rx.addr( 7 downto 0) = x"0E" then + busdebug_tx.data <= cts_data; + end if; + if busdebug_rx.addr( 7 downto 0) = x"0F" then + busdebug_tx.data(15 downto 0) <= cts_length; + busdebug_tx.data(31 downto 15) <= (others => '0'); + end if; + + if busdebug_rx.addr( 7 downto 0) = x"10" then + busdebug_tx.data(30 downto 0) <= DEBUG_read_enable_fifo_cnt(30 downto 0); + busdebug_tx.data(31) <= rd_enabled; + end if; + if busdebug_rx.addr( 7 downto 0) = x"11" then + busdebug_tx.data(30 downto 0) <= DEBUG_read_enable_fifo_vnt1(30 downto 0); + busdebug_tx.data(31) <= cts_read; + end if; + if busdebug_rx.addr( 7 downto 0) = x"12" then + busdebug_tx.data <= DEBUG_read_enable_fifo_cnt2; + end if; busdebug_tx.ack <= '1'; elsif busdebug_rx.write = '1' then -- 2.43.0