From 49b1215e5ed98f3cfb3a2b3e28e890104e4c347c Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Fri, 4 Oct 2013 23:58:37 +0200 Subject: [PATCH] cleanup nxyter stuff --- nxyter/compile_munich2.pl | 156 -------------- nxyter/compile_munich20.sh | 5 - ...ompile_munich20.pl => compile_munich21.pl} | 4 +- ...{compile_munich.sh => compile_munich21.sh} | 2 +- nxyter/source/nx_data_delay.vhd | 9 +- nxyter/source/nx_data_receiver.vhd | 194 +++++++++++------- nxyter/source/nx_fpga_timestamp.vhd | 28 ++- nxyter/source/nx_trigger_validate.vhd | 45 ++-- nxyter/source/nxyter_components.vhd | 2 + nxyter/source/nxyter_fee_board.vhd | 58 +----- nxyter/source/registers.txt | 65 +++--- nxyter/trb3_periph.vhd | 23 +-- nxyter/trb3_periph_constraints.lpf | 101 ++++----- 13 files changed, 263 insertions(+), 429 deletions(-) delete mode 100755 nxyter/compile_munich2.pl delete mode 100755 nxyter/compile_munich20.sh rename nxyter/{compile_munich20.pl => compile_munich21.pl} (95%) rename nxyter/{compile_munich.sh => compile_munich21.sh} (74%) diff --git a/nxyter/compile_munich2.pl b/nxyter/compile_munich2.pl deleted file mode 100755 index c5c2b62..0000000 --- a/nxyter/compile_munich2.pl +++ /dev/null @@ -1,156 +0,0 @@ -#!/usr/bin/perl -use Data::Dumper; -use warnings; -use strict; - - - - -################################################################################### -#Settings for this project -my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1'; -my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; -my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; -my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; -################################################################################### - - - - - - - - -use FileHandle; - -$ENV{'SYNPLIFY'}=$synplify_path; -$ENV{'SYN_DISABLE_RAINBOW_DONGLE'}=1; -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; - - - - -my $FAMILYNAME="LatticeECP3"; -my $DEVICENAME="LFE3-150EA"; -my $PACKAGE="FPBGA672"; -my $SPEEDGRADE="8"; - - -#create full lpf file -system("cp ../base/$TOPNAME"."_nxyter.lpf workdir/$TOPNAME.lpf"); -system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); - - -#set -e -#set -o errexit - -#generate timestamp -my $t=time; -my $fh = new FileHandle(">version.vhd"); -die "could not open file" if (! defined $fh); -print $fh <close; - -system("env| grep LM_"); -my $r = ""; - -my $c="$synplify_path/bin/synplify_premier_dp -batch $TOPNAME.prj"; -$r=execute($c, "do_not_exit" ); - - -chdir "workdir"; -$fh = new FileHandle("<$TOPNAME".".srr"); -my @a = <$fh>; -$fh -> close; - - - -foreach (@a) -{ - if(/\@E:/) - { - print "\n"; - $c="cat $TOPNAME.srr | grep \"\@E\""; - system($c); - print "\n\n"; - exit 129; - } -} - - -$ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_par; - -$c=qq| $lattice_path/ispfpga/bin/lin64/edif2ngd -path "../" -path "." -l $FAMILYNAME -d $DEVICENAME "$TOPNAME.edf" "$TOPNAME.ngo" |; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin64/edfupdate -t "$TOPNAME.tcy" -w "$TOPNAME.ngo" -m "$TOPNAME.ngo" "$TOPNAME.ngx"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin64/ngdbuild -a $FAMILYNAME -d $DEVICENAME -p "$lattice_path/ispfpga/ep5c00/data" -dt "$TOPNAME.ngo" "$TOPNAME.ngd"|; -execute($c); - -my $tpmap = $TOPNAME . "_map" ; - -$c=qq|$lattice_path/ispfpga/bin/lin64/map -retime -split_node -a $FAMILYNAME -p $DEVICENAME -t $PACKAGE -s $SPEEDGRADE "$TOPNAME.ngd" -pr "$TOPNAME.prf" -o "$tpmap.ncd" -mp "$TOPNAME.mrp" "$TOPNAME.lpf"|; -execute($c); - -system("rm $TOPNAME.ncd"); - - -#$c=qq|$lattice_path/ispfpga/bin/lin64/par "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; -$c=qq|$lattice_path/bin/lin64/mpartrce -p "../$TOPNAME.p2t" -f "$TOPNAME.p3t" -tf "$TOPNAME.pt" "$tpmap.ncd" "$TOPNAME.ncd"|; -execute($c); - -# IOR IO Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin64/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -# TWR Timing Report -$c=qq|$lattice_path/ispfpga/bin/lin64/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin64/trce -hld -c -v 5 -o "$TOPNAME.twr.hold" "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin64/ltxt2ptxt $TOPNAME.ncd|; -execute($c); - -$c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w -g CfgMode:Disable -g RamCfg:Reset -g ES:No $TOPNAME.ncd $TOPNAME.bit $TOPNAME.prf|; -# $c=qq|$lattice_path/ispfpga/bin/lin64/bitgen -w "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); - -chdir ".."; - -exit; - -sub execute { - my ($c, $op) = @_; - #print "option: $op \n"; - $op = "" if(!$op); - print "\n\ncommand to execute: $c \n"; - $r=system($c); - if($r) { - print "$!"; - if($op ne "do_not_exit") { - exit; - } - } - - return $r; - -} diff --git a/nxyter/compile_munich20.sh b/nxyter/compile_munich20.sh deleted file mode 100755 index bed8cfa..0000000 --- a/nxyter/compile_munich20.sh +++ /dev/null @@ -1,5 +0,0 @@ -#!/bin/sh - -. /usr/local/opt/lattice_diamond/diamond/2.0/bin/lin/diamond_env - -exec ./compile_munich20.pl diff --git a/nxyter/compile_munich20.pl b/nxyter/compile_munich21.pl similarity index 95% rename from nxyter/compile_munich20.pl rename to nxyter/compile_munich21.pl index cfa5edb..5f2a17b 100755 --- a/nxyter/compile_munich20.pl +++ b/nxyter/compile_munich21.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph"; #Name of top-level entity -my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.0'; +my $lattice_path = '/usr/local/opt/lattice_diamond/diamond/2.1'; my $synplify_path = '/usr/local/opt/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -112,7 +112,7 @@ execute($c); system("rm $TOPNAME.ncd"); -$c=qq|$lattice_path/ispfpga/bin/lin/multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; execute($c); # IOR IO Timing Report diff --git a/nxyter/compile_munich.sh b/nxyter/compile_munich21.sh similarity index 74% rename from nxyter/compile_munich.sh rename to nxyter/compile_munich21.sh index f5574ea..8a73754 100755 --- a/nxyter/compile_munich.sh +++ b/nxyter/compile_munich21.sh @@ -2,4 +2,4 @@ . /usr/local/opt/lattice_diamond/diamond/2.1/bin/lin64/diamond_env -exec ./compile_munich2.pl +exec ./compile_munich21.pl diff --git a/nxyter/source/nx_data_delay.vhd b/nxyter/source/nx_data_delay.vhd index 18e0a4a..e1f41db 100644 --- a/nxyter/source/nx_data_delay.vhd +++ b/nxyter/source/nx_data_delay.vhd @@ -21,7 +21,9 @@ entity nx_data_delay is NX_FRAME_OUT : out std_logic_vector(31 downto 0); ADC_DATA_OUT : out std_logic_vector(11 downto 0); NEW_DATA_OUT : out std_logic; - + + DATA_DELAY_VALUE_OUT : out unsigned(6 downto 0); + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -194,7 +196,7 @@ begin elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is when x"0000" => - if (unsigned(SLV_DATA_IN(6 downto 0)) >= 2 and + if (unsigned(SLV_DATA_IN(6 downto 0)) >= 1 and unsigned(SLV_DATA_IN(6 downto 0)) <= 120) then fifo_delay <= SLV_DATA_IN(6 downto 0); fifo_delay_reset <= '1'; @@ -217,7 +219,8 @@ begin NX_FRAME_OUT <= nx_frame_o; ADC_DATA_OUT <= adc_data_o; NEW_DATA_OUT <= new_data_o; - + DATA_DELAY_VALUE_OUT <= unsigned(fifo_delay); + SLV_DATA_OUT <= slv_data_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 29e2885..914af84 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -34,7 +34,7 @@ entity nx_data_receiver is NEW_DATA_OUT : out std_logic; TIMESTAMP_CURRENT_IN : in unsigned(11 downto 0); - + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -93,7 +93,13 @@ architecture Behavioral of nx_data_receiver is signal johnson_ff_1 : std_logic; signal adc_clk_inv : std_logic; signal adc_clk_delay : std_logic_vector(2 downto 0); + signal adc_clk_ok : std_logic; + -- ADC RESET + signal adc_clk_ok_last : std_logic; + signal adc_reset_s : std_logic; + signal adc_reset_ctr : unsigned(11 downto 0); + ----------------------------------------------------------------------------- -- CLK_IN Domain ----------------------------------------------------------------------------- @@ -105,8 +111,6 @@ architecture Behavioral of nx_data_receiver is signal nx_fifo_data_valid_t : std_logic; signal nx_fifo_data_valid : std_logic; - signal nx_fifo_delay_r : std_logic_vector(2 downto 0); - -- NX FIFO READ signal nx_timestamp_t : std_logic_vector(31 downto 0); signal nx_new_timestamp : std_logic; @@ -130,13 +134,13 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- ADC Handler - signal adc_reset_r : std_logic; - signal adc_reset_l : std_logic; - signal adc_reset : std_logic; - - signal adc_data : std_logic_vector(11 downto 0); - signal test_adc_data : std_logic_vector(11 downto 0); - signal adc_data_valid : std_logic; + signal adc_reset_r : std_logic; + signal adc_reset_l : std_logic; + signal adc_reset : std_logic; + + signal adc_data : std_logic_vector(11 downto 0); + signal test_adc_data : std_logic_vector(11 downto 0); + signal adc_data_valid : std_logic; signal adc_data_t : std_logic_vector(11 downto 0); signal adc_new_data : std_logic; @@ -169,20 +173,51 @@ begin DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN; - DEBUG_OUT(2) <= TRIGGER_IN; --nx_fifo_reset; - - PROC_DEBUG_MULT: process(adc_data_valid, - test_adc_data) + DEBUG_OUT(2) <= TRIGGER_IN; + + PROC_DEBUG_MULT: process(debug_adc, + adc_data, + adc_data_valid, + test_adc_data, + adc_clk_ok, + adc_clk_ok_last, + adc_clk_skip, + adc_reset_s, + adc_reset, + nx_new_frame, + adc_reset_ctr, + nx_fifo_full, + nx_fifo_write_enable, + nx_fifo_empty, + nx_fifo_read_enable, + nx_fifo_data_valid, + nx_new_timestamp, + adc_new_data, + STATE_d, + new_data_o, + nx_frame_synced, + rs_sync_reset + ) begin case debug_adc is when "01" => - DEBUG_OUT(15 downto 4) <= adc_data; DEBUG_OUT(3) <= adc_data_valid; + DEBUG_OUT(15 downto 4) <= adc_data; when "10" => - DEBUG_OUT(15 downto 4) <= test_adc_data; DEBUG_OUT(3) <= adc_data_valid; + DEBUG_OUT(15 downto 4) <= test_adc_data; + when "11" => + DEBUG_OUT(3) <= adc_clk_ok; + DEBUG_OUT(4) <= adc_clk_ok_last; + DEBUG_OUT(5) <= adc_clk_skip; + DEBUG_OUT(6) <= adc_reset_s; + DEBUG_OUT(7) <= adc_reset; + DEBUG_OUT(8) <= '0'; + DEBUG_OUT(9) <= nx_new_frame; + DEBUG_OUT(15 downto 10) <= adc_reset_ctr(5 downto 0) ; + when others => DEBUG_OUT(3) <= nx_fifo_full; DEBUG_OUT(4) <= nx_fifo_write_enable; @@ -265,7 +300,7 @@ begin -- Transfer 8 to 32Bit PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if( RESET_IN = '1' ) then frame_byte_ctr <= (others => '0'); nx_frame_word <= (others => '0'); @@ -296,11 +331,11 @@ begin -- Frame Sync process PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if( RESET_IN = '1' ) then - frame_byte_pos <= "11"; - rs_sync_set <= '0'; - rs_sync_reset <= '0'; + frame_byte_pos <= "11"; + rs_sync_set <= '0'; + rs_sync_reset <= '0'; else rs_sync_set <= '0'; rs_sync_reset <= '0'; @@ -335,7 +370,7 @@ begin -- RS FlipFlop to hold Sync Status PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if (RESET_IN = '1' or rs_sync_reset = '1') then nx_frame_synced <= '0'; elsif (rs_sync_set = '1') then @@ -349,7 +384,7 @@ begin variable parity_bits : std_logic_vector(22 downto 0); variable parity : std_logic; begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if (RESET_IN = '1') then parity_error <= '0'; else @@ -374,7 +409,7 @@ begin -- Write to FIFO PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) begin - if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (rising_edge(NX_TIMESTAMP_CLK_IN) ) then if (RESET_IN = '1') then nx_fifo_data_input <= (others => '0'); nx_fifo_write_enable <= '0'; @@ -407,26 +442,9 @@ begin nx_fifo_reset <= RESET_IN or fifo_reset_r; --- -- Reset NX_TIMESTAMP_CLK Domain --- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN) --- begin --- if( rising_edge(CLK_IN) ) then --- if( RESET_IN = '1' ) then --- reset_nx_domain_ctr <= (others => '0'); --- reset_nx_domain <= '1'; --- else --- if (nx_clk_pulse = '1') then --- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1; --- end if; --- --- end if; --- --- end if; --- end process PROC_NX_CLK_DOMAIN_RESET; - PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_TIMESTAMP_CLK_IN)) then if(RESET_IN = '1' ) then nx_clk_active_ff_0 <= '0'; nx_clk_active_ff_1 <= '0'; @@ -442,7 +460,7 @@ begin -- Johnson Counter PROC_ADC_CLK_GENERATOR: process(NX_TIMESTAMP_CLK_IN) begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_TIMESTAMP_CLK_IN)) then if (RESET_IN = '1') then johnson_ff_0 <= '0'; johnson_ff_1 <= '0'; @@ -457,7 +475,7 @@ begin PROC_ADC_CLK_DELAY_4NS: process(NX_TIMESTAMP_CLK_IN) begin - if(falling_edge(NX_TIMESTAMP_CLK_IN)) then + if (falling_edge(NX_TIMESTAMP_CLK_IN)) then if (RESET_IN = '1') then adc_clk_inv <= '0'; else @@ -471,21 +489,53 @@ begin PROC_ADC_CLK_DELAY: process(NX_TIMESTAMP_CLK_IN) variable adc_clk_state : std_logic_vector(1 downto 0); begin - if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (rising_edge(NX_TIMESTAMP_CLK_IN)) then if (RESET_IN = '1') then - adc_clk_skip <= '0'; + adc_clk_skip <= '0'; + adc_clk_ok <= '0'; else - adc_clk_state := johnson_ff_1 & johnson_ff_0; - adc_clk_skip <= '0'; - + adc_clk_state := johnson_ff_1 & johnson_ff_0; + adc_clk_skip <= '0'; if (nx_new_frame = '1') then if (adc_clk_state /= adc_clk_delay(2 downto 1)) then - adc_clk_skip <= '1'; + adc_clk_skip <= '1'; + adc_clk_ok <= '0'; + else + adc_clk_ok <= '1'; end if; end if; end if; end if; end process PROC_ADC_CLK_DELAY; + + PROC_ADC_RESET: process(NX_TIMESTAMP_CLK_IN) + begin + if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + adc_clk_ok_last <= '0'; + adc_reset_s <= '0'; + else + adc_reset_s <= '0'; + adc_clk_ok_last <= adc_clk_ok; + if (adc_clk_ok_last = '0' and adc_clk_ok = '1') then + adc_reset_s <= '1'; + end if; + end if; + end if; + end process PROC_ADC_RESET; + + PROC_RESET_CTR: process(NX_TIMESTAMP_CLK_IN) + begin + if (rising_edge(NX_TIMESTAMP_CLK_IN)) then + if (RESET_IN = '1') then + adc_reset_ctr <= (others => '0'); + else + if (adc_reset = '1') then + adc_reset_ctr <= adc_reset_ctr + 1; + end if; + end if; + end if; + end process PROC_RESET_CTR; ----------------------------------------------------------------------------- -- NX CLK_IN Domain @@ -496,7 +546,7 @@ begin PROC_NX_FIFO_READ_ENABLE: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if( RESET_IN = '1' or fifo_reset_r = '1') then nx_fifo_data_valid_t <= '0'; nx_fifo_data_valid <= '0'; @@ -510,7 +560,7 @@ begin PROC_NX_FIFO_READ: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if (RESET_IN = '1' or fifo_reset_r = '1') then nx_timestamp_t <= (others => '0'); nx_new_timestamp <= '0'; @@ -555,7 +605,7 @@ begin PROC_SYNC_FRAME_SYNC: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if(RESET_IN = '1' ) then reg_nx_frame_synced_t <= '0'; reg_nx_frame_synced <= '0'; @@ -569,9 +619,9 @@ begin -- Counters PROC_RESYNC_COUNTER: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if (RESET_IN = '1' or reset_resync_ctr = '1') then - resync_counter <= (others => '0'); + resync_counter <= (others => '0'); else if (resync_ctr_inc = '1') then resync_counter <= resync_counter + 1; @@ -582,7 +632,7 @@ begin PROC_PARITY_ERROR_COUNTER: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if (RESET_IN = '1' or reset_parity_error_ctr = '1') then parity_error_counter <= (others => '0'); else @@ -599,7 +649,7 @@ begin ----------------------------------------------------------------------------- PROC_ADC_DATA_READ: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if (RESET_IN = '1' or fifo_reset_r = '1') then adc_data_t <= (others => '0'); adc_new_data <= '0'; @@ -622,7 +672,7 @@ begin ----------------------------------------------------------------------------- PROC_OUTPUT_HANDLER: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if (RESET_IN = '1' or fifo_reset_r = '1') then nx_timestamp_o <= (others => '0'); adc_data_o <= (others => '0'); @@ -689,7 +739,7 @@ begin -- Give status info to the TRB Slow Control Channel PROC_FIFO_REGISTERS: process(CLK_IN) begin - if( rising_edge(CLK_IN) ) then + if (rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -697,7 +747,6 @@ begin slv_no_more_data_o <= '0'; reset_resync_ctr <= '0'; reset_parity_error_ctr <= '0'; - nx_fifo_delay_r <= "100"; fifo_reset_r <= '0'; adc_clk_delay <= "111"; adc_reset_r <= '0'; @@ -731,20 +780,16 @@ begin slv_ack_o <= '1'; when x"0002" => - slv_data_out_o(11 downto 0) <= resync_counter; + slv_data_out_o(11 downto 0) <= std_logic_vector(resync_counter); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"0003" => - slv_data_out_o(11 downto 0) <= parity_error_counter; + slv_data_out_o(11 downto 0) <= + std_logic_vector(parity_error_counter); slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - when x"0004" => - slv_data_out_o( 2 downto 0) <= nx_fifo_delay_r; - slv_data_out_o(31 downto 3) <= (others => '0'); - slv_ack_o <= '1'; - when x"0005" => case adc_clk_delay is when "010" => slv_data_out_o(2 downto 0) <= "000"; @@ -761,11 +806,16 @@ begin slv_ack_o <= '1'; when x"0006" => + slv_data_out_o(11 downto 0) <= std_logic_vector(adc_reset_ctr); + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0007" => slv_data_out_o(1 downto 0) <= debug_adc; slv_data_out_o(31 downto 2) <= (others => '0'); slv_ack_o <= '1'; - when x"0007" => + when x"0008" => slv_data_out_o(11 downto 0) <= adc_data_t; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; @@ -788,11 +838,6 @@ begin reset_parity_error_ctr <= '1'; slv_ack_o <= '1'; - when x"0004" => - nx_fifo_delay_r <= SLV_DATA_IN(2 downto 0); - fifo_reset_r <= '1'; - slv_ack_o <= '1'; - when x"0005" => if (SLV_DATA_IN < x"0000_0008") then case SLV_DATA_IN(2 downto 0) is @@ -805,11 +850,10 @@ begin when "110" => adc_clk_delay <= "110"; when "111" => adc_clk_delay <= "111"; end case; - adc_reset_r <= '1'; end if; slv_ack_o <= '1'; - when x"0006" => + when x"0007" => debug_adc <= SLV_DATA_IN(1 downto 0); slv_ack_o <= '1'; diff --git a/nxyter/source/nx_fpga_timestamp.vhd b/nxyter/source/nx_fpga_timestamp.vhd index 884a0f1..5059218 100644 --- a/nxyter/source/nx_fpga_timestamp.vhd +++ b/nxyter/source/nx_fpga_timestamp.vhd @@ -57,11 +57,17 @@ architecture Behavioral of nx_fpga_timestamp is begin - DEBUG_OUT(0) <= NX_CLK_IN; - DEBUG_OUT(1) <= trigger; - DEBUG_OUT(2) <= timestamp_sync; - DEBUG_OUT(3) <= '0'; - DEBUG_OUT(15 downto 4) <= timestamp_hold_o; + DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= TIMESTAMP_SYNC_IN; + DEBUG_OUT(2) <= nx_timestamp_sync_o; + DEBUG_OUT(3) <= TRIGGER_IN; + DEBUG_OUT(4) <= fifo_full; + DEBUG_OUT(5) <= fifo_write_enable; + DEBUG_OUT(6) <= fifo_empty; + DEBUG_OUT(7) <= fifo_read_enable; + DEBUG_OUT(8) <= fifo_data_valid_t; + DEBUG_OUT(9) <= fifo_data_valid; + DEBUG_OUT(15 downto 10) <= fifo_data_out(5 downto 0); -- NX Clock Domain @@ -108,7 +114,7 @@ begin if( rising_edge(NX_CLK_IN) ) then if( RESET_IN = '1' ) then timestamp_ctr <= (others => '0'); - timestamp_hold_o <= (others => '0'); + timestamp_hold <= (others => '0'); nx_timestamp_sync_o <= '0'; fifo_write_enable <= '0'; else @@ -117,7 +123,7 @@ begin if (timestamp_sync = '1') then timestamp_ctr <= (others => '0'); - timestamp_hold_o <= (others => '0'); + timestamp_hold <= (others => '0'); nx_timestamp_sync_o <= '1'; else if (trigger = '1' and fifo_full = '0') then @@ -154,18 +160,18 @@ begin PROC_RECEIVE_TS: process (CLK_IN) begin - if( rising_edge(NX_CLK_IN) ) then + if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then fifo_data_valid_t <= '0'; fifo_data_valid <= '0'; - timestamp_hold <= (others => '0'); + timestamp_hold_o <= (others => '0'); else if (fifo_data_valid = '1') then - timestamp_hold <= unsigned(fifo_data_out); + timestamp_hold_o <= unsigned(fifo_data_out); end if; fifo_data_valid_t <= fifo_read_enable; - fifo_data_valid <= fifo_data_valid; + fifo_data_valid <= fifo_data_valid_t; end if; end if; end process PROC_RECEIVE_TS; diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 7219ddc..1be6787 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -26,7 +26,8 @@ entity nx_trigger_validate is FAST_CLEAR_IN : in std_logic; TRIGGER_BUSY_OUT : out std_logic; TIMESTAMP_REF_IN : in unsigned(11 downto 0); - + DATA_DELAY_VALUE_IN : in unsigned(6 downto 0); + -- Outputs DATA_OUT : out std_logic_vector(31 downto 0); DATA_CLK_OUT : out std_logic; @@ -132,19 +133,21 @@ begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; + DEBUG_OUT(1) <= TRIGGER_IN; DEBUG_OUT(2) <= trigger_busy_o; - DEBUG_OUT(3) <= channel_all_done; - DEBUG_OUT(4) <= data_clk_o; - DEBUG_OUT(5) <= t_data_clk_o; - DEBUG_OUT(6) <= out_of_window_l; - DEBUG_OUT(7) <= out_of_window_h; - DEBUG_OUT(8) <= NX_TOKEN_RETURN_IN; - DEBUG_OUT(9) <= NX_NOMORE_DATA_IN; - DEBUG_OUT(10) <= store_to_fifo; - DEBUG_OUT(11) <= wait_timer_done; - DEBUG_OUT(12) <= timer_reset; - DEBUG_OUT(13) <= busy_time_min_done; - DEBUG_OUT(15 downto 14) <= (others => '0'); + DEBUG_OUT(3) <= DATA_CLK_IN; + DEBUG_OUT(4) <= out_of_window_l; + DEBUG_OUT(5) <= out_of_window_h; + DEBUG_OUT(6) <= NX_TOKEN_RETURN_IN; + DEBUG_OUT(7) <= NX_NOMORE_DATA_IN; + DEBUG_OUT(8) <= channel_all_done; + DEBUG_OUT(9) <= store_to_fifo; + DEBUG_OUT(10) <= data_clk_o; + DEBUG_OUT(11) <= t_data_clk_o; + DEBUG_OUT(12) <= wait_timer_done; + DEBUG_OUT(13) <= timer_reset; + DEBUG_OUT(14) <= busy_time_min_done; + DEBUG_OUT(15) <= nomore_data_o; -- Timer nx_timer_1: nx_timer @@ -547,23 +550,29 @@ begin slv_data_out_o(11 downto 0) <= window_upper_thr_r; slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; - + when x"0008" => + slv_data_out_o(6 downto 0) <= + std_logic_vector(DATA_DELAY_VALUE_IN); + slv_data_out_o(31 downto 7) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0009" => slv_data_out_o <= std_logic_vector(channel_done(31 downto 0)); slv_ack_o <= '1'; - when x"0009" => + when x"000a" => slv_data_out_o <= std_logic_vector(channel_done(63 downto 32)); slv_ack_o <= '1'; - when x"000a" => + when x"000b" => slv_data_out_o <= std_logic_vector(channel_done(95 downto 64)); slv_ack_o <= '1'; - when x"000b" => + when x"000c" => slv_data_out_o <= std_logic_vector(channel_done(127 downto 96)); slv_ack_o <= '1'; @@ -593,7 +602,7 @@ begin readout_time_max <= unsigned(SLV_DATA_IN(11 downto 0)); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; slv_ack_o <= '0'; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index e4f44d6..0ca8eb2 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -368,6 +368,7 @@ component nx_data_delay NX_FRAME_OUT : out std_logic_vector(31 downto 0); ADC_DATA_OUT : out std_logic_vector(11 downto 0); NEW_DATA_OUT : out std_logic; + DATA_DELAY_VALUE_OUT : out unsigned(6 downto 0); SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; SLV_DATA_OUT : out std_logic_vector(31 downto 0); @@ -424,6 +425,7 @@ component nx_trigger_validate FAST_CLEAR_IN : in std_logic; TRIGGER_BUSY_OUT : out std_logic; TIMESTAMP_REF_IN : in unsigned(11 downto 0); + DATA_DELAY_VALUE_IN : in unsigned(6 downto 0); DATA_OUT : out std_logic_vector(31 downto 0); DATA_CLK_OUT : out std_logic; NOMORE_DATA_OUT : out std_logic; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index f87438a..8aaed58 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -143,7 +143,8 @@ architecture Behavioral of nXyter_FEE_board is signal new_timestamp_delayed : std_logic_vector(31 downto 0); signal new_adc_data_delayed : std_logic_vector(11 downto 0); signal new_data_delayed : std_logic; - + signal new_data_delay_value : unsigned(6 downto 0); + -- Data Validate signal timestamp : std_logic_vector(13 downto 0); signal timestamp_channel_id : std_logic_vector(6 downto 0); @@ -201,53 +202,10 @@ begin ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- --- DEBUG_LINE_OUT(0) <= nx_testpulse_o; --CLK_IN; --- DEBUG_LINE_OUT(1) <= NX_CLK128_IN; --- DEBUG_LINE_OUT(2) <= ADC_SAMPLE_CLK_OUT; --- DEBUG_LINE_OUT(7 downto 3) <= (others => '0'); --- DEBUG_LINE_OUT(15 downto 8) <= NX_TIMESTAMP_IN; --- DEBUG_LINE_OUT(4) <= nx_new_timestamp; --- DEBUG_LINE_OUT(5) <= timestamp_valid; --- DEBUG_LINE_OUT(6) <= timestamp_trigger; --- DEBUG_LINE_OUT(7) <= nx_token_return; --- DEBUG_LINE_OUT(8) <= nx_nomore_data; --- DEBUG_LINE_OUT(9) <= trigger; --- DEBUG_LINE_OUT(10) <= trigger_busy; --- DEBUG_LINE_OUT(11) <= ts_data_clk; --- DEBUG_LINE_OUT(12) <= data_fifo_reset; --- --- DEBUG_LINE_OUT(14 downto 13) <= timestamp_status; --- DEBUG_LINE_OUT(15) <= slv_ack(3); - --- DEBUG_LINE_OUT(0) <= CLK_IN; --- DEBUG_LINE_OUT(1) <= CLK_125_IN; --- DEBUG_LINE_OUT(2) <= clk_250_o; --- DEBUG_LINE_OUT(3) <= NX_CLK128_IN; --- DEBUG_LINE_OUT(4) <= nx_timestamp(0); --- DEBUG_LINE_OUT(15 downto 5) <= (others => '0'); - --DEBUG_LINE_OUT(5) <= timestamp_valid; - --DEBUG_LINE_OUT(6) <= nx_token_return; - --DEBUG_LINE_OUT(7) <= nx_nomore_data; - --- DEBUG_LINE_OUT(0) <= NX_CLK128_IN; --- DEBUG_LINE_OUT(8 downto 1) <= NX_TIMESTAMP_IN; --- DEBUG_LINE_OUT(13 downto 9) <= (others => '0'); --- DEBUG_LINE_OUT(15) <= CLK_IN; --- DEBUG_LINE_OUT(5) <= '0'; --- DEBUG_LINE_OUT(6) <= '0'; --- DEBUG_LINE_OUT(7) <= '0'; --- --- --- DEBUG_LINE_OUT(8) <= ADC_FCLK_IN; --- DEBUG_LINE_OUT(10) <= ADC_SC_CLK32_OUT; --- DEBUG_LINE_OUT(11) <= ADC_A_IN; --- DEBUG_LINE_OUT(12) <= ADC_B_IN; --- DEBUG_LINE_OUT(13) <= ADC_NX_IN; --- DEBUG_LINE_OUT(14) <= ADC_D_IN; --- DEBUG_LINE_OUT(15) <= '0'; + -- DEBUG_LINE_OUT(0) <= CLK_IN; + -- DEBUG_LINE_OUT(15 downto 0) <= (others => '0'); + -- See Multiplexer --- DEBUG_LINE_OUT(15 downto 8) <= slv_read(9 downto 2); - ------------------------------------------------------------------------------- -- Port Maps ------------------------------------------------------------------------------- @@ -274,7 +232,7 @@ begin PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler 1 => 0, -- I2C master - 2 => 3, -- Data Receiver + 2 => 4, -- Data Receiver 3 => 3, -- Data Buffer 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator @@ -579,7 +537,8 @@ begin NX_FRAME_OUT => new_timestamp_delayed, ADC_DATA_OUT => new_adc_data_delayed, NEW_DATA_OUT => new_data_delayed, - + DATA_DELAY_VALUE_OUT => new_data_delay_value, + SLV_READ_IN => slv_read(12), SLV_WRITE_IN => slv_write(12), SLV_DATA_OUT => slv_data_rd(12*32+31 downto 12*32), @@ -650,6 +609,7 @@ begin FAST_CLEAR_IN => fast_clear, TRIGGER_BUSY_OUT => trigger_validate_busy, TIMESTAMP_REF_IN => timestamp_hold, + DATA_DELAY_VALUE_IN => new_data_delay_value, DATA_OUT => trigger_data, DATA_CLK_OUT => trigger_data_clk, diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index b6709b0..6a76a87 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -28,12 +28,12 @@ -- NX Data Receiver 0x8500 : r current Timestamp FIFO value 0x8501 : r/w r: FIFO Status - 0: fifo_full - 1: fifo_empty - 2: fifo_almost_empty - 3..29: ignore - 31: nx_frame_synced - w: pll reset + 0: fifo_full + 1: fifo_empty + 2: fifo_almost_empty + 3..29: ignore + 31: nx_frame_synced + w: adc reset 0x8502 : r/w r: Resync Counter(12bit) w: clear Resync Counter 0x8503 : r/w r: Parity Error Counter (12bit) @@ -45,14 +45,16 @@ 6: 28ns -------"--------- 7: 32ns -------"--------- <= this shoud be correct i.e. 2ns before new frame clock -0x8506 : r/w debug multiplexer: +0x8506 : r ADC Reset Counter +0x8507 : r/w Debug Multiplexer: 0: no ADC Values, normal Debug 1: ADC Value Nxyter 2: ADC Value Testchannel -0x8507 : r current ADC FIFO value + 3: ADC Reset Handler +0x8508 : r current ADC FIFO value -- NX Data Delay -0x8130 : r/w FIFO Delay, i.e. Trigger Delay (7Bit, in 10ns, Range 2..120) +0x8130 : r/w FIFO Delay, i.e. Trigger Delay (7Bit, in 31.25ns, Range 2..120) default: 10 -- NX Data Validate @@ -75,10 +77,11 @@ 0x8185 : r timestamp_ref 0x8186 : r window_lower_thr 0x8187 : r window_upper_thr -0x8188 : r done counter ch 0..31 -0x8189 : r done counter ch 32..63 -0x818a : r done counter ch 94..95 -0x818b : r done counter ch 96..127 +0x8188 : r current Data Delay Value +0x8189 : r done counter ch 0..31 +0x818a : r done counter ch 32..63 +0x818b : r done counter ch 94..95 +0x818c : r done counter ch 96..127 -- Event Data Buffer 0x8600 : r read FIFO buffer @@ -97,24 +100,24 @@ 0x8060 : Access to SPI Interface -- Histogram Handler -0x8800 : r: Read Channel Statistic (128 channel in a row) - w: reset all Histograms -0x8880 : r: Read Channel Trigger Rate (128 channel in a row, 1/s) -0x8900 : r: Read Channel ADC Value (128 channel in a row) +0x8800 : r/w r: Read Channel Statistic (128 channel in a row) + w: reset all Histograms +0x8880 : r Read Channel Trigger Rate (128 channel in a row, 1/s) +0x8900 : r Read Channel ADC Value (128 channel in a row) -- Debug Multiplexer -0x8020 : r/w Select Debug Entity - 0: nxyter_registers - 1: nx_setup - 2: nx_i2c_master - 3: adc_spi_master - 4: nx_fpga_timestamp - 5: nx_trigger_handler - 6: nx_trigger_generator - 7: nx_data_receiver - 8: nx_data_delay - 9: nx_data_validate - 10: nx_trigger_validate - 11: nx_event_buffer - 12: nx_histograms +0x8020 : r/w Select Debug Entity + 0: nxyter_registers + 1: nx_setup + 2: nx_i2c_master + 3: adc_spi_master + 4: nx_fpga_timestamp + 5: nx_trigger_handler + 6: nx_trigger_generator + 7: nx_data_receiver + 8: nx_data_delay + 9: nx_data_validate + 10: nx_trigger_validate + 11: nx_event_buffer + 12: nx_histograms diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index ba13427..49adc63 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -100,7 +100,6 @@ entity trb3_periph is -- END AddonBoard nXyter --------------------------------------------------------------------------- - --Flash ROM & Reboot FLASH_CLK : out std_logic; FLASH_CS : out std_logic; @@ -279,9 +278,10 @@ architecture trb3_periph_arch of trb3_periph is -- nXyter-FEB-Board Clocks signal nx_main_clk : std_logic; signal pll_nx_clk_lock : std_logic; - signal clk_adc_dat_2 : std_logic; signal clk_adc_dat_1 : std_logic; - signal pll_adc_clk_lock : std_logic; + signal clk_adc_dat_2 : std_logic; + signal pll_adc_clk_lock_1 : std_logic; + signal pll_adc_clk_lock_2 : std_logic; -- nXyter 1 Regio Bus signal nx1_regio_addr_in : std_logic_vector (15 downto 0); @@ -329,7 +329,7 @@ begin port map( CLEAR_IN => '0', -- reset input (high active, async) CLEAR_N_IN => '1', -- reset input (low active, async) - CLK_IN => clk_200_i, -- raw master clock, NOT from PLL/DLL! + CLK_IN => CLK_PCLK_RIGHT, -- raw master clock, NOT from PLL/DLL! SYSCLK_IN => clk_100_i, -- PLL/DLL remastered clock PLL_LOCKED_IN => pll_lock, -- master PLL lock signal (async) RESET_IN => '0', -- general reset signal (SYSCLK) @@ -364,7 +364,7 @@ begin USE_CTC => c_NO ) port map( - CLK => clk_200_i, + CLK => CLK_PCLK_RIGHT, SYSCLK => clk_100_i, RESET => reset_i, CLEAR => clear_i, @@ -845,7 +845,7 @@ begin -- nXyter Main Clock (250/256 MHz) pll_nx_clk250_1: entity work.pll_nx_clk250 port map ( - CLK => clk_200_i, + CLK => CLK_PCLK_RIGHT, CLKOP => nx_main_clk, LOCK => pll_nx_clk_lock ); @@ -853,23 +853,22 @@ begin NX1_CLK256A_OUT <= nx_main_clk; NX2_CLK256A_OUT <= nx_main_clk; - -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be base on same - -- ClockSource as nXyter Main Clock) + -- ADC Receiver Clock (nXyter Main Clock * 3/4 (187.5), must be + -- based on same ClockSource as nXyter Main Clock) pll_adc_clk_1: pll_adc_clk port map ( CLK => CLK_PCLK_RIGHT, CLKOP => clk_adc_dat_1, - LOCK => pll_adc_clk_lock + LOCK => pll_adc_clk_lock_1 ); + pll_adc_clk_2: pll_adc_clk port map ( CLK => CLK_PCLK_RIGHT, CLKOP => clk_adc_dat_2, - LOCK => pll_adc_clk_lock + LOCK => pll_adc_clk_lock_2 ); - ----------------------------------------------------------------------------- - ------------------------------------------------------------------------------- -- Timestamp Simulator ------------------------------------------------------------------------------- diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 5af8655..69cab84 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -1,107 +1,77 @@ -# BLOCK RESETPATHS ; -# BLOCK ASYNCPATHS ; -# BLOCK RD_DURING_WR_PATHS ; +BLOCK RESETPATHS ; +BLOCK ASYNCPATHS ; +BLOCK RD_DURING_WR_PATHS ; ################################################################# # Basic Settings ################################################################# - #Speed for the configuration Flash access - SYSCONFIG MCCLK_FREQ = 20; - - - # Clock Setup: + # nXyter FEB Clock Setup: # - # CLK_GPLL_RIGHT : real Oszillator 200MHz - # CLK_GPLL_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities - # CLK_GPLL_RIGHT --> PLL#0 --> clk_200_i -----> PLL#1 + # CLK_PCLK_RIGHT : real Oszillator 200MHz + # CLK_PCLK_RIGHT --> PLL#0 --> clk_100_i -----> Main Clock all entities # - # clk_200_i (PLL#1) --> nx_main_clk - # (250/256 MHz) -----> nXyter Main Clock + # CLK_PCLK_RIGHT --> nx_main_clk 1+2 + # (250/256 MHz) -----> nXyter Main Clock 1+2 # | - # |----> FPGA Timestamp Entity - # - # clk_200_i (PLL#1) --> clk_adc_dat - # (nx_main_clk * 3/8) -----> ADC Handler + # |----> FPGA Timestamp Entity 1+2 # - # nXyter Main Clock --> nXyter Data Clock -----> FPGA Data Receiver - # | + # nXyter Main Clock 1+2 --> nXyter Data Clk -----> FPGA Data Receiver + # (* 1/2) | # |----> Johnson 1/4 --> ADC SCLK + # + # CLK_PCLK_RIGHT (PLL#2) --> clk_adc_dat_1 + # (nx_main_clk * 3/4) -----> ADC Handler 1 + # + # CLK_PCLK_RIGHT (PLL#3) --> clk_adc_dat_2 + # (nx_main_clk * 3/4) -----> ADC Handler 2 + # Speed for the configuration Flash access + SYSCONFIG MCCLK_FREQ = 20; # Not used in current design #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + + FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT NX1_CLK128_IN 125 MHz; FREQUENCY PORT NX2_CLK128_IN 125 MHz; - FREQUENCY PORT NX1_ADC_SAMPLE_CLK_OUT 31.25 MHz; - FREQUENCY PORT NX2_ADC_SAMPLE_CLK_OUT 31.25 MHz; USE PRIMARY NET "nx_main_clk"; - USE PRIMARY NET "NX1_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "NX2_ADC_SAMPLE_CLK_OUT"; - USE PRIMARY NET "clk_200_i"; USE PRIMARY NET "clk_100_i_c"; USE PRIMARY NET "CLK_PCLK_RIGHT_c"; - #LOCATE COMP THE_MAIN_PLL/PLLInst_0 SITE PLL_R79C178; - - -# Put the names of your nxyter inputs here: - -# ------ ADC Stuff --------------------------- - -# ADC Settings - - - #FREQUENCY PORT clk_adc_dat 93.75 MHz; - #USE PRIMARY NET "clk_adc_dat"; - - #PROHIBIT PRIMARY NET "NX1_ADC_FCLK_IN"; - #PROHIBIT PRIMARY NET "NX1B_ADC_FCLK_IN"; - #PROHIBIT SECONDARY NET "NX1_ADC_FCLK_IN"; - #PROHIBIT SECONDARY NET "NX1B_ADC_FCLK_IN"; - #PROHIBIT PRIMARY NET "NX1_ADC_DCLK_IN"; - #PROHIBIT PRIMARY NET "NX1B_ADC_DCLK_IN"; - #PROHIBIT SECONDARY NET "NX1_ADC_DCLK_IN"; - #PROHIBIT SECONDARY NET "NX1B_ADC_DCLK_IN"; - - #PROHIBIT PRIMARY NET "NX2_ADC_FCLK_IN"; - #PROHIBIT PRIMARY NET "NX2B_ADC_FCLK_IN"; - #PROHIBIT SECONDARY NET "NX2_ADC_FCLK_IN"; - #PROHIBIT SECONDARY NET "NX2B_ADC_FCLK_IN"; - #PROHIBIT PRIMARY NET "NX2_ADC_DCLK_IN"; - #PROHIBIT PRIMARY NET "NX2B_ADC_DCLK_IN"; - #PROHIBIT SECONDARY NET "NX2_ADC_DCLK_IN"; - #PROHIBIT SECONDARY NET "NX2B_ADC_DCLK_IN"; - ################################################################# # Reset Nets ################################################################# -#GSR_NET NET "GSR_N"; - +# GSR_NET NET "GSR_N"; ################################################################# # Locate Serdes and media interfaces ################################################################# + LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; REGION "MEDIA_UPLINK" "R102C95D" 13 25; LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; - ################################################################# # Relax some of the timing constraints ################################################################# -# WARNING: matches no cells in the design. -#MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -#MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; - +MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns; MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/restart_i" 20 ns; -MULTICYCLE FROM CLKNET "nx_main_clk" 50 ns; + +MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 20 ns; +MULTICYCLE FROM CLKNET "nXyter_FEE_board_1/nx_data_receiver_1/adc_ad9222_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns; +MULTICYCLE FROM CLKNET "nXyter_FEE_board_0/nx_data_receiver_1/adc_ad9222_1/un1_adc_ad9222*" TO CLKNET "clk_100_i_c" 10 ns; + +MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/timestamp_sync_x" 5 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_0/nx_fpga_timestamp_1/trigger_x" 5 ns; + +MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_fpga_timestamp_1/timestamp_sync_x" 5 ns; +MULTICYCLE TO CELL "nXyter_FEE_board_1/nx_fpga_timestamp_1/trigger_x" 5 ns; ################################################################# # Constraints for nxyter inputs @@ -120,4 +90,3 @@ INPUT_SETUP GROUP "NX1_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN"; DEFINE PORT GROUP "NX2_IN" "NX2_TIMESTAMP_*"; INPUT_SETUP GROUP "NX2_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX2_CLK128_IN"; - -- 2.43.0