From 4a45448b834e83690d38441af1816e5d76d1ed5c Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Tue, 24 Jul 2012 16:48:12 +0000 Subject: [PATCH] *** empty log message *** --- gbe2_ecp3/trb_net16_gbe_buf.vhd | 12 +- gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd | 27 +++++ ...trb_net16_gbe_response_constructor_ARP.vhd | 66 ++++++++--- ...rb_net16_gbe_response_constructor_DHCP.vhd | 71 +++++++---- ...rb_net16_gbe_response_constructor_Ping.vhd | 64 +++++++--- ...b_net16_gbe_response_constructor_SCTRL.vhd | 110 +++++++++++++----- ...rb_net16_gbe_response_constructor_Stat.vhd | 21 +++- 7 files changed, 276 insertions(+), 95 deletions(-) diff --git a/gbe2_ecp3/trb_net16_gbe_buf.vhd b/gbe2_ecp3/trb_net16_gbe_buf.vhd index 143dbdc..96b2a08 100755 --- a/gbe2_ecp3/trb_net16_gbe_buf.vhd +++ b/gbe2_ecp3/trb_net16_gbe_buf.vhd @@ -1298,10 +1298,10 @@ imp_gen: if (DO_SIMULATION = 0) generate -------------------------------------------------------------------------------------------- - TIMEOUT_CTR_PROC : process(serdes_clk_125) + TIMEOUT_CTR_PROC : process(CLK) begin - if rising_edge(serdes_clk_125) then - if (RESEt = '1' or mac_tx_done = '1') then + if rising_edge(CLK) then + if (RESET = '1' or mac_tx_done = '1') then timeout_ctr <= (others => '0'); else timeout_ctr <= timeout_ctr + x"1"; @@ -1309,12 +1309,12 @@ imp_gen: if (DO_SIMULATION = 0) generate end if; end process TIMEOUT_CTR_PROC; - TIMEOUT_NOTICED_PROC : process(serdes_clk_125) + TIMEOUT_NOTICED_PROC : process(CLK) begin - if rising_edge(serdes_clk_125) then + if rising_edge(CLK) then if (RESET = '1') then timeout_noticed <= '0'; - elsif (timeout_ctr(29) = '1') then + elsif (timeout_ctr(30) = '1') then timeout_noticed <= '1'; end if; end if; diff --git a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd index 4a2185d..79cb01e 100644 --- a/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd +++ b/gbe2_ecp3/trb_net16_gbe_frame_receiver.vhd @@ -107,6 +107,8 @@ signal state : std_logic_vector(3 downto 0); signal parsed_frames_ctr : std_logic_vector(15 downto 0); signal ok_frames_ctr : std_logic_vector(15 downto 0); +signal rx_data : std_logic_vector(8 downto 0); + begin DEBUG_OUT(0) <= rec_fifo_empty; @@ -463,6 +465,7 @@ receive_fifo : fifo_4096x9 port map( Data(7 downto 0) => MAC_RXD_IN, Data(8) => MAC_RX_EOF_IN, +-- Data => rx_data, WrClock => RX_MAC_CLK, RdClock => CLK, WrEn => fifo_wr_en, @@ -480,6 +483,30 @@ fifo_wr_en <= '1' when (MAC_RX_EN_IN = '1') and ((filter_current_state = SAVE_FR ((filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") or (filter_current_state = DECIDE and frame_type_valid = '1'))) else '0'; + +--RX_FIFO_SYNC : process(RX_MAC_CLK) +--begin +-- if rising_edge(RX_MAC_CLK) then +-- +-- rx_data(8) <= MAC_RX_EOF_IN; +-- rx_data(7 downto 0) <= MAC_RXD_IN; +-- +-- if (MAC_RX_EN_IN = '1') then +-- if (filter_current_state = SAVE_FRAME) then +-- fifo_wr_en <= '1'; +-- elsif (filter_current_state = REMOVE_VTYPE and remove_ctr = x"f") then +-- fifo_wr_en <= '1'; +-- elsif (filter_current_state = DECIDE and frame_type_valid = '1') then +-- fifo_wr_en <= '1'; +-- else +-- fifo_wr_en <= '0'; +-- end if; +-- else +-- fifo_wr_en <= '0'; +-- end if; +-- +-- end if; +--end process RX_FIFO_SYNC; MAC_RX_FIFO_FULL_OUT <= rec_fifo_full; diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd index f1add73..7bc222d 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_ARP.vhd @@ -247,9 +247,27 @@ begin end if; end process TC_DATA_SYNC; -PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1'; +--PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1'; +--PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0'; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + + if (dissect_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; + -PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0'; TC_FRAME_SIZE_OUT <= x"001c"; -- fixed frame size @@ -335,25 +353,25 @@ begin end process STATS_MACHINE; -SELECTOR : process(stats_current_state) +SELECTOR : process(CLK) begin - - case(stats_current_state) is - - when LOAD_SENT => - stat_data_temp <= x"0601" & sent_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); + if rising_edge(CLK) then + case(stats_current_state) is - when LOAD_RECEIVED => - stat_data_temp <= x"0602" & rec_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + when LOAD_SENT => + stat_data_temp <= x"0601" & sent_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); + + when LOAD_RECEIVED => + stat_data_temp <= x"0602" & rec_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + + when others => + stat_data_temp <= (others => '0'); + STAT_ADDR_OUT <= (others => '0'); - when others => - stat_data_temp <= (others => '0'); - STAT_ADDR_OUT <= (others => '0'); - - end case; - + end case; + end if; end process SELECTOR; STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); @@ -361,7 +379,17 @@ STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); -STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +STAT_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then + STAT_DATA_RDY_OUT <= '1'; + else + STAT_DATA_RDY_OUT <= '0'; + end if; + end if; +end process STAT_SYNC; +--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; -- **** debug DEBUG_OUT(3 downto 0) <= state; diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd index d22f3b5..aba6ad4 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_DHCP.vhd @@ -628,9 +628,25 @@ end process; --end process TC_DATA_SYNC; -PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1'; +--PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1'; +--PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1'; -PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1'; +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (construct_current_state = IDLE) then + PS_RESPONSE_READY_OUT <= '0'; + else + PS_RESPONSE_READY_OUT <= '1'; + end if; + + if (construct_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; -- fixed sizes for discover and request messages TC_FRAME_SIZE_OUT <= x"0103" when (main_current_state = SENDING_DISCOVER) else x"0109"; @@ -719,28 +735,29 @@ begin end process STATS_MACHINE; -SELECTOR : process(stats_current_state) +SELECTOR : process(CLK) begin - - case(stats_current_state) is - - when LOAD_SENT => - stat_data_temp <= x"0101" & sent_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); - - when LOAD_RECEIVED => - stat_data_temp <= x"0102" & rec_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + if rising_edge(CLK) then + case(stats_current_state) is - when LOAD_DISCARDED => - stat_data_temp <= x"0103" & discarded_ctr; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8)); + when LOAD_SENT => + stat_data_temp <= x"0101" & sent_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); + + when LOAD_RECEIVED => + stat_data_temp <= x"0102" & rec_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + + when LOAD_DISCARDED => + stat_data_temp <= x"0103" & discarded_ctr; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 2, 8)); + + when others => + stat_data_temp <= (others => '0'); + STAT_ADDR_OUT <= (others => '0'); - when others => - stat_data_temp <= (others => '0'); - STAT_ADDR_OUT <= (others => '0'); - - end case; + end case; + end if; end process SELECTOR; @@ -749,7 +766,17 @@ STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); -STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +STAT_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then + STAT_DATA_RDY_OUT <= '1'; + else + STAT_DATA_RDY_OUT <= '0'; + end if; + end if; +end process STAT_SYNC; +--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; -- **** diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd index cc21aed..6e1e527 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_Ping.vhd @@ -286,9 +286,25 @@ begin end process TC_DATA_SYNC; -PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1'; +--PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1'; +--PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0'; -PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) else '0'; +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + + if (dissect_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; TC_FRAME_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16)); TC_IP_SIZE_OUT <= std_logic_vector(to_unsigned(data_length, 16)); @@ -385,25 +401,25 @@ begin end process STATS_MACHINE; -SELECTOR : process(stats_current_state) +SELECTOR : process(CLK) begin - - case(stats_current_state) is - - when LOAD_SENT => - stat_data_temp <= x"0401" & sent_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); + if rising_edge(CLK) then + case(stats_current_state) is - when LOAD_RECEIVED => - stat_data_temp <= x"0402" & rec_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + when LOAD_SENT => + stat_data_temp <= x"0401" & sent_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); + + when LOAD_RECEIVED => + stat_data_temp <= x"0402" & rec_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + + when others => + stat_data_temp <= (others => '0'); + STAT_ADDR_OUT <= (others => '0'); - when others => - stat_data_temp <= (others => '0'); - STAT_ADDR_OUT <= (others => '0'); - - end case; - + end case; + end if; end process SELECTOR; STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); @@ -411,7 +427,17 @@ STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); -STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +STAT_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then + STAT_DATA_RDY_OUT <= '1'; + else + STAT_DATA_RDY_OUT <= '0'; + end if; + end if; +end process STAT_SYNC; +--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; -- **** debug DEBUG_OUT(3 downto 0) <= state; diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd index 164158e..8123848 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_SCTRL.vhd @@ -137,6 +137,8 @@ signal fifo_rd_q : std_logic; signal too_much_data : std_logic; +signal rx_fifo_data : std_logic_vector(8 downto 0); + begin @@ -148,7 +150,7 @@ receive_fifo : fifo_2048x8x16 RPReset => RESET, WrClock => CLK, RdClock => CLK, - Data => PS_DATA_IN, + Data => rx_fifo_data, --PS_DATA_IN, WrEn => rx_fifo_wr, RdEn => rx_fifo_rd, Q => rx_fifo_q, @@ -156,12 +158,35 @@ receive_fifo : fifo_2048x8x16 Empty => rx_empty ); -rx_fifo_wr <= '1' when PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' else '0'; - +--rx_fifo_wr <= '1' when PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1' else '0'; rx_fifo_rd <= '1' when (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) or (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') or (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') else '0'; -- preload first word + +RX_FIFO_SYNC : process(CLK) +begin + if rising_edge(CLK) then + + if (PS_WR_EN_IN = '1' and PS_ACTIVATE_IN = '1') then + rx_fifo_wr <= '1'; + else + rx_fifo_wr <= '0'; + end if; + +-- if (gsc_init_dataready = '1' and dissect_current_state = LOAD_TO_HUB) then +-- rx_fifo_rd <= '1'; +-- elsif (gsc_init_dataready = '1' and dissect_current_state = WAIT_FOR_HUB and GSC_INIT_READ_IN = '1') then +-- rx_fifo_rd <= '1'; +-- elsif (dissect_current_state = READ_FRAME and PS_DATA_IN(8) = '1') then +-- rx_fifo_rd <= '1'; +-- else +-- rx_fifo_rd <= '0'; +-- end if; + + rx_fifo_data <= PS_DATA_IN; + end if; +end process RX_FIFO_SYNC; GSC_INIT_DATA_OUT(7 downto 0) <= rx_fifo_q(16 downto 9); GSC_INIT_DATA_OUT(15 downto 8) <= rx_fifo_q(7 downto 0); @@ -271,12 +296,33 @@ begin end if; end process TX_LOADED_CTR_PROC; -PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1'; - -PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or - dissect_current_state = CLEANUP or dissect_current_state = WAIT_FOR_LOAD_ACK or - dissect_current_state = LOAD_ACK or dissect_current_state = DIVIDE) and (too_much_data = '0') - else '0'; +--PS_BUSY_OUT <= '0' when (dissect_current_state = IDLE) else '1'; +-- +--PS_RESPONSE_READY_OUT <= '1' when (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or +-- dissect_current_state = CLEANUP or dissect_current_state = WAIT_FOR_LOAD_ACK or +-- dissect_current_state = LOAD_ACK or dissect_current_state = DIVIDE) and (too_much_data = '0') +-- else '0'; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (too_much_data = '0') then + if (dissect_current_state = WAIT_FOR_LOAD or dissect_current_state = LOAD_FRAME or dissect_current_state = CLEANUP) then + PS_RESPONSE_READY_OUT <= '1'; + elsif (dissect_current_state = WAIT_FOR_LOAD_ACK or dissect_current_state = LOAD_ACK or dissect_current_state = DIVIDE) then + PS_RESPONSE_READY_OUT <= '1'; + else + PS_RESPONSE_READY_OUT <= '0'; + end if; + end if; + + if (dissect_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; TC_FRAME_TYPE_OUT <= x"0008"; TC_DEST_MAC_OUT <= PS_SRC_MAC_ADDRESS_IN; @@ -601,25 +647,25 @@ begin end process STATS_MACHINE; -SELECTOR : process(stats_current_state) +SELECTOR : process(CLK) begin - - case(stats_current_state) is - - when LOAD_RECEIVED => - stat_data_temp <= x"0502" & rec_frames; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); - - when LOAD_REPLY => - stat_data_temp <= x"0503" & reply_ctr; - STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + if rising_edge(CLK) then + case(stats_current_state) is - when others => - stat_data_temp <= (others => '0'); - STAT_ADDR_OUT <= (others => '0'); - - end case; - + when LOAD_RECEIVED => + stat_data_temp <= x"0502" & rec_frames; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE, 8)); + + when LOAD_REPLY => + stat_data_temp <= x"0503" & reply_ctr; + STAT_ADDR_OUT <= std_logic_vector(to_unsigned(STAT_ADDRESS_BASE + 1, 8)); + + when others => + stat_data_temp <= (others => '0'); + STAT_ADDR_OUT <= (others => '0'); + + end case; + end if; end process SELECTOR; STAT_DATA_OUT(7 downto 0) <= stat_data_temp(31 downto 24); @@ -627,7 +673,17 @@ STAT_DATA_OUT(15 downto 8) <= stat_data_temp(23 downto 16); STAT_DATA_OUT(23 downto 16) <= stat_data_temp(15 downto 8); STAT_DATA_OUT(31 downto 24) <= stat_data_temp(7 downto 0); -STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; +STAT_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (stats_current_state /= IDLE and stats_current_state /= CLEANUP) then + STAT_DATA_RDY_OUT <= '1'; + else + STAT_DATA_RDY_OUT <= '0'; + end if; + end if; +end process STAT_SYNC; +--STAT_DATA_RDY_OUT <= '1' when stats_current_state /= IDLE and stats_current_state /= CLEANUP else '0'; -- end of statistics diff --git a/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd b/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd index 8cab4ae..2ec472e 100644 --- a/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd +++ b/gbe2_ecp3/trb_net16_gbe_response_constructor_Stat.vhd @@ -288,8 +288,25 @@ begin end process TC_DATA_SYNC; -PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1'; -PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1'; +--PS_BUSY_OUT <= '0' when (construct_current_state = IDLE) else '1'; +--PS_RESPONSE_READY_OUT <= '0' when (construct_current_state = IDLE) else '1'; + +PS_RESPONSE_SYNC : process(CLK) +begin + if rising_edge(CLK) then + if (construct_current_state = IDLE) then + PS_RESPONSE_READY_OUT <= '0'; + else + PS_RESPONSE_READY_OUT <= '1'; + end if; + + if (construct_current_state = IDLE) then + PS_BUSY_OUT <= '0'; + else + PS_BUSY_OUT <= '1'; + end if; + end if; +end process PS_RESPONSE_SYNC; TC_FRAME_SIZE_OUT <= x"0100"; TC_FRAME_TYPE_OUT <= x"0008"; -- frame type: ip -- 2.43.0