From 4aef31de0fcbfe24faae0d6a256d54595c74fe1b Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 15 May 2014 17:04:12 +0200 Subject: [PATCH] different FIFOs for different ring buffer sizes --- base/trb3_components.vhd | 69 ++++++++++++++++++++++++++++++++++++++-- 1 file changed, 67 insertions(+), 2 deletions(-) diff --git a/base/trb3_components.vhd b/base/trb3_components.vhd index 994c690..a0a43a4 100644 --- a/base/trb3_components.vhd +++ b/base/trb3_components.vhd @@ -437,10 +437,45 @@ package trb3_components is Reset : in std_logic; Q : out std_logic_vector(35 downto 0); Empty : out std_logic; - Full : out std_logic; - AlmostEmpty : out std_logic); + Full : out std_logic); end component FIFO_36x128_OutReg; + component FIFO_36x64_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component FIFO_36x64_OutReg; + + component FIFO_36x32_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component FIFO_36x32_OutReg; + + component FIFO_36x16_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic); + end component FIFO_36x16_OutReg; + component FIFO_DC_36x128_OutReg is port ( Data : in std_logic_vector(35 downto 0); @@ -471,6 +506,36 @@ package trb3_components is AlmostFull : out std_logic); end component FIFO_DC_36x64_OutReg; + component FIFO_DC_36x32_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component FIFO_DC_36x32_OutReg; + + component FIFO_DC_36x16_OutReg is + port ( + Data : in std_logic_vector(35 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + Q : out std_logic_vector(35 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic); + end component FIFO_DC_36x16_OutReg; + component FIFO_36x128_OutReg_Counter is port ( Data : in std_logic_vector(35 downto 0); -- 2.43.0