From 4b28acbe298b6c987bc459e62499221d58602012 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 29 Apr 2011 15:11:46 +0000 Subject: [PATCH] *** empty log message *** --- special/handler_data.vhd | 6 ++-- special/handler_ipu.vhd | 1 + special/handler_lvl1.vhd | 4 ++- special/trb_net_bridge_pcie_endpoint_hub.vhd | 29 ++++++++++++++------ 4 files changed, 29 insertions(+), 11 deletions(-) diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 1fd105e..0d32452 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -142,7 +142,8 @@ architecture handler_data_arch of handler_data is signal flag_almost_full_combined : std_logic; signal flag_half_full_combined : std_logic; - signal tmg_trg_error_i : std_logic; + signal tmg_trg_error_i : std_logic; + signal partially_missing_i : std_logic; begin @@ -177,7 +178,8 @@ begin end generate; - header_buffer_data_in <= "000000" & tmg_trg_error_i & LVL1_TRG_INFO_IN(0) & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; + header_buffer_data_in <= x"0" & "0" & partially_missing_i & tmg_trg_error_i & LVL1_TRG_INFO_IN(0) + & LVL1_TRG_TYPE_IN & LVL1_TRG_CODE_IN & LVL1_TRG_NUMBER_IN; process(CLOCK) begin diff --git a/special/handler_ipu.vhd b/special/handler_ipu.vhd index 3f833b4..085c579 100644 --- a/special/handler_ipu.vhd +++ b/special/handler_ipu.vhd @@ -153,6 +153,7 @@ begin next_state <= SEND_DHDR; next_suppress_output <= DAT_HDR_DATA_IN(28); next_error_lvl1 <= DAT_HDR_DATA_IN(29); + next_error_missing <= DAT_HDR_DATA_IN(30); end if; -- when GOT_LENGTH => diff --git a/special/handler_lvl1.vhd b/special/handler_lvl1.vhd index 4a9d590..a88747b 100644 --- a/special/handler_lvl1.vhd +++ b/special/handler_lvl1.vhd @@ -150,7 +150,9 @@ THE_SYNC_PROC: process( CLOCK ) begin if( rising_edge(CLOCK) ) then -- timeout_found <= next_timeout_found; -- gk 28.09.10 - if (trg_rel = '1') then + if RESET = '1' then + trg_num_match <= '1'; + elsif (LVL1_TRG_RELEASE_IN = '1') then trg_num_match <= next_trg_num_match; end if; diff --git a/special/trb_net_bridge_pcie_endpoint_hub.vhd b/special/trb_net_bridge_pcie_endpoint_hub.vhd index 8649910..8fc0741 100644 --- a/special/trb_net_bridge_pcie_endpoint_hub.vhd +++ b/special/trb_net_bridge_pcie_endpoint_hub.vhd @@ -212,12 +212,17 @@ architecture trb_net_bridge_pcie_endpoint_hub_arch of trb_net_bridge_pcie_endpoi signal dma_config_i : std_logic_vector(31 downto 0); signal apl_read_dma : std_logic; signal debug_dma_core : std_logic_vector(31 downto 0); - signal status_dma_core : std_logic_vector(127 downto 0); + signal status_dma_core : std_logic_vector(159 downto 0); + signal bus_wdat_last : std_logic_vector(31 downto 0); signal do_reprogram_i : std_logic; signal reprogram_i : std_logic; signal restart_fpga_counter: unsigned(11 downto 0); + + signal wren_addr_fifo : std_logic; + signal wren_length_fifo : std_logic; + begin RESET_i <= RESET; @@ -401,6 +406,7 @@ begin bus_stb_last <= BUS_STB_IN; bus_read_last <= bus_read_i; bus_write_last <= bus_write_i; + bus_wdat_last <= BUS_WDAT_IN; end if; end process; @@ -454,6 +460,8 @@ begin bus_data_i <= status_dma_core(95 downto 64); when x"77" => bus_data_i <= status_dma_core(127 downto 96); + when x"78" => + bus_data_i <= status_dma_core(159 downto 128); when others => bus_data_i <= x"10000000"; --"1000000000000000000" & CTRL(31 downto 19); end case; @@ -468,13 +476,15 @@ begin sender_target <= (others => '0'); sender_error <= (others => '0'); dma_control_i <= (others => '0'); - dma_start_address_i <= (others => '0'); - dma_length_i <= (others => '0'); reg_extended_trigger_information <= (others => '0'); - dma_config_i <= x"0000001f"; + dma_config_i <= x"00000030"; + wren_length_fifo <= '0'; + wren_addr_fifo <= '0'; else dma_control_i <= (others => '0'); do_reprogram_i <= '0'; + wren_length_fifo <= '0'; + wren_addr_fifo <= '0'; if bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"1" and USE_CHANNELS(channel_address) = c_YES then case BUS_ADDR_IN(3 downto 0) is --middle nibble is dont care @@ -493,9 +503,9 @@ begin elsif bus_write_i = '1' and BUS_ADDR_IN(11 downto 8) = x"7" then case BUS_ADDR_IN(3 downto 0) is when x"0" => - dma_start_address_i <= BUS_WDAT_IN; + wren_addr_fifo <= '1'; when x"1" => - dma_length_i <= BUS_WDAT_IN; + wren_length_fifo <= '1'; when x"2" => dma_control_i <= BUS_WDAT_IN; --pulses only! when x"3" => @@ -599,8 +609,10 @@ THE_DMA_CORE : dma_core CLK_IN => CLK, CLK_125_IN => CLK_125_IN, - DMA_START_ADDR_IN => dma_start_address_i, - DMA_LENGTH_IN => dma_length_i, + DMA_DATA_IN => bus_wdat_last, + DMA_LENGTH_WR_IN => wren_length_fifo, + DMA_ADDR_WR_IN => wren_addr_fifo, + DMA_CONTROL_IN => dma_control_i, DMA_STATUS_OUT => dma_status_i, DMA_CONFIG_IN => dma_config_i, @@ -638,6 +650,7 @@ THE_DMA_CORE : dma_core ); + -------------------------------- -- SPI Flash Programming -------------------------------- -- 2.43.0