From 4b38aa3805a3d19cf33c469087a15861be34671e Mon Sep 17 00:00:00 2001 From: Thomas Gessler Date: Tue, 8 Jun 2021 12:06:33 +0200 Subject: [PATCH] trb_net_xdna: Add option for external DNA --- xilinx/xcku/trb_net_xdna.vhd | 44 ++++++++++++++++++++++++------------ 1 file changed, 30 insertions(+), 14 deletions(-) diff --git a/xilinx/xcku/trb_net_xdna.vhd b/xilinx/xcku/trb_net_xdna.vhd index 873840d..d8e3e68 100644 --- a/xilinx/xcku/trb_net_xdna.vhd +++ b/xilinx/xcku/trb_net_xdna.vhd @@ -3,14 +3,19 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity trb_net_xdna is + generic ( + IS_DNA_EXTERNAL : integer range 0 to 1 := 0 + ); port ( - CLK : in std_logic; - RESET : in std_logic; - DATA_OUT : out std_logic_vector(15 downto 0); - ADDR_OUT : out std_logic_vector( 2 downto 0); - WRITE_OUT : out std_logic; - TEMP_OUT : out std_logic_vector(11 downto 0); - ID_OUT : out std_logic_vector(63 downto 0) + CLK : in std_logic; + RESET : in std_logic; + DNA_IN : in std_logic_vector(95 downto 0) := (others => '0'); + DNA_VALID_IN : in std_logic := '0'; + DATA_OUT : out std_logic_vector(15 downto 0); + ADDR_OUT : out std_logic_vector( 2 downto 0); + WRITE_OUT : out std_logic; + TEMP_OUT : out std_logic_vector(11 downto 0); + ID_OUT : out std_logic_vector(63 downto 0) ); end entity trb_net_xdna; @@ -30,13 +35,24 @@ architecture behavioral of trb_net_xdna is signal temp_sysmon_signed : signed(16 downto 0); signal temp_degc_q10_33 : signed(43 downto 0); begin - THE_XDNA : entity work.read_dna_address - port map ( - CLK => CLK, - RESET => RESET, - DNA => dna, - VALID => dna_valid - ); + generate_xdna: + if IS_DNA_EXTERNAL = 0 generate + begin + THE_XDNA : entity work.read_dna_address + port map ( + CLK => CLK, + RESET => RESET, + DNA => dna, + VALID => dna_valid + ); + end generate generate_xdna; + + generate_external_dna: + if IS_DNA_EXTERNAL = 1 generate + begin + dna <= DNA_IN; + dna_valid <= DNA_VALID_IN; + end generate generate_external_dna; THE_SYSMON : entity work.read_sysmon port map ( -- 2.43.0