From 4bff5e439981ae26dcf29206e81f6b604ca907fc Mon Sep 17 00:00:00 2001 From: hadaq Date: Wed, 26 Sep 2012 09:28:19 +0000 Subject: [PATCH] Control Registers are updated - cu --- trb3/TdcSlowControl.tex | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/trb3/TdcSlowControl.tex b/trb3/TdcSlowControl.tex index 3d0e649..a79fff4 100644 --- a/trb3/TdcSlowControl.tex +++ b/trb3/TdcSlowControl.tex @@ -6,9 +6,11 @@ A set of control registers are assigned in order to access the basic controls, e \hline Address & \multicolumn{1}{c|}{Name} & Bits & \multicolumn{1}{c|}{Explanation}\\ \hline \hline - \multirow{11}{*}{0xc0} & \multirow{11}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\ - & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\ - & & 11-5 & reserved.\\ + \multirow{13}{*}{0xc0} & \multirow{13}{*}{Basic controls} & 3-0 & Enables different signals to the HPLA* output for debugging with logic analyser (For more details see Table \ref{tab:tdcControlRegBasicLA}).\\ + & & 4 & Enables the \textit{Debug Mode}. Different statistics and debug words are sent after every trigger (see \ref{sec:tdcDebug}).\\ + & & 7-5 & reserved.\\ + & & 8 & Resets the internal counters.\\ + & & 11-9 & reserved.\\ & & 12 & Used to select the trigger mode. 0 - with trigger mode; 1 - trigger-less mode (For more details see \ref{sec:tdcTrigWin}).\\ & & 31-13 & reserved.\\ \hline -- 2.43.0