From 4cdec521da2c2cbdf57bcf827dc25f9e290b6349 Mon Sep 17 00:00:00 2001 From: Cahit Date: Thu, 24 Apr 2014 23:38:10 +0200 Subject: [PATCH] corrected clock name for timing constraints --- base/trb3_periph_ada.lpf | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/base/trb3_periph_ada.lpf b/base/trb3_periph_ada.lpf index 2006ebd..e02c344 100644 --- a/base/trb3_periph_ada.lpf +++ b/base/trb3_periph_ada.lpf @@ -94,8 +94,8 @@ BLOCK RD_DURING_WR_PATHS ; FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; -MULTICYCLE FROM CLKNET "clk_100_internal_c" TO CLKNET "CLK_PCLK_LEFT" 2 X ; -MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT" TO CLKNET "clk_100_internal_c" 2 X ; +MULTICYCLE FROM CLKNET "clk_100_i_c" TO CLKNET "CLK_PCLK_LEFT_c" 1 X ; +MULTICYCLE FROM CLKNET "CLK_PCLK_LEFT_c" TO CLKNET "clk_100_i_c" 2 X ; LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_1_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; -- 2.43.0