From 4cf07f976223e7cf45b1211996d3885fe6522d0e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 13 Dec 2013 16:43:15 +0100 Subject: [PATCH] slightly changed hardware information register --- trb3/Trb3GeneralRemarks.tex | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex index f4f99b5..e24d3d8 100644 --- a/trb3/Trb3GeneralRemarks.tex +++ b/trb3/Trb3GeneralRemarks.tex @@ -90,11 +90,13 @@ The lower 16 Bit are used to identify the contents of the design and the AddOn b \item[6XXX] use with Nxyter \item[7XXX] use with 32PinAddOn \item[8XXX] uses RX clock as main internal clock - \item[X0nX] contains $2^n$ TDC channels, single edge - \item[X1nX] contains $2^n$ TDC channels, double edge + \item[X0nX] contains $2^n$ TDC channels, single edge, n<8 + \item[X1nX] contains $2^n$ TDC channels, double edge, n<8 \item[X2XX] contains a network hub \item[X4XX] SPI interface on AddOn connector \item[X8XX] Double edge TDC realized with two single edge channels + \item[XX8X] Non-TDC (because of bad choice of encoding) + \item[XX9X] for MVD converter board 2013 \end{description*} \end{description*} -- 2.43.0