From 4d7a86ddca19fa417cf0dd59b588446de5c20ea7 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 14 Jul 2015 14:53:28 +0200 Subject: [PATCH] trb3sc details --- trb3/Trb3scBasics.tex | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/trb3/Trb3scBasics.tex b/trb3/Trb3scBasics.tex index 622a143..e1566ba 100644 --- a/trb3/Trb3scBasics.tex +++ b/trb3/Trb3scBasics.tex @@ -34,7 +34,7 @@ The native frequency of the board are 240 MHz, logic running at 120 MHz. Neverth \end{itemize*} \subsubsection{Other I/O} -JGPIO is available for any general purpose I/O. All lines are LVCMOS25. By default, SPI and UART are available: +HDR\_IO is available for any general purpose I/O. All lines are LVCMOS25. By default, SPI and UART are available: \begin{center} \begin{tabular}{|l|l|} \hline @@ -49,15 +49,16 @@ JGPIO is available for any general purpose I/O. All lines are LVCMOS25. By defau 7 & \\ 8 & \\ 9 & \\ - 10 & 3.3V\\ + 10 & \\ 11 & 3.3V\\ - 12 & GND\\ + 12 & 3.3V\\ 13 & GND\\ + 14 & GND\\ \hline \end{tabular} \end{center} -SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 6 is reserved for JGPIO. +SPI channels 0 to 3 are linked to the AddOn connector (e.g. four Padiwa chains), channels 4 and 5 are used on additional KEL connectors. Channel 8 is reserved for HDR\_IO. \subsubsection{Serial Links} -- 2.43.0