From 4db929694403f98eb7737da8698fe3c6dafc5366 Mon Sep 17 00:00:00 2001 From: Benedikt Gutsche Date: Tue, 16 May 2023 10:44:19 +0200 Subject: [PATCH] added i2c and register for pulsing --- mimosis/code/MimosisInput.vhd | 118 ++++++++++++++++++++-------------- 1 file changed, 69 insertions(+), 49 deletions(-) diff --git a/mimosis/code/MimosisInput.vhd b/mimosis/code/MimosisInput.vhd index f05f45d..63b68b7 100644 --- a/mimosis/code/MimosisInput.vhd +++ b/mimosis/code/MimosisInput.vhd @@ -11,12 +11,12 @@ entity MimosisInput is CLK : in std_logic; CLK_SYS : in std_logic; RESET : in std_logic; - + INPUT : in std_logic_vector(7 downto 0); - + BUSRDO_RX : in READOUT_RX; BUSRDO_TX : out READOUT_TX; - + BUS_RX : in CTRLBUS_RX; BUS_TX : out CTRLBUS_TX ); @@ -26,7 +26,6 @@ end entity; architecture arch of MimosisInput is constant HDR_WORD : std_logic_vector(15 downto 0) := x"FE00"; constant WORD_LIMIT : integer := 8500; - signal input_active_i : std_logic; signal data_i : std_logic_vector(15 downto 0); signal inp_i : std_logic_vector(7 downto 0); @@ -39,9 +38,9 @@ architecture arch of MimosisInput is signal ct_fifo_afull, ct_fifo_full, ct_fifo_empty : std_logic; signal ct_fifo_read, ct_fifo_valid, ct_fifo_nextvalid : std_logic; signal ct_fifo_data_out : std_logic_vector(31 downto 0); - - signal buffer_empty, buffer_full : std_logic; - signal buffer_write, buffer_read : std_logic; + + signal buffer_empty, buffer_full : std_logic; + signal buffer_write, buffer_read : std_logic; signal buffer_valid, buffer_nextvalid : std_logic; signal buffer_din, buffer_dout : std_logic_vector(31 downto 0); signal buffer_fill : std_logic_vector(13 downto 0); @@ -58,10 +57,11 @@ architecture arch of MimosisInput is signal count_fe : unsigned(31 downto 0); signal count_ff : unsigned(31 downto 0); signal count_oof : unsigned(31 downto 0); + signal pulse_stats : std_logic_vector(31 downto 0); signal buffer_blocked : std_logic; type frame_state_t is (IDLE,HDR1,WRITING); signal frame_state : frame_state_t; - + begin @@ -70,11 +70,11 @@ begin CLK => CLK, CLK_SYS => CLK_SYS, RESET => RESET, - + DIN => INPUT, DOUT => data_i, ACTIVE => input_active_i, - + BUS_RX => businp_rx, BUS_TX => businp_tx ); @@ -85,13 +85,13 @@ begin CLK => CLK, CLK_SYS => CLK_SYS, RESET => RESET, - + DIN => data_i, DOUT => word_i, VALID => word_valid, - + ACTIVE => input_active_i, - + BUS_RX => busword_rx, BUS_TX => busword_tx ); @@ -99,7 +99,7 @@ begin ---------------------------------------------------------------------- -- Clock Domain Transfer ----------------------------------------------------------------------- +---------------------------------------------------------------------- THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg port map( Data(31 downto 0) => word_i(31 downto 0), @@ -119,32 +119,32 @@ THE_CT_FIFO : entity work.lattice_ecp5_fifo_36x16_dualport_oreg ct_fifo_read <= '1'; ct_fifo_nextvalid <= ct_fifo_read and not ct_fifo_empty when rising_edge(CLK_SYS); ct_fifo_valid <= ct_fifo_nextvalid when rising_edge(CLK_SYS); - + ---------------------------------------------------------------------- -- Frame Copy ----------------------------------------------------------------------- +---------------------------------------------------------------------- PROC_FRAMES : process begin wait until rising_edge(CLK_SYS); buffer_write <= '0'; buffer_din <= ct_fifo_data_out; - + if ct_fifo_valid = '1' then count_words <= count_words + 1; - end if; - + end if; + if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FE" then count_fe <= count_fe + 1; - end if; + end if; if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then count_ff <= count_ff + 1; - end if; + end if; if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) < x"FC" and frame_state = IDLE then count_oof <= count_oof + 1; - end if; - + end if; + case frame_state is when IDLE => count_words <= (others => '0'); @@ -157,11 +157,24 @@ PROC_FRAMES : process begin end if; when HDR1 => if ct_fifo_valid = '1' then - frame_state <= WRITING; + frame_state <= HDR2; frame_number(31 downto 16) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); buffer_write <= not buffer_blocked; end if; - + when HDR2 => + if ct_fifo_valid = '1' then + frame_state <= HDR3; + buffer_din(23 downto 16) <= pulse_stats(7 downto 0); + buffer_din(7 downto 0) <= pulse_stats(15 downto 8); + buffer_write <= not buffer_blocked; + end if; + when HDR3 => + if ct_fifo_valid = '1' then + frame_state <= WRITING; + buffer_din(23 downto 16) <= pulse_stats(23 downto 16); + buffer_din(7 downto 0) <= pulse_stats(31 downto 24); + buffer_write <= not buffer_blocked; + end if; when WRITING => buffer_write <= ct_fifo_valid and not buffer_blocked; if ct_fifo_valid = '1' and ct_fifo_data_out(31 downto 24) = x"FF" then @@ -175,16 +188,16 @@ PROC_FRAMES : process begin frame_number(15 downto 0) <= ct_fifo_data_out(7 downto 0) & ct_fifo_data_out(23 downto 16); buffer_write <= not buffer_full; buffer_blocked <= buffer_full; - end if; - end case; - + end if; + end case; + end process; - + ---------------------------------------------------------------------- -- Main Fifo ----------------------------------------------------------------------- +---------------------------------------------------------------------- THE_FIFO : entity work.fifo_36x8k_oreg port map( Data(31 downto 0) => buffer_din, @@ -198,14 +211,14 @@ THE_FIFO : entity work.fifo_36x8k_oreg Empty => buffer_empty, Full => open, AlmostFull => buffer_full - ); + ); buffer_nextvalid <= buffer_read and not buffer_empty when rising_edge(CLK_SYS); buffer_valid <= buffer_nextvalid when rising_edge(CLK_SYS); - + --------------------------------------------------------------------------- -- Buffer Handler ---------------------------------------------------------------------------- +--------------------------------------------------------------------------- PROC_RDO : process begin wait until rising_edge(CLK_SYS); -- if state = IDLE and buffer_full = '1' then @@ -213,12 +226,12 @@ PROC_RDO : process begin -- else buffer_read <= '0'; -- end if; - - + + BUSRDO_TX.busy_release <= '0'; BUSRDO_TX.data_write <= '0'; - BUSRDO_TX.data_finished <= '0'; - + BUSRDO_TX.data_finished <= '0'; + case state is when IDLE => if BUSRDO_RX.valid_timing_trg = '1' or BUSRDO_RX.valid_notiming_trg = '1' then @@ -229,19 +242,19 @@ PROC_RDO : process begin if BUSRDO_RX.invalid_trg = '1' then state <= FINISH; end if; - + when START_COPY => state <= START_COPY2; buffer_read <= '1'; word_count <= word_count + 1; - + when START_COPY2 => state <= COPY; buffer_read <= '1'; - word_count <= word_count + 1; - + word_count <= word_count + 1; + when COPY => - + if word_count = WORD_LIMIT or buffer_valid = '0' then state <= FINISH; else @@ -250,16 +263,16 @@ PROC_RDO : process begin BUSRDO_TX.data <= buffer_dout; BUSRDO_TX.data_write <= '1'; end if; - + when FINISH => BUSRDO_TX.data_finished <= '1'; state <= DONE; - + when DONE => BUSRDO_TX.busy_release <= '1'; state <= IDLE; end case; - + end process; --------------------------------------------------------------------------- @@ -291,7 +304,7 @@ end process; STAT_DEBUG => open ); -PROC_REGS : process +PROC_REGS : process variable addr : integer range 0 to 7; begin wait until rising_edge(CLK_SYS); @@ -301,7 +314,12 @@ begin busmimosis_tx.data <= (others => '0'); if busmimosis_rx.write = '1' then - busmimosis_tx.unknown <= '1'; + if busmimosis_rx.addr = x"0009" then + pulse_stats <= busmimosis_rx.data; + busmimosis_tx.ack <= '1'; + else + busmimosis_tx.unknown <= '1'; + end if; elsif busmimosis_rx.read = '1' then busmimosis_tx.ack <= '1'; if busmimosis_rx.addr = x"0000" then @@ -322,12 +340,14 @@ begin busmimosis_tx.data <= std_logic_vector(count_ff); elsif busmimosis_rx.addr = x"0008" then busmimosis_tx.data <= std_logic_vector(count_oof); + elsif busmimosis_rx.addr = x"0009" then + busmimosis_tx.data <= pulse_stats; else busmimosis_tx.ack <= '0'; busmimosis_tx.unknown <= '1'; - + end if; end if; -end process; +end process; end architecture; -- 2.43.0