From 4de8948dd309ac522e14d7dc4c5b2fffe8a66ded Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 18 Apr 2013 14:26:19 +0200 Subject: [PATCH] sync interface Reset fixed --- media_interfaces/med_ecp3_sfp_sync.vhd | 46 ++++++++++++++++---------- media_interfaces/sync/rx_control.vhd | 2 ++ media_interfaces/sync/tx_reset_fsm.vhd | 16 ++++----- 3 files changed, 38 insertions(+), 26 deletions(-) diff --git a/media_interfaces/med_ecp3_sfp_sync.vhd b/media_interfaces/med_ecp3_sfp_sync.vhd index 2145c26..9c4a5c1 100644 --- a/media_interfaces/med_ecp3_sfp_sync.vhd +++ b/media_interfaces/med_ecp3_sfp_sync.vhd @@ -107,12 +107,14 @@ signal rx_k : std_logic; signal rx_error : std_logic; signal rst_n : std_logic; +signal rst : std_logic; signal rx_serdes_rst : std_logic; signal tx_serdes_rst : std_logic; signal tx_pcs_rst : std_logic; signal rx_pcs_rst : std_logic; signal rst_qd : std_logic; signal serdes_rst_qd : std_logic; +signal sd_los_i : std_logic; signal rx_los_low : std_logic; signal lsm_status : std_logic; @@ -176,7 +178,8 @@ CLK_RX_FULL_OUT <= clk_rx_full; SD_TXDIS_OUT <= '0'; --not (rx_allow_q or not IS_SLAVE); --slave only switches on when RX is ready -rst_n <= not CLEAR; +rst_n <= not (CLEAR or sd_los_i or internal_make_link_reset_out); +rst <= (CLEAR or sd_los_i or internal_make_link_reset_out); gen_slave_clock : if IS_SYNC_SLAVE = c_YES generate @@ -241,6 +244,9 @@ THE_SERDES : entity work.serdes_sync_0 ); + tx_serdes_rst <= '0'; --no function + serdes_rst_qd <= '0'; --included in rst_qd + ------------------------------------------------- -- Reset FSM & Link states ------------------------------------------------- @@ -309,7 +315,7 @@ THE_TX : tx_control port map( CLK_200 => clk_200_i, CLK_100 => SYSCLK, - RESET_IN => CLEAR, + RESET_IN => rst, TX_DATA_IN => MED_DATA_IN, TX_PACKET_NUMBER_IN => MED_PACKET_NUM_IN, @@ -344,7 +350,7 @@ THE_RX_CONTROL : rx_control port map( CLK_200 => clk_200_i, CLK_100 => SYSCLK, - RESET_IN => CLEAR, + RESET_IN => rst, RX_DATA_OUT => MED_DATA_OUT, RX_PACKET_NUMBER_OUT => MED_PACKET_NUM_OUT, @@ -462,16 +468,16 @@ end process; -- Generate LED signals ------------------------------------------------- led_ok <= rx_allow and tx_allow when rising_edge(SYSCLK); -led_rx <= (MED_DATAREADY_OUT or led_rx or last_led_rx) and not timer(20) when rising_edge(SYSCLK); -led_tx <= (MED_DATAREADY_IN or led_tx or last_led_tx) and not timer(20) when rising_edge(SYSCLK); -led_dlm <= (led_dlm or rx_dlm_i or last_led_dlm) and not timer(20) when rising_edge(clk_200_i); +led_rx <= (MED_DATAREADY_OUT or led_rx) and not timer(20) when rising_edge(SYSCLK); +led_tx <= (MED_DATAREADY_IN or led_tx or sd_los_i) and not timer(20) when rising_edge(SYSCLK); +led_dlm <= (led_dlm or rx_dlm_i) and not timer(20) when rising_edge(SYSCLK); ROC_TIMER : process begin wait until rising_edge(SYSCLK); timer <= timer + 1 ; if timer(20) = '1' then timer <= (others => '0'); - last_led_rx <= led_rx; + last_led_rx <= led_rx ; last_led_tx <= led_tx; last_led_dlm <= led_dlm; end if; @@ -481,16 +487,19 @@ end process; -- Debug Registers ------------------------------------------------- debug_reg(3 downto 0) <= rx_fsm_state; -debug_reg(4) <= rx_k; -debug_reg(5) <= rx_error; +debug_reg(4) <= CLEAR; +debug_reg(5) <= tx_allow_q; debug_reg(6) <= rx_los_low; debug_reg(7) <= rx_cdr_lol; -debug_reg(8) <= tx_k; +debug_reg(8) <= RESET; debug_reg(9) <= tx_pll_lol; -debug_reg(10) <= lsm_status; -debug_reg(11) <= make_link_reset_i; -debug_reg(15 downto 12) <= tx_fsm_state; +debug_reg(10) <= rx_allow_q; +debug_reg(11) <= CTRL_OP(15); +debug_reg(12) <= make_link_reset_i; +debug_reg(13) <= send_link_reset_i; +debug_reg(14) <= rst_qd; +debug_reg(15) <= rx_pcs_rst; -- debug_reg(31 downto 24) <= tx_data; debug_reg(16) <= '0'; @@ -508,16 +517,17 @@ debug_reg(63 downto 40) <= debug_rx_control_i(23 downto 0); STAT_DEBUG <= debug_reg; internal_make_link_reset_out <= make_link_reset_i when IS_SYNC_SLAVE = 1 else '0'; - +sd_los_i <= SD_LOS_IN when rising_edge(SYSCLK); STAT_OP(15) <= send_link_reset_i when rising_edge(SYSCLK); -STAT_OP(14) <= '0'; +STAT_OP(14) <= '0' when rising_edge(SYSCLK); --sd_los_i STAT_OP(13) <= internal_make_link_reset_out when rising_edge(SYSCLK); --make trbnet reset -STAT_OP(12) <= led_dlm; -STAT_OP(11) <= led_tx; -STAT_OP(10) <= led_rx; +STAT_OP(12) <= led_dlm or last_led_dlm; +STAT_OP(11) <= led_tx or last_led_tx; +STAT_OP(10) <= led_rx or last_led_rx; STAT_OP(9) <= led_ok; STAT_OP(8 downto 4) <= (others => '0'); STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else x"7"; +--STAT_OP(3 downto 0) <= x"0" when rx_allow_q = '1' and tx_allow_q = '1' else ("01" & tx_pll_lol & rx_cdr_lol); end architecture; diff --git a/media_interfaces/sync/rx_control.vhd b/media_interfaces/sync/rx_control.vhd index 4b8740f..30bae72 100644 --- a/media_interfaces/sync/rx_control.vhd +++ b/media_interfaces/sync/rx_control.vhd @@ -220,6 +220,8 @@ PROC_RX_FSM : process begin if RESET_IN = '1' then rx_state <= SLEEP; + make_reset_i <= '0'; + send_link_reset_i <= '0'; end if; end process; diff --git a/media_interfaces/sync/tx_reset_fsm.vhd b/media_interfaces/sync/tx_reset_fsm.vhd index b5dc18d..0d8d22c 100644 --- a/media_interfaces/sync/tx_reset_fsm.vhd +++ b/media_interfaces/sync/tx_reset_fsm.vhd @@ -27,7 +27,7 @@ signal cs: statetype; -- current state of lsm signal ns: statetype; -- next state of lsm signal tx_pll_lol_qd_s_int : std_logic; -signal tx_pcs_rst_ch_c_int : std_logic_vector(3 downto 0); +signal tx_pcs_rst_ch_c_int : std_logic; signal RST_QD_C_int : std_logic; signal reset_timer1: std_logic; @@ -51,7 +51,7 @@ begin else if rising_edge(TX_REFCLK) then cs <= ns; tx_pll_lol_qd_s_int <= tx_pll_lol_qd_s; - tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int(0); + tx_pcs_rst_ch_c <= tx_pcs_rst_ch_c_int; RST_QD_C <= RST_QD_C_int; end if; end if; @@ -61,7 +61,7 @@ end process; -- A 2 bit counter ([1:0]) counts 4 cycles, so a 3 bit ([2:0]) counter will do if we set TIMER1 = bit[2] -process (TX_REFCLK, reset_timer1) +process (TX_REFCLK) begin if rising_edge(TX_REFCLK) then if reset_timer1 = '1' then @@ -115,14 +115,14 @@ begin when QUAD_RESET => STATE_OUT <= x"1"; - tx_pcs_rst_ch_c_int <= "1111"; + tx_pcs_rst_ch_c_int <= '1'; RST_QD_C_int <= '1'; reset_timer1 <= '1'; ns <= WAIT_FOR_TIMER1; when WAIT_FOR_TIMER1 => STATE_OUT <= x"2"; - tx_pcs_rst_ch_c_int <= "1111"; + tx_pcs_rst_ch_c_int <= '1'; RST_QD_C_int <= '1'; if TIMER1 = '1' then ns <= CHECK_PLOL; @@ -132,14 +132,14 @@ begin when CHECK_PLOL => STATE_OUT <= x"3"; - tx_pcs_rst_ch_c_int <= "1111"; + tx_pcs_rst_ch_c_int <= '1'; RST_QD_C_int <= '0'; reset_timer2 <= '1'; ns <= WAIT_FOR_TIMER2; when WAIT_FOR_TIMER2 => STATE_OUT <= x"4"; - tx_pcs_rst_ch_c_int <= "1111"; + tx_pcs_rst_ch_c_int <= '1'; RST_QD_C_int <= '0'; if TIMER2 = '1' then if tx_pll_lol_qd_s_int = '1' then @@ -153,7 +153,7 @@ begin when NORMAL => STATE_OUT <= x"5"; - tx_pcs_rst_ch_c_int <= "0000"; + tx_pcs_rst_ch_c_int <= '0'; RST_QD_C_int <= '0'; if tx_pll_lol_qd_s_int = '1' then ns <= QUAD_RESET; -- 2.43.0