From 4e0ba75c4e9c6a06eb1a129a851f7faede9fee8e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 16 Apr 2014 12:08:23 +0200 Subject: [PATCH] added configuration option for ignoring padiwa slow inputs --- wasa/compile_padiwa_frankfurt.pl | 2 +- wasa/config.vhd | 13 ++++++++----- wasa/trb3_periph_padiwa.vhd | 20 ++++++++++++++++---- 3 files changed, 25 insertions(+), 10 deletions(-) diff --git a/wasa/compile_padiwa_frankfurt.pl b/wasa/compile_padiwa_frankfurt.pl index 7cc1748..a417c27 100755 --- a/wasa/compile_padiwa_frankfurt.pl +++ b/wasa/compile_padiwa_frankfurt.pl @@ -9,7 +9,7 @@ use strict; ################################################################################### #Settings for this project my $TOPNAME = "trb3_periph_padiwa"; #Name of top-level entity -my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; +my $lattice_path = '/d/jspc29/lattice/diamond/2.1_x64'; my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; #my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; diff --git a/wasa/config.vhd b/wasa/config.vhd index aa3e6bb..f678395 100644 --- a/wasa/config.vhd +++ b/wasa/config.vhd @@ -11,9 +11,12 @@ package config is ------------------------------------------------------------------------------ --Include GbE logic - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 65; - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 6; --the nearest power of two, for convenience reasons - constant USE_DOUBLE_EDGE : integer := c_NO; + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 33; + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 5; --the nearest power of two, for convenience reasons + constant USE_DOUBLE_EDGE : integer := c_YES; + +--Use only every second input channel (mask slow channels from padiwa amps) + constant USE_PADIWA_FAST_ONLY : integer := c_YES; --Include SPI on AddOn connector constant INCLUDE_SPI : integer := c_YES; @@ -25,7 +28,8 @@ package config is constant INCLUDE_STATISTICS : integer := c_YES; --number of real inputs to the FPGA - constant PHYSICAL_INPUTS : integer := 64; + constant PHYSICAL_INPUTS : integer := 16; + --Run wih 125 MHz instead of 100 MHz constant USE_125_MHZ : integer := c_NO; --not implemented yet! @@ -33,7 +37,6 @@ package config is --Use sync mode, RX clock for all parts of the FPGA constant USE_RXCLOCK : integer := c_NO; --not implemented yet! - --Address settings constant INIT_ADDRESS : std_logic_vector := x"F306"; constant BROADCAST_SPECIAL_ADDR : std_logic_vector := x"48"; diff --git a/wasa/trb3_periph_padiwa.vhd b/wasa/trb3_periph_padiwa.vhd index 8c0ad8c..28a7fce 100644 --- a/wasa/trb3_periph_padiwa.vhd +++ b/wasa/trb3_periph_padiwa.vhd @@ -291,6 +291,7 @@ architecture trb3_periph_padiwa_arch of trb3_periph_padiwa is --TDC signal hit_in_i : std_logic_vector(64 downto 1); + signal input_i : std_logic_vector(64 downto 1); begin --------------------------------------------------------------------------- @@ -779,13 +780,13 @@ begin gen_TRIGGER_LOGIC : if INCLUDE_TRIGGER_LOGIC = 1 generate THE_TRIG_LOGIC : input_to_trigger_logic generic map( - INPUTS => 32, + INPUTS => PHYSICAL_INPUTS, OUTPUTS => 4 ) port map( CLK => clk_100_i, - INPUT => INP(32 downto 1), + INPUT => input_i(PHYSICAL_INPUTS downto 1), OUTPUT => trig_out, DATA_IN => trig_din, @@ -811,7 +812,7 @@ gen_STATISTICS : if INCLUDE_STATISTICS = 1 generate port map( CLK => clk_100_i, - INPUT => INP(PHYSICAL_INPUTS-1 downto 0), + INPUT => input_i(PHYSICAL_INPUTS downto 1), DATA_IN => stat_din, DATA_OUT => stat_dout, @@ -944,14 +945,25 @@ end generate; -- For single edge measurements gen_single : if USE_DOUBLE_EDGE = 0 generate hit_in_i <= INP; + input_i <= INP; end generate; -- For ToT Measurements - gen_double : if USE_DOUBLE_EDGE = 1 generate + gen_double : if USE_DOUBLE_EDGE = 1 and USE_PADIWA_FAST_ONLY = 0 generate Gen_Hit_In_Signals : for i in 1 to 32 generate hit_in_i(i*2-1) <= INP(i-1); hit_in_i(i*2) <= not INP(i-1); + input_i(i) <= INP(i-1); end generate Gen_Hit_In_Signals; end generate; + gen_double_padiwa_fast : if USE_PADIWA_FAST_ONLY = 1 generate + Gen_Hit_Fast_Signals : for i in 1 to 32 generate + hit_in_i(i*2-1) <= INP(i*2-2); + hit_in_i(i*2) <= not INP(i*2-2); + input_i(i) <= INP(i*2-2); + end generate; + end generate; + + end architecture; -- 2.43.0