From 4e44acac2b848f1a060d9b76aa538a88f755d46e Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Wed, 26 Oct 2022 13:08:12 +0200 Subject: [PATCH] better link handling --- gbe_trb/base/gbe_lsm.vhd | 52 +++++--- gbe_trb/base/gbe_mac_control.vhd | 187 ++++++++++++++++++++++++++++ gbe_trb/base/rx_rb.vhd | 95 +++++++------- gbe_trb/base/sgl_ctrl.vhd | 46 ++++--- gbe_trb/base/tx_fifo.vhd | 20 +-- gbe_trb_ecp3/media/gbe_med_fifo.vhd | 86 ++++--------- 6 files changed, 323 insertions(+), 163 deletions(-) create mode 100644 gbe_trb/base/gbe_mac_control.vhd diff --git a/gbe_trb/base/gbe_lsm.vhd b/gbe_trb/base/gbe_lsm.vhd index 03f9cc4..cd7c4a1 100644 --- a/gbe_trb/base/gbe_lsm.vhd +++ b/gbe_trb/base/gbe_lsm.vhd @@ -11,10 +11,11 @@ entity gbe_lsm is -- SERDES_ACTIVE_IN : in std_logic; -- SerDes Tx / Rx channels operational AN_COMPLETE_IN : in std_logic; -- Link AN completed - MAC_READY_CONF_IN : in std_logic; -- MAC configuration completed + MAC_CONF_DONE_IN : in std_logic; -- MAC configuration completed -- AN_RESTART_OUT : out std_logic; - MAC_RECONF_OUT : out std_logic; + MAC_CONF_START_OUT : out std_logic; + MAC_CONF_STOP_OUT : out std_logic; LINK_ACTIVE_OUT : out std_logic; LINK_START_OUT : out std_logic; LINK_STOP_OUT : out std_logic; @@ -28,7 +29,7 @@ architecture gbe_lsm_arch of gbe_lsm is -- Components -- state machine signals - type state_t is (INACTIVE,AN_WAIT,AN_RESTART,ENABLE_MAC,ACTIVATED); + type state_t is (INACTIVE,AN_WAIT,AN_RESTART,ENABLE_MAC,ACTIVATED,SHUTDOWN); signal STATE, NEXT_STATE : state_t; -- Signals @@ -36,8 +37,10 @@ architecture gbe_lsm_arch of gbe_lsm is signal dly_ctr_done : std_logic; signal dly_ctr_rst_x : std_logic; signal dly_ctr_rst : std_logic; - signal reconf_mac_x : std_logic; - signal reconf_mac : std_logic; + signal start_mac_x : std_logic; + signal start_mac : std_logic; + signal stop_mac_x : std_logic; + signal stop_mac : std_logic; signal restart_an_x : std_logic; signal restart_an : std_logic; signal link_start_x : std_logic; @@ -70,24 +73,27 @@ begin if ( RESET = '1' ) then STATE <= INACTIVE; restart_an <= '0'; - reconf_mac <= '0'; + start_mac <= '0'; + stop_mac <= '0'; dly_ctr_rst <= '1'; link_start <= '0'; link_stop <= '0'; elsif( rising_edge(CLK) ) then STATE <= NEXT_STATE; restart_an <= restart_an_x; - reconf_mac <= reconf_mac_x; + start_mac <= start_mac_x; + stop_mac <= stop_mac_x; dly_ctr_rst <= dly_ctr_rst_x; link_start <= link_start_x; link_stop <= link_stop_x; end if; end process THE_FSM; - THE_STATE_TRANSITIONS: process( STATE, SERDES_ACTIVE_IN, AN_COMPLETE_IN, MAC_READY_CONF_IN, dly_ctr_done ) + THE_STATE_TRANSITIONS: process( STATE, SERDES_ACTIVE_IN, AN_COMPLETE_IN, MAC_CONF_DONE_IN, dly_ctr_done ) begin restart_an_x <= '0'; - reconf_mac_x <= '0'; + start_mac_x <= '0'; + stop_mac_x <= '0'; dly_ctr_rst_x <= '1'; link_start_x <= '0'; link_stop_x <= '0'; @@ -120,7 +126,7 @@ begin if( AN_COMPLETE_IN = '1' ) then -- AN completed NEXT_STATE <= ENABLE_MAC; - reconf_mac_x <= '1'; + start_mac_x <= '1'; elsif( dly_ctr_done = '1' ) then -- no AN within delay NEXT_STATE <= AN_RESTART; @@ -135,33 +141,43 @@ begin -- SerDes broken NEXT_STATE <= INACTIVE; else - if( MAC_READY_CONF_IN = '1' ) then + if( MAC_CONF_DONE_IN = '1' ) then NEXT_STATE <= ACTIVATED; link_start_x <= '1'; else NEXT_STATE <= ENABLE_MAC; - reconf_mac_x <= '1'; + start_mac_x <= '1'; end if; end if; when ACTIVATED => if ( (SERDES_ACTIVE_IN = '0') or (AN_COMPLETE_IN = '0') ) then -- SerDes broken - NEXT_STATE <= INACTIVE; + NEXT_STATE <= SHUTDOWN; link_stop_x <= '1'; + stop_mac_x <= '1'; else NEXT_STATE <= ACTIVATED; end if; + when SHUTDOWN => + if( MAC_CONF_DONE_IN = '1' ) then + NEXT_STATE <= INACTIVE; + else + NEXT_STATE <= SHUTDOWN; + stop_mac_x <= '1'; + end if; + when others => NEXT_STATE <= INACTIVE; end case; end process THE_STATE_TRANSITIONS; - AN_RESTART_OUT <= restart_an; - MAC_RECONF_OUT <= reconf_mac; - LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0'; - LINK_START_OUT <= link_start; - LINK_STOP_OUT <= link_stop; + AN_RESTART_OUT <= restart_an; + MAC_CONF_START_OUT <= start_mac; + MAC_CONF_STOP_OUT <= stop_mac; + LINK_ACTIVE_OUT <= '1' when (STATE = ACTIVATED) else '0'; + LINK_START_OUT <= link_start; + LINK_STOP_OUT <= link_stop; end architecture; diff --git a/gbe_trb/base/gbe_mac_control.vhd b/gbe_trb/base/gbe_mac_control.vhd new file mode 100644 index 0000000..1807aac --- /dev/null +++ b/gbe_trb/base/gbe_mac_control.vhd @@ -0,0 +1,187 @@ +LIBRARY IEEE; +USE IEEE.std_logic_1164.ALL; +USE IEEE.numeric_std.ALL; +USE IEEE.std_logic_UNSIGNED.ALL; + +library work; +--use work.trb_net_std.all; +--use work.trb_net_components.all; +--use work.trb_net16_hub_func.all; + +entity gbe_mac_control is + port ( + CLK : in std_logic; -- system clock + RESET : in std_logic; + -- signals to/from main controller + MC_READY_OUT : out std_logic; + MC_START_IN : in std_logic; + MC_STOP_IN : in std_logic; + -- signal to/from Host interface of TriSpeed MAC + TSM_HADDR_OUT : out std_logic_vector(7 downto 0); + TSM_HDATA_OUT : out std_logic_vector(7 downto 0); + TSM_HCS_N_OUT : out std_logic; + TSM_HWRITE_N_OUT : out std_logic; + TSM_HREAD_N_OUT : out std_logic; + TSM_HREADY_N_IN : in std_logic; + TSM_HDATA_EN_N_IN : in std_logic; + -- Debug + DEBUG_OUT : out std_logic_vector(63 downto 0) + ); +end entity gbe_mac_control; + +architecture gbe_mac_control_arch of gbe_mac_control is + +-- state machine signals + type state_t is (IDLE,WR_DIS,WR_DIS_W,WR_CTLL,WR_CTLL_W,WR_CTLH,WR_CTLH_W,WR_ENA,WR_ENA_W,DONE_W); + signal STATE : state_t; + + signal reg_mode : std_logic_vector(7 downto 0); + signal reg_tx_rx_ctrl : std_logic_vector(15 downto 0); + + signal haddr : std_logic_vector(7 downto 0); + signal hcsn : std_logic; + signal hwriten : std_logic; + signal hdata : std_logic_vector(7 downto 0); + + signal tsm_ready : std_logic; + +begin + + -- MAC main control register + -- address 0x00/0x01 + reg_mode(7 downto 4) <= (others => '0'); + reg_mode(3) <= '1'; -- tx_en + reg_mode(2) <= '1'; -- rx_en + reg_mode(1) <= '0'; -- flow_control en + reg_mode(0) <= '1'; -- gbe en + + -- MAC setup register + -- address 0x02/0x03 + reg_tx_rx_ctrl(15 downto 9) <= (others => '0'); -- reserved + reg_tx_rx_ctrl(8) <= '0'; -- receive short + reg_tx_rx_ctrl(7) <= '1'; -- receive broadcast + reg_tx_rx_ctrl(6) <= '1'; -- drop control + reg_tx_rx_ctrl(5) <= '0'; -- half_duplex en + reg_tx_rx_ctrl(4) <= '1'; -- receive multicast + reg_tx_rx_ctrl(3) <= '0'; -- receive pause + reg_tx_rx_ctrl(2) <= '0'; -- transmit disable FCS + reg_tx_rx_ctrl(1) <= '1'; -- receive discard FCS and padding + reg_tx_rx_ctrl(0) <= '1'; -- promiscuous mode + + ----------------------------------------------------------- + -- statemachine: clocked process + ----------------------------------------------------------- + THE_FSM: process( CLK, RESET ) + begin + if ( RESET = '1' ) then + STATE <= IDLE; + haddr <= x"00"; + hdata <= x"00"; + hcsn <= '1'; + hwriten <= '1'; + tsm_ready <= '0'; + elsif( rising_edge(CLK) ) then + + case STATE is + + when IDLE => + if( (MC_START_IN = '1') or (MC_STOP_IN = '1') ) then + STATE <= WR_DIS; + haddr <= x"00"; + hdata <= x"00"; + hcsn <= '0'; + hwriten <= '0'; + end if; + + when WR_DIS => + if( TSM_HREADY_N_IN = '0' ) then + STATE <= WR_DIS_W; + hcsn <= '1'; + hwriten <= '1'; + end if; + + when WR_DIS_W => + STATE <= WR_CTLL; + haddr <= x"02"; + hdata <= reg_tx_rx_ctrl(7 downto 0); + hcsn <= '0'; + hwriten <= '0'; + + when WR_CTLL => + if( TSM_HREADY_N_IN = '0' ) then + STATE <= WR_CTLL_W; + hcsn <= '1'; + hwriten <= '1'; + end if; + + when WR_CTLL_W => + STATE <= WR_CTLH; + haddr <= x"03"; + hdata <= reg_tx_rx_ctrl(15 downto 8); + hcsn <= '0'; + hwriten <= '0'; + + when WR_CTLH => + if( TSM_HREADY_N_IN = '0' ) then + STATE <= WR_CTLH_W; + hcsn <= '1'; + hwriten <= '1'; + end if; + + when WR_CTLH_W => + if( MC_START_IN = '1' ) then + STATE <= WR_ENA; + haddr <= x"00"; + hdata <= reg_mode; + hcsn <= '0'; + hwriten <= '0'; + else + STATE <= DONE_W; + haddr <= x"00"; + hdata <= x"00"; + hcsn <= '1'; + hwriten <= '1'; + tsm_ready <= '1'; + end if; + + when WR_ENA => + if( TSM_HREADY_N_IN = '0' ) then + STATE <= WR_ENA_W; + haddr <= x"00"; + hdata <= x"00"; + hcsn <= '1'; + hwriten <= '1'; + end if; + + when WR_ENA_W => + STATE <= DONE_W; + tsm_ready <= '1'; + + when DONE_W => + if( (MC_START_IN = '0') and (MC_STOP_IN = '0') ) then + STATE <= IDLE; + tsm_ready <= '0'; + end if; + + when others => + STATE <= IDLE; + haddr <= x"00"; + hdata <= x"00"; + hcsn <= '1'; + hwriten <= '1'; + + end case; + + end if; + end process THE_FSM; + + TSM_HADDR_OUT <= haddr; + TSM_HDATA_OUT <= hdata; + TSM_HCS_N_OUT <= hcsn; + TSM_HWRITE_N_OUT <= hwriten; + TSM_HREAD_N_OUT <= '1'; + MC_READY_OUT <= tsm_ready; + +end gbe_mac_control_arch; + + diff --git a/gbe_trb/base/rx_rb.vhd b/gbe_trb/base/rx_rb.vhd index c6e1b76..0461aae 100644 --- a/gbe_trb/base/rx_rb.vhd +++ b/gbe_trb/base/rx_rb.vhd @@ -87,12 +87,12 @@ begin -- FrameActive: we must not change to "receive" in the middle of a frame -- when "buffer full" condition is deasserted. -- Needs to be extra process, not inside the state machine! - THE_FRAME_ACTIVE_PROC: process( CLK ) + THE_FRAME_ACTIVE_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then + if ( RESET = '1' ) then frame_active <= '0'; - elsif( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then + elsif( rising_edge(CLK) ) then + if ( (MAC_RX_WR_IN = '1') and (frame_active = '0') ) then frame_active <= '1'; elsif( (MAC_RX_EOF_IN = '1') and (frame_active = '1') ) then frame_active <= '0'; @@ -101,24 +101,24 @@ begin end process THE_FRAME_ACTIVE_PROC; -- Read pointer for ring buffer - THE_RD_PTR_PROC: process( CLK ) + THE_RD_PTR_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - rd_ptr <= (others => '0'); - elsif( ce_rd_ptr_x = '1' ) then + if ( RESET = '1' ) then + rd_ptr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( ce_rd_ptr_x = '1' ) then rd_ptr <= rd_ptr + 1; end if; end if; end process THE_RD_PTR_PROC; -- Write pointer for ring buffer - THE_WR_PTR_PROC: process( CLK ) + THE_WR_PTR_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - wr_ptr <= (others => '0'); - elsif( ld_wr_ptr_x = '1' ) then + if ( RESET = '1' ) then + wr_ptr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( ld_wr_ptr_x = '1' ) then wr_ptr <= unsigned(last_wr_ptr); elsif( ce_wr_ptr_x = '1' ) then wr_ptr <= wr_ptr + 1; @@ -127,12 +127,12 @@ begin end process THE_WR_PTR_PROC; -- last write pointer: used to drop a broken frame, in case - THE_LAST_WR_PTR_PROC: process( CLK ) + THE_LAST_WR_PTR_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - last_wr_ptr <= (others => '0'); - elsif( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then + if ( RESET = '1' ) then + last_wr_ptr <= (others => '0'); + elsif( rising_edge(CLK) ) then + if( (STATE = RX_READY) and (MAC_RX_WR_IN = '1') ) then last_wr_ptr <= std_logic_vector(wr_ptr); end if; end if; @@ -176,12 +176,12 @@ begin else '0'; -- FrameError: catches problem with FIFOFULL during a frame write. - THE_FRAME_ERROR_PROC: process( CLK ) + THE_FRAME_ERROR_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - frame_error <= '0'; - elsif( (frame_active = '1') and (rb_full_x = '1') and (MAC_RX_WR_IN = '1') ) then + if ( RESET = '1' ) then + frame_error <= '0'; + elsif( rising_edge(CLK) ) then + if ( (frame_active = '1') and (rb_full_x = '1') and (MAC_RX_WR_IN = '1') ) then frame_error <= '1'; elsif( (frame_active = '0') ) then -- could be better! frame_error <= '0'; @@ -190,12 +190,12 @@ begin end process THE_FRAME_ERROR_PROC; -- FrameReq signal, one pulse only - THE_FRAME_REQ_PROC: process( CLK ) + THE_FRAME_REQ_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - frame_requested <= '0'; - elsif( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then + if ( RESET = '1' ) then + frame_requested <= '0'; + elsif( rising_edge(CLK) ) then + if ( (FRAME_REQ_IN = '1') and (frame_requested = '0') ) then frame_requested <= '1'; elsif( ((ram_q(8) = '1') and (frame_requested = '1')) or (empty_read_ack = '1') ) then frame_requested <= '0'; @@ -210,24 +210,21 @@ begin rd_ram_x <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty_x = '0')) else '0'; ce_rd_ptr_x <= '1' when ((frame_requested = '1') and (ram_q(8) = '0') and (FIFO_FULL_IN = '0') and (rb_empty_x = '0')) else '0'; --- THE_SYNC_PROC: process( CLK ) --- begin - empty_read_ack <= FRAME_REQ_IN and rb_empty_x when rising_edge(CLK); + empty_read_ack <= FRAME_REQ_IN and rb_empty_x when rising_edge(CLK); sof_int <= FRAME_REQ_IN and not frame_requested when rising_edge(CLK); - FRAME_START_OUT <= sof_int when rising_edge(CLK); - fifo_wr_int <= rd_ram_x when rising_edge(CLK); - FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK); - FRAME_ACK_OUT <= normal_read_ack_x or empty_read_ack when rising_edge(CLK); - FIFO_Q_OUT <= ram_q when rising_edge(CLK); --- end process THE_SYNC_PROC; + FRAME_START_OUT <= sof_int when rising_edge(CLK); + fifo_wr_int <= rd_ram_x when rising_edge(CLK); + FIFO_WR_OUT <= fifo_wr_int when rising_edge(CLK); + FRAME_ACK_OUT <= normal_read_ack_x or empty_read_ack when rising_edge(CLK); + FIFO_Q_OUT <= ram_q when rising_edge(CLK); -- FramesAvailable counter - THE_FRAMES_AVAIL_PROC: process( CLK ) + THE_FRAMES_AVAIL_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - frames_avail <= (others => '0'); - elsif( (STATE = FRAME_OK) and (normal_read_ack_x = '0') ) then + if ( RESET = '1' ) then + frames_avail <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( (STATE = FRAME_OK) and (normal_read_ack_x = '0') ) then -- one frame written successfully frames_avail <= frames_avail + 1; elsif( (STATE /= FRAME_OK) and (normal_read_ack_x = '1') ) then @@ -242,14 +239,12 @@ begin ----------------------------------------------------------- -- statemachine: clocked process ----------------------------------------------------------- - THE_FSM: process( CLK ) + THE_FSM: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - STATE <= RX_DENY; - else - STATE <= NEXT_STATE; - end if; + if ( RESET = '1' ) then + STATE <= RX_DENY; + elsif( rising_edge(CLK) ) then + STATE <= NEXT_STATE; end if; end process THE_FSM; diff --git a/gbe_trb/base/sgl_ctrl.vhd b/gbe_trb/base/sgl_ctrl.vhd index e1249fa..06ef0af 100644 --- a/gbe_trb/base/sgl_ctrl.vhd +++ b/gbe_trb/base/sgl_ctrl.vhd @@ -93,12 +93,12 @@ begin -- store the src port status GEN_REGS: for I in 0 to 15 generate - THE_SRC_STORE_PROC: process( CLK ) + THE_SRC_STORE_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - stored_ports(I) <= '0'; - elsif( store_ports_x = '1' ) then + if ( RESET = '1' ) then + stored_ports(I) <= '0'; + elsif( rising_edge(CLK) ) then + if ( store_ports_x = '1' ) then stored_ports(I) <= DL_FRAME_AVAIL_IN(I); elsif( DL_FRAME_ACK_IN(I) = '1' ) then stored_ports(I) <= '0'; @@ -110,16 +110,14 @@ begin all_ports_done_x <= '1' when stored_ports = x"0000" else '0'; -- select the port data - THE_SELECT_PORT_PROC: process( CLK ) + THE_SELECT_PORT_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - select_ports <= (others => '0'); - mux_ports <= (others => '0'); - else - select_ports <= next_port_x; - mux_ports <= next_mux_x; - end if; + if ( RESET = '1' ) then + select_ports <= (others => '0'); + mux_ports <= (others => '0'); + elsif( rising_edge(CLK) ) then + select_ports <= next_port_x; + mux_ports <= next_mux_x; end if; end process THE_SELECT_PORT_PROC; @@ -199,18 +197,16 @@ begin ----------------------------------------------------------- -- statemachine: clocked process ----------------------------------------------------------- - THE_FSM: process( CLK ) + THE_FSM: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if( RESET = '1' ) then - STATE <= IDLE; - ul_frame_req <= '0'; - local_frame_req <= '0'; - else - STATE <= NEXT_STATE; - ul_frame_req <= ul_frame_req_x; - local_frame_req <= local_frame_req_x; - end if; + if ( RESET = '1' ) then + STATE <= IDLE; + ul_frame_req <= '0'; + local_frame_req <= '0'; + elsif( rising_edge(CLK) ) then + STATE <= NEXT_STATE; + ul_frame_req <= ul_frame_req_x; + local_frame_req <= local_frame_req_x; end if; end process THE_FSM; diff --git a/gbe_trb/base/tx_fifo.vhd b/gbe_trb/base/tx_fifo.vhd index 940d72a..3fa7136 100644 --- a/gbe_trb/base/tx_fifo.vhd +++ b/gbe_trb/base/tx_fifo.vhd @@ -70,12 +70,12 @@ architecture tx_fifo_arch of tx_fifo is begin -- FrameActice signal - used to inhibit acceptance of runt frames - THE_FRAME_ACTIVE_PROC: process( CLK ) + THE_FRAME_ACTIVE_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - frame_active <= '0'; - elsif( FRAME_START_IN = '1' ) then + if ( RESET = '1' ) then + frame_active <= '0'; + elsif( rising_edge(CLK) ) then + if ( FRAME_START_IN = '1' ) then frame_active <= LINK_ACTIVE_IN; elsif( frame_written = '1' ) then frame_active <= '0'; @@ -113,12 +113,12 @@ begin frame_read <= '1' when (mac_fifoeof = '1') and (mac_tx_read = '1') else '0'; -- FramesAvailable counter - THE_FRAMES_AVAIL_PROC: process( CLK ) + THE_FRAMES_AVAIL_PROC: process( CLK, RESET ) begin - if( rising_edge(CLK) ) then - if ( RESET = '1' ) then - frames_avail <= (others => '0'); - elsif( (frame_written = '1') and (frame_read = '0') ) then + if ( RESET = '1' ) then + frames_avail <= (others => '0'); + elsif( rising_edge(CLK) ) then + if ( (frame_written = '1') and (frame_read = '0') ) then -- one frame written successfully frames_avail <= frames_avail + 1; elsif( (frame_written = '0') and (frame_read = '1') ) then diff --git a/gbe_trb_ecp3/media/gbe_med_fifo.vhd b/gbe_trb_ecp3/media/gbe_med_fifo.vhd index 6de563b..003ab18 100644 --- a/gbe_trb_ecp3/media/gbe_med_fifo.vhd +++ b/gbe_trb_ecp3/media/gbe_med_fifo.vhd @@ -253,8 +253,9 @@ architecture gbe_med_fifo_arch of gbe_med_fifo is signal mac_rx_eof : std_logic_vector(3 downto 0); signal mac_rx_err : std_logic_vector(3 downto 0); signal mac_rx_fifofull : std_logic_vector(3 downto 0); - signal mac_ready_conf : std_logic_vector(3 downto 0); - signal mac_reconf : std_logic_vector(3 downto 0); + signal mac_conf_done : std_logic_vector(3 downto 0); + signal mac_conf_start : std_logic_vector(3 downto 0); + signal mac_conf_stop : std_logic_vector(3 downto 0); signal link_active : std_logic_vector(3 downto 0); signal led_timer : unsigned(19 downto 0); @@ -548,9 +549,9 @@ begin DEBUG_OUT(i * 32 + 25) <= '0'; -- (25) DEBUG_OUT(i * 32 + 24) <= '0'; -- (24) DEBUG_OUT(i * 32 + 23) <= '0'; -- (23) - DEBUG_OUT(i * 32 + 22) <= '0'; -- (22) - DEBUG_OUT(i * 32 + 21) <= '0'; -- (21) - DEBUG_OUT(i * 32 + 20) <= '0'; -- (20) + DEBUG_OUT(i * 32 + 22) <= tsm_hready_n(i); -- (22) + DEBUG_OUT(i * 32 + 21) <= tsm_hwrite_n(i); -- (21) + DEBUG_OUT(i * 32 + 20) <= tsm_hcs_n(i); -- (20) DEBUG_OUT(i * 32 + 19) <= TX_PCS_RST_IN; -- (19) DEBUG_OUT(i * 32 + 18) <= rx_pcs_rst(i); -- (18) DEBUG_OUT(i * 32 + 17) <= rx_serdes_rst(i); -- (17) @@ -558,11 +559,11 @@ begin DEBUG_OUT(i * 32 + 15) <= lsm_status(i); -- (15) DEBUG_OUT(i * 32 + 14) <= sd_rx_cv_error(i); -- (14) DEBUG_OUT(i * 32 + 13) <= rx_cdr_lol(i); -- (13) - DEBUG_OUT(i * 32 + 12) <= sci_ch_i(0); -- (12) - DEBUG_OUT(i * 32 + 11) <= is_wap_zero(i); -- (11) - DEBUG_OUT(i * 32 + 10) <= sci_read_i; -- (10) - DEBUG_OUT(i * 32 + 9) <= mac_ready_conf(i); -- (9) - DEBUG_OUT(i * 32 + 8) <= mac_reconf(i); -- (8) + DEBUG_OUT(i * 32 + 12) <= is_wap_zero(i); -- (12) + DEBUG_OUT(i * 32 + 11) <= sci_read_i; -- (11) + DEBUG_OUT(i * 32 + 10) <= mac_conf_done(i); -- (10) + DEBUG_OUT(i * 32 + 9) <= mac_conf_stop(i); -- (9) + DEBUG_OUT(i * 32 + 8) <= mac_conf_start(i); -- (8) DEBUG_OUT(i * 32 + 7) <= an_restart_i(i); -- (7) DEBUG_OUT(i * 32 + 6) <= an_link_ok_i(i); -- (6) DEBUG_OUT(i * 32 + 5) <= mr_page_rx_i(i); --(5) @@ -721,7 +722,7 @@ begin txmac_clk => MASTER_CLK_IN, rxmac_clk => MASTER_CLK_IN, reset_n => CLEAR_N, --RESET_N, -- CHECKIFWORKS - ------------------- Input signals to the GMII ---------------- + ------------------- Input signals to the Gdhcp_startMII ---------------- rxd => pcs_rxd(i * 8 + 7 downto i * 8), rx_dv => pcs_rx_en(i), rx_er => pcs_rx_er(i), @@ -768,19 +769,15 @@ begin ); -- responsible for loading the TSMAC registers - -- CAN BE OPTIMIZED - TSMAC_CONTROLLER : trb_net16_gbe_mac_control + THE_GBE_MAC_CONTROL: entity gbe_mac_control port map( CLK => MASTER_CLK_IN, - RESET => CLEAR, --RESET, -- CHECKIFWORKS - -- signals to/from main controller - MC_TSMAC_READY_OUT => mac_ready_conf(i), - MC_RECONF_IN => mac_reconf(i), - MC_GBE_EN_IN => '1', --- MC_RX_DISCARD_FCS => '0', - MC_PROMISC_IN => '1', --- MC_MAC_ADDR_IN => (others => '0'), - -- signal to/from Host interface of TriSpeed MAC + RESET => CLEAR, --RESET, -- CHECKIFWORKS + -- signals to/from main controller + MC_READY_OUT => mac_conf_done(i), + MC_START_IN => mac_conf_start(i), + MC_STOP_IN => mac_conf_stop(i), + -- signal to/from Host interface of TriSpeed MAC TSM_HADDR_OUT => tsm_haddr(i * 8 + 7 downto i * 8), TSM_HDATA_OUT => tsm_hdata(i * 8 + 7 downto i * 8), TSM_HCS_N_OUT => tsm_hcs_n(i), @@ -788,10 +785,10 @@ begin TSM_HREAD_N_OUT => tsm_hread_n(i), TSM_HREADY_N_IN => tsm_hready_n(i), TSM_HDATA_EN_N_IN => tsm_hdataout_en_n(i), - -- Debug + -- Debug DEBUG_OUT => open ); - + -- initializes MAC after AN is complete THE_FW_GBE_LSM: entity gbe_lsm port map( @@ -799,9 +796,10 @@ begin RESET => CLEAR, --RESET, -- CHECKIFWORKS SERDES_ACTIVE_IN => serdes_active(i), AN_COMPLETE_IN => an_link_ok_i(i), - MAC_READY_CONF_IN => mac_ready_conf(i), + MAC_CONF_DONE_IN => mac_conf_done(i), AN_RESTART_OUT => an_restart_i(i), - MAC_RECONF_OUT => mac_reconf(i), + MAC_CONF_START_OUT => mac_conf_start(i), + MAC_CONF_STOP_OUT => mac_conf_stop(i), LINK_ACTIVE_OUT => link_active(i), DEBUG => open ); @@ -848,7 +846,9 @@ begin LINK_ACTIVE_IN => link_active(i) ); + -- TO BE REMOVED. NOT NEEDED ANYMORE. PCS_AN_READY_OUT(i) <= an_link_ok_i(i); -- needed for internal SCTRL + LINK_ACTIVE_OUT(i) <= link_active(i); -- LED connections, can be simplified by CE signal, to get rid of local counter instances @@ -924,37 +924,3 @@ begin led_timer_done_x <= '1' when (std_logic_vector(led_timer) = x"fffff") else '0'; end architecture gbe_med_fifo_arch; - --- -- Debug signals, MSB to LSB --- DEBUG_OUT((i + 1) * 32 - 1) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 2) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 3) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 4) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 5) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 6) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 7) <= '0'; --- DEBUG_OUT((i + 1) * 32 - 8) <= an_link_ok_i(i); --- DEBUG_OUT((i + 1) * 32 - 9) <= is_wap_zero(i); --- DEBUG_OUT((i + 1) * 32 - 10) <= sci_read_i; --- DEBUG_OUT((i + 1) * 32 - 11) <= tx_clk_avail_i; --- DEBUG_OUT((i + 1) * 32 - 12) <= link_active(i); --- DEBUG_OUT((i + 1) * 32 - 13) <= an_complete(i); --- DEBUG_OUT((i + 1) * 32 - 14) <= cfg_rx_int(i); --- DEBUG_OUT((i + 1) * 32 - 15) <= idle_rx_int(i); --- DEBUG_OUT((i + 1) * 32 - 16) <= unknown_rx_int(i); --- DEBUG_OUT((i + 1) * 32 - 17) <= cfg_tx_int(i); --- DEBUG_OUT((i + 1) * 32 - 18) <= idle_tx_int(i); --- DEBUG_OUT((i + 1) * 32 - 19) <= unknown_tx_int(i); --- DEBUG_OUT((i + 1) * 32 - 20) <= TX_LINK_READY_IN; --- DEBUG_OUT((i + 1) * 32 - 21) <= link_rx_ready(i); --- DEBUG_OUT((i + 1) * 32 - 22) <= rx_serdes_rst(i); --- DEBUG_OUT((i + 1) * 32 - 23) <= rx_pcs_rst(i); --- DEBUG_OUT((i + 1) * 32 - 24) <= sd_rx_disp_error(i); --- DEBUG_OUT((i + 1) * 32 - 25) <= sd_rx_cv_error(i); --- DEBUG_OUT((i + 1) * 32 - 26) <= lsm_status(i); --- DEBUG_OUT((i + 1) * 32 - 27) <= rx_los_low(i); --- DEBUG_OUT((i + 1) * 32 - 28) <= rx_cdr_lol(i); --- DEBUG_OUT((i + 1) * 32 - 29) <= TX_PCS_RST_IN; --- DEBUG_OUT((i + 1) * 32 - 30) <= tx_plol_lol; --- DEBUG_OUT((i + 1) * 32 - 31) <= RESET; --- DEBUG_OUT((i + 1) * 32 - 32) <= CLEAR; -- 2.43.0