From 4eb3112061033ad18110e88e0c37da4914f0a9fc Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Tue, 9 Apr 2013 14:43:05 +0200 Subject: [PATCH] no more fifo9to36 stuff in nx_timestamp_fifo_read, updates... --- base/trb3_periph_nxyter.lpf | 16 +- nxyter/.cvsignore | 12 - nxyter/cores/fifo_32to32_dc.ipx | 9 + ...fo_dc_8to32_dyn.lpc => fifo_32to32_dc.lpc} | 12 +- ...fo_dc_8to32_dyn.vhd => fifo_32to32_dc.vhd} | 757 +++++++++--------- nxyter/cores/fifo_dc_8to32_dyn.ipx | 9 - nxyter/cores/nxyter_input_pll.ipx | 8 - nxyter/cores/nxyter_input_pll.lpc | 66 -- nxyter/cores/nxyter_input_pll.vhd | 98 --- nxyter/source/nx_timestamp_decode.vhd | 14 +- nxyter/source/nx_timestamp_fifo_read.vhd | 690 ++++++++-------- nxyter/source/nxyter.vhd | 68 +- nxyter/source/nxyter_components.vhd | 54 +- nxyter/source/registers.txt | 17 +- nxyter/trb3_periph.prj | 9 +- nxyter/trb3_periph.vhd | 69 +- nxyter/trb3_periph_constraints.lpf | 22 +- nxyter/version.vhd | 2 +- 18 files changed, 948 insertions(+), 984 deletions(-) delete mode 100644 nxyter/.cvsignore create mode 100644 nxyter/cores/fifo_32to32_dc.ipx rename nxyter/cores/{fifo_dc_8to32_dyn.lpc => fifo_32to32_dc.lpc} (87%) rename nxyter/cores/{fifo_dc_8to32_dyn.vhd => fifo_32to32_dc.vhd} (68%) delete mode 100644 nxyter/cores/fifo_dc_8to32_dyn.ipx delete mode 100644 nxyter/cores/nxyter_input_pll.ipx delete mode 100644 nxyter/cores/nxyter_input_pll.lpc delete mode 100644 nxyter/cores/nxyter_input_pll.vhd diff --git a/base/trb3_periph_nxyter.lpf b/base/trb3_periph_nxyter.lpf index 955f425..c02b52e 100644 --- a/base/trb3_periph_nxyter.lpf +++ b/base/trb3_periph_nxyter.lpf @@ -6,12 +6,12 @@ BLOCK RD_DURING_WR_PATHS ; # Basic Settings ################################################################# -# SYSCONFIG MCCLK_FREQ = 2.5; -# -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + #SYSCONFIG MCCLK_FREQ = 2.5; + + #FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; + #FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; + #FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + #FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; ################################################################# # Clock I/O @@ -97,8 +97,8 @@ IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; LOCATE COMP "NX1_TESTPULSE_OUT" SITE "T7"; #DQLL1_8 #46 LOCATE COMP "NX1_CLK256A_OUT" SITE "AB1"; #DQLL2_2 #29 LOCATE COMP "NX1_RESET_OUT" SITE "V6"; #DQLL2_8 #45 -LOCATE COMP "NX1_CLK128_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 -#LOCATE COMP "NX1_CLK128_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE +#LOCATE COMP "NX1_CLK128_IN" SITE "M3"; #DQUL3_8_OUTOFLANE_FPGA__3 #69 +LOCATE COMP "NX1_CLK128_IN" SITE "K4"; #DQSUL2_T #62 see DQUL3_8_OUTOFLANE LOCATE COMP "NX1_I2C_SM_RESET_OUT" SITE "P4"; #DQLL1_4 #34 LOCATE COMP "NX1_I2C_REG_RESET_OUT" SITE "R3"; #DQLL1_5 #36 diff --git a/nxyter/.cvsignore b/nxyter/.cvsignore deleted file mode 100644 index a459553..0000000 --- a/nxyter/.cvsignore +++ /dev/null @@ -1,12 +0,0 @@ -*.log -*.rpt -netlists -version.vhd -*.jhd -*.naf -*.sort -*.srp -*.sym -*tmpl.vhd -*.log - diff --git a/nxyter/cores/fifo_32to32_dc.ipx b/nxyter/cores/fifo_32to32_dc.ipx new file mode 100644 index 0000000..ad3a7ac --- /dev/null +++ b/nxyter/cores/fifo_32to32_dc.ipx @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/nxyter/cores/fifo_dc_8to32_dyn.lpc b/nxyter/cores/fifo_32to32_dc.lpc similarity index 87% rename from nxyter/cores/fifo_dc_8to32_dyn.lpc rename to nxyter/cores/fifo_32to32_dc.lpc index bf10176..ad53e9e 100644 --- a/nxyter/cores/fifo_dc_8to32_dyn.lpc +++ b/nxyter/cores/fifo_32to32_dc.lpc @@ -13,11 +13,11 @@ CoreType=LPM CoreStatus=Demo CoreName=FIFO_DC CoreRevision=5.4 -ModuleName=fifo_dc_8to32_dyn +ModuleName=fifo_32to32_dc SourceFormat=VHDL ParameterFileVersion=1.0 -Date=03/30/2013 -Time=18:53:35 +Date=04/07/2013 +Time=20:23:08 [Parameters] Verilog=0 @@ -28,12 +28,12 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Based -Depth=256 -Width=8 +Depth=64 +Width=32 RDepth=64 RWidth=32 regout=1 -CtrlByRdEn=0 +CtrlByRdEn=1 EmpFlg=1 PeMode=Dynamic - Single Threshold PeAssert=10 diff --git a/nxyter/cores/fifo_dc_8to32_dyn.vhd b/nxyter/cores/fifo_32to32_dc.vhd similarity index 68% rename from nxyter/cores/fifo_dc_8to32_dyn.vhd rename to nxyter/cores/fifo_32to32_dc.vhd index 0ace693..a52318a 100644 --- a/nxyter/cores/fifo_dc_8to32_dyn.vhd +++ b/nxyter/cores/fifo_32to32_dc.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) -- Module Version: 5.4 ---/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 256 -width 8 -depth 256 -rdata_width 32 -regout -no_enable -pe 0 -pf -1 -e +--/usr/local/opt/lattice_diamond/diamond/2.0/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 64 -width 32 -depth 64 -rdata_width 32 -regout -pe 0 -pf -1 -e --- Sat Mar 30 18:53:35 2013 +-- Sun Apr 7 20:23:08 2013 library IEEE; use IEEE.std_logic_1164.all; @@ -11,9 +11,9 @@ library ecp3; use ecp3.components.all; -- synopsys translate_on -entity fifo_dc_8to32_dyn is +entity fifo_32to32_dc is port ( - Data: in std_logic_vector(7 downto 0); + Data: in std_logic_vector(31 downto 0); WrClock: in std_logic; RdClock: in std_logic; WrEn: in std_logic; @@ -25,16 +25,13 @@ entity fifo_dc_8to32_dyn is Empty: out std_logic; Full: out std_logic; AlmostEmpty: out std_logic); -end fifo_dc_8to32_dyn; +end fifo_32to32_dc; -architecture Structure of fifo_dc_8to32_dyn is +architecture Structure of fifo_32to32_dc is -- internal signal declarations signal invout_1: std_logic; signal invout_0: std_logic; - signal wcount_r1: std_logic; - signal wcount_r0: std_logic; - signal w_g2b_xor_cluster_1: std_logic; signal rcnt_reg_5_inv: std_logic; signal w_gdata_0: std_logic; signal w_gdata_1: std_logic; @@ -42,8 +39,6 @@ architecture Structure of fifo_dc_8to32_dyn is signal w_gdata_3: std_logic; signal w_gdata_4: std_logic; signal w_gdata_5: std_logic; - signal w_gdata_6: std_logic; - signal w_gdata_7: std_logic; signal wptr_0: std_logic; signal wptr_1: std_logic; signal wptr_2: std_logic; @@ -51,8 +46,6 @@ architecture Structure of fifo_dc_8to32_dyn is signal wptr_4: std_logic; signal wptr_5: std_logic; signal wptr_6: std_logic; - signal wptr_7: std_logic; - signal wptr_8: std_logic; signal r_gdata_0: std_logic; signal r_gdata_1: std_logic; signal r_gdata_2: std_logic; @@ -66,6 +59,38 @@ architecture Structure of fifo_dc_8to32_dyn is signal rptr_4: std_logic; signal rptr_5: std_logic; signal rptr_6: std_logic; + signal ffidata_0: std_logic; + signal ffidata_1: std_logic; + signal ffidata_2: std_logic; + signal ffidata_3: std_logic; + signal ffidata_4: std_logic; + signal ffidata_5: std_logic; + signal ffidata_6: std_logic; + signal ffidata_7: std_logic; + signal ffidata_8: std_logic; + signal ffidata_9: std_logic; + signal ffidata_10: std_logic; + signal ffidata_11: std_logic; + signal ffidata_12: std_logic; + signal ffidata_13: std_logic; + signal ffidata_14: std_logic; + signal ffidata_15: std_logic; + signal ffidata_16: std_logic; + signal ffidata_17: std_logic; + signal ffidata_18: std_logic; + signal ffidata_19: std_logic; + signal ffidata_20: std_logic; + signal ffidata_21: std_logic; + signal ffidata_22: std_logic; + signal ffidata_23: std_logic; + signal ffidata_24: std_logic; + signal ffidata_25: std_logic; + signal ffidata_26: std_logic; + signal ffidata_27: std_logic; + signal ffidata_28: std_logic; + signal ffidata_29: std_logic; + signal ffidata_30: std_logic; + signal ffidata_31: std_logic; signal w_gcount_0: std_logic; signal w_gcount_1: std_logic; signal w_gcount_2: std_logic; @@ -73,8 +98,6 @@ architecture Structure of fifo_dc_8to32_dyn is signal w_gcount_4: std_logic; signal w_gcount_5: std_logic; signal w_gcount_6: std_logic; - signal w_gcount_7: std_logic; - signal w_gcount_8: std_logic; signal r_gcount_0: std_logic; signal r_gcount_1: std_logic; signal r_gcount_2: std_logic; @@ -96,10 +119,6 @@ architecture Structure of fifo_dc_8to32_dyn is signal w_gcount_r5: std_logic; signal w_gcount_r26: std_logic; signal w_gcount_r6: std_logic; - signal w_gcount_r27: std_logic; - signal w_gcount_r7: std_logic; - signal w_gcount_r28: std_logic; - signal w_gcount_r8: std_logic; signal r_gcount_w20: std_logic; signal r_gcount_w0: std_logic; signal r_gcount_w21: std_logic; @@ -128,12 +147,9 @@ architecture Structure of fifo_dc_8to32_dyn is signal iwcount_5: std_logic; signal co1: std_logic; signal iwcount_6: std_logic; - signal iwcount_7: std_logic; - signal co2: std_logic; - signal iwcount_8: std_logic; - signal co4: std_logic; - signal wcount_8: std_logic; signal co3: std_logic; + signal wcount_6: std_logic; + signal co2: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal r_gctr_ci: std_logic; @@ -162,18 +178,18 @@ architecture Structure of fifo_dc_8to32_dyn is signal co3_2d: std_logic; signal co3_2: std_logic; signal cmp_ci: std_logic; - signal wcount_r2: std_logic; - signal wcount_r3: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; signal rcount_0: std_logic; signal rcount_1: std_logic; signal co0_3: std_logic; - signal wcount_r4: std_logic; + signal wcount_r2: std_logic; signal w_g2b_xor_cluster_0: std_logic; signal rcount_2: std_logic; signal rcount_3: std_logic; signal co1_3: std_logic; - signal wcount_r6: std_logic; - signal wcount_r7: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; signal rcount_4: std_logic; signal rcount_5: std_logic; signal co2_3: std_logic; @@ -183,24 +199,21 @@ architecture Structure of fifo_dc_8to32_dyn is signal empty_d_c: std_logic; signal wren_i: std_logic; signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; signal wcount_0: std_logic; signal wcount_1: std_logic; signal co0_4: std_logic; - signal rcount_w0: std_logic; - signal rcount_w1: std_logic; + signal rcount_w2: std_logic; + signal r_g2b_xor_cluster_0: std_logic; signal wcount_2: std_logic; signal wcount_3: std_logic; signal co1_4: std_logic; - signal rcount_w2: std_logic; - signal r_g2b_xor_cluster_0: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; signal wcount_4: std_logic; signal wcount_5: std_logic; signal co2_4: std_logic; - signal rcount_w4: std_logic; - signal rcount_w5: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; - signal co3_3: std_logic; signal full_cmp_clr: std_logic; signal full_cmp_set: std_logic; signal full_d: std_logic; @@ -280,79 +293,91 @@ architecture Structure of fifo_dc_8to32_dyn is component XOR2 port (A: in std_logic; B: in std_logic; Z: out std_logic); end component; - component DP16KC - generic (GSR : in String; WRITEMODE_B : in String; - WRITEMODE_A : in String; CSDECODE_B : in String; - CSDECODE_A : in String; REGMODE_B : in String; - REGMODE_A : in String; DATA_WIDTH_B : in Integer; - DATA_WIDTH_A : in Integer); - port (DIA0: in std_logic; DIA1: in std_logic; - DIA2: in std_logic; DIA3: in std_logic; - DIA4: in std_logic; DIA5: in std_logic; - DIA6: in std_logic; DIA7: in std_logic; - DIA8: in std_logic; DIA9: in std_logic; - DIA10: in std_logic; DIA11: in std_logic; - DIA12: in std_logic; DIA13: in std_logic; - DIA14: in std_logic; DIA15: in std_logic; - DIA16: in std_logic; DIA17: in std_logic; - ADA0: in std_logic; ADA1: in std_logic; - ADA2: in std_logic; ADA3: in std_logic; - ADA4: in std_logic; ADA5: in std_logic; - ADA6: in std_logic; ADA7: in std_logic; - ADA8: in std_logic; ADA9: in std_logic; - ADA10: in std_logic; ADA11: in std_logic; - ADA12: in std_logic; ADA13: in std_logic; - CEA: in std_logic; CLKA: in std_logic; OCEA: in std_logic; - WEA: in std_logic; CSA0: in std_logic; CSA1: in std_logic; - CSA2: in std_logic; RSTA: in std_logic; - DIB0: in std_logic; DIB1: in std_logic; - DIB2: in std_logic; DIB3: in std_logic; - DIB4: in std_logic; DIB5: in std_logic; - DIB6: in std_logic; DIB7: in std_logic; - DIB8: in std_logic; DIB9: in std_logic; - DIB10: in std_logic; DIB11: in std_logic; - DIB12: in std_logic; DIB13: in std_logic; - DIB14: in std_logic; DIB15: in std_logic; - DIB16: in std_logic; DIB17: in std_logic; - ADB0: in std_logic; ADB1: in std_logic; - ADB2: in std_logic; ADB3: in std_logic; - ADB4: in std_logic; ADB5: in std_logic; - ADB6: in std_logic; ADB7: in std_logic; - ADB8: in std_logic; ADB9: in std_logic; - ADB10: in std_logic; ADB11: in std_logic; - ADB12: in std_logic; ADB13: in std_logic; - CEB: in std_logic; CLKB: in std_logic; OCEB: in std_logic; - WEB: in std_logic; CSB0: in std_logic; CSB1: in std_logic; - CSB2: in std_logic; RSTB: in std_logic; - DOA0: out std_logic; DOA1: out std_logic; - DOA2: out std_logic; DOA3: out std_logic; - DOA4: out std_logic; DOA5: out std_logic; - DOA6: out std_logic; DOA7: out std_logic; - DOA8: out std_logic; DOA9: out std_logic; - DOA10: out std_logic; DOA11: out std_logic; - DOA12: out std_logic; DOA13: out std_logic; - DOA14: out std_logic; DOA15: out std_logic; - DOA16: out std_logic; DOA17: out std_logic; - DOB0: out std_logic; DOB1: out std_logic; - DOB2: out std_logic; DOB3: out std_logic; - DOB4: out std_logic; DOB5: out std_logic; - DOB6: out std_logic; DOB7: out std_logic; - DOB8: out std_logic; DOB9: out std_logic; - DOB10: out std_logic; DOB11: out std_logic; - DOB12: out std_logic; DOB13: out std_logic; - DOB14: out std_logic; DOB15: out std_logic; - DOB16: out std_logic; DOB17: out std_logic); + component PDPW16KC + generic (GSR : in String; CSDECODE_R : in String; + CSDECODE_W : in String; REGMODE : in String; + DATA_WIDTH_R : in Integer; DATA_WIDTH_W : in Integer); + port (DI0: in std_logic; DI1: in std_logic; DI2: in std_logic; + DI3: in std_logic; DI4: in std_logic; DI5: in std_logic; + DI6: in std_logic; DI7: in std_logic; DI8: in std_logic; + DI9: in std_logic; DI10: in std_logic; DI11: in std_logic; + DI12: in std_logic; DI13: in std_logic; + DI14: in std_logic; DI15: in std_logic; + DI16: in std_logic; DI17: in std_logic; + DI18: in std_logic; DI19: in std_logic; + DI20: in std_logic; DI21: in std_logic; + DI22: in std_logic; DI23: in std_logic; + DI24: in std_logic; DI25: in std_logic; + DI26: in std_logic; DI27: in std_logic; + DI28: in std_logic; DI29: in std_logic; + DI30: in std_logic; DI31: in std_logic; + DI32: in std_logic; DI33: in std_logic; + DI34: in std_logic; DI35: in std_logic; + ADW0: in std_logic; ADW1: in std_logic; + ADW2: in std_logic; ADW3: in std_logic; + ADW4: in std_logic; ADW5: in std_logic; + ADW6: in std_logic; ADW7: in std_logic; + ADW8: in std_logic; BE0: in std_logic; BE1: in std_logic; + BE2: in std_logic; BE3: in std_logic; CEW: in std_logic; + CLKW: in std_logic; CSW0: in std_logic; + CSW1: in std_logic; CSW2: in std_logic; + ADR0: in std_logic; ADR1: in std_logic; + ADR2: in std_logic; ADR3: in std_logic; + ADR4: in std_logic; ADR5: in std_logic; + ADR6: in std_logic; ADR7: in std_logic; + ADR8: in std_logic; ADR9: in std_logic; + ADR10: in std_logic; ADR11: in std_logic; + ADR12: in std_logic; ADR13: in std_logic; + CER: in std_logic; CLKR: in std_logic; CSR0: in std_logic; + CSR1: in std_logic; CSR2: in std_logic; RST: in std_logic; + DO0: out std_logic; DO1: out std_logic; + DO2: out std_logic; DO3: out std_logic; + DO4: out std_logic; DO5: out std_logic; + DO6: out std_logic; DO7: out std_logic; + DO8: out std_logic; DO9: out std_logic; + DO10: out std_logic; DO11: out std_logic; + DO12: out std_logic; DO13: out std_logic; + DO14: out std_logic; DO15: out std_logic; + DO16: out std_logic; DO17: out std_logic; + DO18: out std_logic; DO19: out std_logic; + DO20: out std_logic; DO21: out std_logic; + DO22: out std_logic; DO23: out std_logic; + DO24: out std_logic; DO25: out std_logic; + DO26: out std_logic; DO27: out std_logic; + DO28: out std_logic; DO29: out std_logic; + DO30: out std_logic; DO31: out std_logic; + DO32: out std_logic; DO33: out std_logic; + DO34: out std_logic; DO35: out std_logic); end component; attribute MEM_LPC_FILE : string; attribute MEM_INIT_FILE : string; attribute RESETMODE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_dc_8to32_dyn.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_dc_8to32_dyn.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_32to32_dc.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute RESETMODE of pdp_ram_0_0_0 : label is "SYNC"; + attribute GSR of FF_111 : label is "ENABLED"; + attribute GSR of FF_110 : label is "ENABLED"; + attribute GSR of FF_109 : label is "ENABLED"; + attribute GSR of FF_108 : label is "ENABLED"; + attribute GSR of FF_107 : label is "ENABLED"; + attribute GSR of FF_106 : label is "ENABLED"; + attribute GSR of FF_105 : label is "ENABLED"; + attribute GSR of FF_104 : label is "ENABLED"; + attribute GSR of FF_103 : label is "ENABLED"; + attribute GSR of FF_102 : label is "ENABLED"; + attribute GSR of FF_101 : label is "ENABLED"; + attribute GSR of FF_100 : label is "ENABLED"; + attribute GSR of FF_99 : label is "ENABLED"; + attribute GSR of FF_98 : label is "ENABLED"; + attribute GSR of FF_97 : label is "ENABLED"; + attribute GSR of FF_96 : label is "ENABLED"; + attribute GSR of FF_95 : label is "ENABLED"; + attribute GSR of FF_94 : label is "ENABLED"; + attribute GSR of FF_93 : label is "ENABLED"; + attribute GSR of FF_92 : label is "ENABLED"; + attribute GSR of FF_91 : label is "ENABLED"; + attribute GSR of FF_90 : label is "ENABLED"; attribute GSR of FF_89 : label is "ENABLED"; attribute GSR of FF_88 : label is "ENABLED"; attribute GSR of FF_87 : label is "ENABLED"; @@ -447,44 +472,38 @@ architecture Structure of fifo_dc_8to32_dyn is begin -- component instantiation statements - AND2_t19: AND2 + AND2_t17: AND2 port map (A=>WrEn, B=>invout_1, Z=>wren_i); INV_2: INV port map (A=>full_i, Z=>invout_1); - AND2_t18: AND2 + AND2_t16: AND2 port map (A=>RdEn, B=>invout_0, Z=>rden_i); INV_1: INV port map (A=>empty_i, Z=>invout_0); - OR2_t17: OR2 + OR2_t15: OR2 port map (A=>Reset, B=>RPReset, Z=>rRst); - XOR2_t16: XOR2 - port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); - - XOR2_t15: XOR2 - port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); - XOR2_t14: XOR2 - port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); XOR2_t13: XOR2 - port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); XOR2_t12: XOR2 - port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); XOR2_t11: XOR2 - port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); XOR2_t10: XOR2 - port map (A=>wcount_6, B=>wcount_7, Z=>w_gdata_6); + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); XOR2_t9: XOR2 - port map (A=>wcount_7, B=>wcount_8, Z=>w_gdata_7); + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); XOR2_t8: XOR2 port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); @@ -504,52 +523,36 @@ begin XOR2_t3: XOR2 port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); - LUT4_18: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, - AD1=>w_gcount_r27, AD0=>w_gcount_r28, - DO0=>w_g2b_xor_cluster_0); - - LUT4_17: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, - AD1=>w_gcount_r23, AD0=>w_gcount_r24, - DO0=>w_g2b_xor_cluster_1); - - LUT4_16: ROM16X1A - generic map (initval=> X"6996") - port map (AD3=>w_gcount_r27, AD2=>w_gcount_r28, AD1=>scuba_vlo, - AD0=>scuba_vlo, DO0=>wcount_r7); - LUT4_15: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r26, AD2=>w_gcount_r27, - AD1=>w_gcount_r28, AD0=>scuba_vlo, DO0=>wcount_r6); + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, + DO0=>w_g2b_xor_cluster_0); LUT4_14: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, - AD1=>w_gcount_r26, AD0=>wcount_r7, DO0=>wcount_r4); + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r5); LUT4_13: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, - AD1=>w_gcount_r25, AD0=>wcount_r6, DO0=>wcount_r3); + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4); LUT4_12: ROM16X1A generic map (initval=> X"6996") port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, - AD1=>w_gcount_r24, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r2); + AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2); LUT4_11: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>scuba_vlo, AD0=>scuba_vlo, DO0=>wcount_r1); + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); LUT4_10: ROM16X1A generic map (initval=> X"6996") - port map (AD3=>w_g2b_xor_cluster_0, AD2=>w_g2b_xor_cluster_1, - AD1=>w_gcount_r20, AD0=>scuba_vlo, DO0=>wcount_r0); + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0); LUT4_9: ROM16X1A generic map (initval=> X"6996") @@ -583,26 +586,26 @@ begin AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0); XOR2_t2: XOR2 - port map (A=>w_gcount_r28, B=>rcount_6, Z=>rcnt_sub_msb); + port map (A=>w_gcount_r26, B=>rcount_6, Z=>rcnt_sub_msb); LUT4_3: ROM16X1A generic map (initval=> X"0410") - port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28, + port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>empty_cmp_set); LUT4_2: ROM16X1A generic map (initval=> X"1004") - port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r28, + port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>empty_cmp_clr); LUT4_1: ROM16X1A generic map (initval=> X"0140") - port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26, + port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>full_cmp_set); LUT4_0: ROM16X1A generic map (initval=> X"4001") - port map (AD3=>wptr_8, AD2=>wcount_8, AD1=>r_gcount_w26, + port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>full_cmp_clr); INV_0: INV @@ -614,360 +617,400 @@ begin AND2_t0: AND2 port map (A=>rcnt_reg_6, B=>rcnt_reg_5, Z=>ae_setsig); - pdp_ram_0_0_1: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), - DIA3=>Data(3), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo, - ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, - ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, - OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(0), - DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), DOB4=>Q(8), DOB5=>Q(9), - DOB6=>Q(10), DOB7=>Q(11), DOB8=>open, DOB9=>Q(16), - DOB10=>Q(17), DOB11=>Q(18), DOB12=>Q(19), DOB13=>Q(24), - DOB14=>Q(25), DOB15=>Q(26), DOB16=>Q(27), DOB17=>open); - - pdp_ram_0_1_0: DP16KC - generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", - WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 4) - port map (DIA0=>Data(4), DIA1=>Data(5), DIA2=>Data(6), - DIA3=>Data(7), DIA4=>scuba_vlo, DIA5=>scuba_vlo, - DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, - DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, - DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, - DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>wptr_0, ADA3=>wptr_1, - ADA4=>wptr_2, ADA5=>wptr_3, ADA6=>wptr_4, ADA7=>wptr_5, - ADA8=>wptr_6, ADA9=>wptr_7, ADA10=>scuba_vlo, - ADA11=>scuba_vlo, ADA12=>scuba_vlo, ADA13=>scuba_vlo, - CEA=>wren_i, CLKA=>WrClock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, - ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, - ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, - ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, - OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(4), - DOB1=>Q(5), DOB2=>Q(6), DOB3=>Q(7), DOB4=>Q(12), DOB5=>Q(13), - DOB6=>Q(14), DOB7=>Q(15), DOB8=>open, DOB9=>Q(20), - DOB10=>Q(21), DOB11=>Q(22), DOB12=>Q(23), DOB13=>Q(28), - DOB14=>Q(29), DOB15=>Q(30), DOB16=>Q(31), DOB17=>open); - - FF_89: FD1P3BX + pdp_ram_0_0_0: PDPW16KC + generic map (CSDECODE_R=> "0b000", CSDECODE_W=> "0b001", GSR=> "DISABLED", + REGMODE=> "NOREG", DATA_WIDTH_R=> 36, DATA_WIDTH_W=> 36) + port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), + DI4=>Data(4), DI5=>Data(5), DI6=>Data(6), DI7=>Data(7), + DI8=>Data(8), DI9=>Data(9), DI10=>Data(10), DI11=>Data(11), + DI12=>Data(12), DI13=>Data(13), DI14=>Data(14), + DI15=>Data(15), DI16=>Data(16), DI17=>Data(17), + DI18=>Data(18), DI19=>Data(19), DI20=>Data(20), + DI21=>Data(21), DI22=>Data(22), DI23=>Data(23), + DI24=>Data(24), DI25=>Data(25), DI26=>Data(26), + DI27=>Data(27), DI28=>Data(28), DI29=>Data(29), + DI30=>Data(30), DI31=>Data(31), DI32=>scuba_vlo, + DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, + ADW0=>wptr_0, ADW1=>wptr_1, ADW2=>wptr_2, ADW3=>wptr_3, + ADW4=>wptr_4, ADW5=>wptr_5, ADW6=>scuba_vlo, ADW7=>scuba_vlo, + ADW8=>scuba_vlo, BE0=>scuba_vhi, BE1=>scuba_vhi, + BE2=>scuba_vhi, BE3=>scuba_vhi, CEW=>wren_i, CLKW=>WrClock, + CSW0=>scuba_vhi, CSW1=>scuba_vlo, CSW2=>scuba_vlo, + ADR0=>scuba_vlo, ADR1=>scuba_vlo, ADR2=>scuba_vlo, + ADR3=>scuba_vlo, ADR4=>scuba_vlo, ADR5=>rptr_0, ADR6=>rptr_1, + ADR7=>rptr_2, ADR8=>rptr_3, ADR9=>rptr_4, ADR10=>rptr_5, + ADR11=>scuba_vlo, ADR12=>scuba_vlo, ADR13=>scuba_vlo, + CER=>rden_i, CLKR=>RdClock, CSR0=>scuba_vlo, CSR1=>scuba_vlo, + CSR2=>scuba_vlo, RST=>Reset, DO0=>ffidata_18, + DO1=>ffidata_19, DO2=>ffidata_20, DO3=>ffidata_21, + DO4=>ffidata_22, DO5=>ffidata_23, DO6=>ffidata_24, + DO7=>ffidata_25, DO8=>ffidata_26, DO9=>ffidata_27, + DO10=>ffidata_28, DO11=>ffidata_29, DO12=>ffidata_30, + DO13=>ffidata_31, DO14=>open, DO15=>open, DO16=>open, + DO17=>open, DO18=>ffidata_0, DO19=>ffidata_1, + DO20=>ffidata_2, DO21=>ffidata_3, DO22=>ffidata_4, + DO23=>ffidata_5, DO24=>ffidata_6, DO25=>ffidata_7, + DO26=>ffidata_8, DO27=>ffidata_9, DO28=>ffidata_10, + DO29=>ffidata_11, DO30=>ffidata_12, DO31=>ffidata_13, + DO32=>ffidata_14, DO33=>ffidata_15, DO34=>ffidata_16, + DO35=>ffidata_17); + + FF_111: FD1P3BX port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, Q=>wcount_0); - FF_88: FD1P3DX + FF_110: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_1); - FF_87: FD1P3DX + FF_109: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_2); - FF_86: FD1P3DX + FF_108: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_3); - FF_85: FD1P3DX + FF_107: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_4); - FF_84: FD1P3DX + FF_106: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_5); - FF_83: FD1P3DX + FF_105: FD1P3DX port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wcount_6); - FF_82: FD1P3DX - port map (D=>iwcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_7); - - FF_81: FD1P3DX - port map (D=>iwcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wcount_8); - - FF_80: FD1P3DX + FF_104: FD1P3DX port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_0); - FF_79: FD1P3DX + FF_103: FD1P3DX port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_1); - FF_78: FD1P3DX + FF_102: FD1P3DX port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_2); - FF_77: FD1P3DX + FF_101: FD1P3DX port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_3); - FF_76: FD1P3DX + FF_100: FD1P3DX port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_4); - FF_75: FD1P3DX + FF_99: FD1P3DX port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_5); - FF_74: FD1P3DX - port map (D=>w_gdata_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + FF_98: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>w_gcount_6); - FF_73: FD1P3DX - port map (D=>w_gdata_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_7); - - FF_72: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>w_gcount_8); - - FF_71: FD1P3DX + FF_97: FD1P3DX port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_0); - FF_70: FD1P3DX + FF_96: FD1P3DX port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_1); - FF_69: FD1P3DX + FF_95: FD1P3DX port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_2); - FF_68: FD1P3DX + FF_94: FD1P3DX port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_3); - FF_67: FD1P3DX + FF_93: FD1P3DX port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_4); - FF_66: FD1P3DX + FF_92: FD1P3DX port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_5); - FF_65: FD1P3DX + FF_91: FD1P3DX port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, Q=>wptr_6); - FF_64: FD1P3DX - port map (D=>wcount_7, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_7); - - FF_63: FD1P3DX - port map (D=>wcount_8, SP=>wren_i, CK=>WrClock, CD=>Reset, - Q=>wptr_8); - - FF_62: FD1P3BX + FF_90: FD1P3BX port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, Q=>rcount_0); - FF_61: FD1P3DX + FF_89: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_1); - FF_60: FD1P3DX + FF_88: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_2); - FF_59: FD1P3DX + FF_87: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_3); - FF_58: FD1P3DX + FF_86: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_4); - FF_57: FD1P3DX + FF_85: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_5); - FF_56: FD1P3DX + FF_84: FD1P3DX port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rcount_6); - FF_55: FD1P3DX + FF_83: FD1P3DX port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_0); - FF_54: FD1P3DX + FF_82: FD1P3DX port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_1); - FF_53: FD1P3DX + FF_81: FD1P3DX port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_2); - FF_52: FD1P3DX + FF_80: FD1P3DX port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_3); - FF_51: FD1P3DX + FF_79: FD1P3DX port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_4); - FF_50: FD1P3DX + FF_78: FD1P3DX port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_5); - FF_49: FD1P3DX + FF_77: FD1P3DX port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>r_gcount_6); - FF_48: FD1P3DX + FF_76: FD1P3DX port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_0); - FF_47: FD1P3DX + FF_75: FD1P3DX port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_1); - FF_46: FD1P3DX + FF_74: FD1P3DX port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_2); - FF_45: FD1P3DX + FF_73: FD1P3DX port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_3); - FF_44: FD1P3DX + FF_72: FD1P3DX port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_4); - FF_43: FD1P3DX + FF_71: FD1P3DX port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_5); - FF_42: FD1P3DX + FF_70: FD1P3DX port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, Q=>rptr_6); - FF_41: FD1S3DX - port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + FF_69: FD1P3DX + port map (D=>ffidata_0, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(0)); - FF_40: FD1S3DX - port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + FF_68: FD1P3DX + port map (D=>ffidata_1, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(1)); - FF_39: FD1S3DX - port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + FF_67: FD1P3DX + port map (D=>ffidata_2, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(2)); - FF_38: FD1S3DX - port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + FF_66: FD1P3DX + port map (D=>ffidata_3, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(3)); + + FF_65: FD1P3DX + port map (D=>ffidata_4, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(4)); + + FF_64: FD1P3DX + port map (D=>ffidata_5, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(5)); + + FF_63: FD1P3DX + port map (D=>ffidata_6, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(6)); + + FF_62: FD1P3DX + port map (D=>ffidata_7, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(7)); + + FF_61: FD1P3DX + port map (D=>ffidata_8, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(8)); + + FF_60: FD1P3DX + port map (D=>ffidata_9, SP=>RdEn, CK=>RdClock, CD=>rRst, Q=>Q(9)); + + FF_59: FD1P3DX + port map (D=>ffidata_10, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_58: FD1P3DX + port map (D=>ffidata_11, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_57: FD1P3DX + port map (D=>ffidata_12, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_56: FD1P3DX + port map (D=>ffidata_13, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_55: FD1P3DX + port map (D=>ffidata_14, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_54: FD1P3DX + port map (D=>ffidata_15, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_53: FD1P3DX + port map (D=>ffidata_16, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(16)); + + FF_52: FD1P3DX + port map (D=>ffidata_17, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(17)); + + FF_51: FD1P3DX + port map (D=>ffidata_18, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(18)); + + FF_50: FD1P3DX + port map (D=>ffidata_19, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(19)); + + FF_49: FD1P3DX + port map (D=>ffidata_20, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(20)); + + FF_48: FD1P3DX + port map (D=>ffidata_21, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(21)); + + FF_47: FD1P3DX + port map (D=>ffidata_22, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(22)); + + FF_46: FD1P3DX + port map (D=>ffidata_23, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(23)); + + FF_45: FD1P3DX + port map (D=>ffidata_24, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(24)); + + FF_44: FD1P3DX + port map (D=>ffidata_25, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(25)); + + FF_43: FD1P3DX + port map (D=>ffidata_26, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(26)); + + FF_42: FD1P3DX + port map (D=>ffidata_27, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(27)); + + FF_41: FD1P3DX + port map (D=>ffidata_28, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(28)); + + FF_40: FD1P3DX + port map (D=>ffidata_29, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(29)); + + FF_39: FD1P3DX + port map (D=>ffidata_30, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(30)); + + FF_38: FD1P3DX + port map (D=>ffidata_31, SP=>RdEn, CK=>RdClock, CD=>rRst, + Q=>Q(31)); FF_37: FD1S3DX - port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); FF_36: FD1S3DX - port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); FF_35: FD1S3DX - port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); FF_34: FD1S3DX - port map (D=>w_gcount_7, CK=>RdClock, CD=>Reset, Q=>w_gcount_r7); + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); FF_33: FD1S3DX - port map (D=>w_gcount_8, CK=>RdClock, CD=>Reset, Q=>w_gcount_r8); + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); FF_32: FD1S3DX - port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); FF_31: FD1S3DX - port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); FF_30: FD1S3DX - port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); FF_29: FD1S3DX - port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); FF_28: FD1S3DX - port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); FF_27: FD1S3DX - port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); FF_26: FD1S3DX - port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); FF_25: FD1S3DX + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_24: FD1S3DX + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_23: FD1S3DX port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r20); - FF_24: FD1S3DX + FF_22: FD1S3DX port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r21); - FF_23: FD1S3DX + FF_21: FD1S3DX port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r22); - FF_22: FD1S3DX + FF_20: FD1S3DX port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r23); - FF_21: FD1S3DX + FF_19: FD1S3DX port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r24); - FF_20: FD1S3DX + FF_18: FD1S3DX port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r25); - FF_19: FD1S3DX + FF_17: FD1S3DX port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r26); - FF_18: FD1S3DX - port map (D=>w_gcount_r7, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r27); - - FF_17: FD1S3DX - port map (D=>w_gcount_r8, CK=>RdClock, CD=>Reset, - Q=>w_gcount_r28); - FF_16: FD1S3DX port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); @@ -1037,12 +1080,8 @@ begin NC0=>iwcount_4, NC1=>iwcount_5); w_gctr_3: CU2 - port map (CI=>co2, PC0=>wcount_6, PC1=>wcount_7, CO=>co3, - NC0=>iwcount_6, NC1=>iwcount_7); - - w_gctr_4: CU2 - port map (CI=>co3, PC0=>wcount_8, PC1=>scuba_vlo, CO=>co4, - NC0=>iwcount_8, NC1=>open); + port map (CI=>co2, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3, + NC0=>iwcount_6, NC1=>open); r_gctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, @@ -1069,22 +1108,22 @@ begin port map (Z=>scuba_vhi); rcnt_0: FSUB2B - port map (A0=>scuba_vhi, A1=>wcount_r2, B0=>scuba_vlo, + port map (A0=>scuba_vhi, A1=>wcount_r0, B0=>scuba_vlo, B1=>rcount_0, BI=>scuba_vlo, BOUT=>co0_2, S0=>open, S1=>rcnt_sub_0); rcnt_1: FSUB2B - port map (A0=>wcount_r3, A1=>wcount_r4, B0=>rcount_1, + port map (A0=>wcount_r1, A1=>wcount_r2, B0=>rcount_1, B1=>rcount_2, BI=>co0_2, BOUT=>co1_2, S0=>rcnt_sub_1, S1=>rcnt_sub_2); rcnt_2: FSUB2B - port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r6, B0=>rcount_3, + port map (A0=>w_g2b_xor_cluster_0, A1=>wcount_r4, B0=>rcount_3, B1=>rcount_4, BI=>co1_2, BOUT=>co2_2, S0=>rcnt_sub_3, S1=>rcnt_sub_4); rcnt_3: FSUB2B - port map (A0=>wcount_r7, A1=>rcnt_sub_msb, B0=>rcount_5, + port map (A0=>wcount_r5, A1=>rcnt_sub_msb, B0=>rcount_5, B1=>scuba_vlo, BI=>co2_2, BOUT=>co3_2, S0=>rcnt_sub_5, S1=>rcnt_sub_6); @@ -1097,16 +1136,16 @@ begin CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); empty_cmp_0: AGEB2 - port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r2, - B1=>wcount_r3, CI=>cmp_ci, GE=>co0_3); + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_3); empty_cmp_1: AGEB2 - port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r4, + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, B1=>w_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3); empty_cmp_2: AGEB2 - port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r6, - B1=>wcount_r7, CI=>co1_3, GE=>co2_3); + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_3, GE=>co2_3); empty_cmp_3: AGEB2 port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, @@ -1122,24 +1161,20 @@ begin CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); full_cmp_0: AGEB2 - port map (A0=>wcount_0, A1=>wcount_1, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>cmp_ci_1, GE=>co0_4); + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_4); full_cmp_1: AGEB2 - port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w0, - B1=>rcount_w1, CI=>co0_4, GE=>co1_4); + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>r_g2b_xor_cluster_0, CI=>co0_4, GE=>co1_4); full_cmp_2: AGEB2 - port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w2, - B1=>r_g2b_xor_cluster_0, CI=>co1_4, GE=>co2_4); + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_4, GE=>co2_4); full_cmp_3: AGEB2 - port map (A0=>wcount_6, A1=>wcount_7, B0=>rcount_w4, - B1=>rcount_w5, CI=>co2_4, GE=>co3_3); - - full_cmp_4: AGEB2 port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, - B1=>scuba_vlo, CI=>co3_3, GE=>full_d_c); + B1=>scuba_vlo, CI=>co2_4, GE=>full_d_c); a1: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -1179,7 +1214,7 @@ end Structure; -- synopsys translate_off library ecp3; -configuration Structure_CON of fifo_dc_8to32_dyn is +configuration Structure_CON of fifo_32to32_dc is for Structure for all:AGEB2 use entity ecp3.AGEB2(V); end for; for all:AND2 use entity ecp3.AND2(V); end for; @@ -1196,7 +1231,7 @@ configuration Structure_CON of fifo_dc_8to32_dyn is for all:VHI use entity ecp3.VHI(V); end for; for all:VLO use entity ecp3.VLO(V); end for; for all:XOR2 use entity ecp3.XOR2(V); end for; - for all:DP16KC use entity ecp3.DP16KC(V); end for; + for all:PDPW16KC use entity ecp3.PDPW16KC(V); end for; end for; end Structure_CON; diff --git a/nxyter/cores/fifo_dc_8to32_dyn.ipx b/nxyter/cores/fifo_dc_8to32_dyn.ipx deleted file mode 100644 index 21d2bdb..0000000 --- a/nxyter/cores/fifo_dc_8to32_dyn.ipx +++ /dev/null @@ -1,9 +0,0 @@ - - - - - - - - - diff --git a/nxyter/cores/nxyter_input_pll.ipx b/nxyter/cores/nxyter_input_pll.ipx deleted file mode 100644 index d5412bc..0000000 --- a/nxyter/cores/nxyter_input_pll.ipx +++ /dev/null @@ -1,8 +0,0 @@ - - - - - - - - diff --git a/nxyter/cores/nxyter_input_pll.lpc b/nxyter/cores/nxyter_input_pll.lpc deleted file mode 100644 index 874962c..0000000 --- a/nxyter/cores/nxyter_input_pll.lpc +++ /dev/null @@ -1,66 +0,0 @@ -[Device] -Family=latticeecp3 -PartType=LFE3-150EA -PartName=LFE3-150EA-8FN1156C -SpeedGrade=8 -Package=FPBGA1156 -OperatingCondition=COM -Status=P - -[IP] -VendorName=Lattice Semiconductor Corporation -CoreType=LPM -CoreStatus=Demo -CoreName=PLL -CoreRevision=5.3 -ModuleName=nxyter_input_pll -SourceFormat=VHDL -ParameterFileVersion=1.0 -Date=03/27/2013 -Time=23:26:48 - -[Parameters] -Verilog=0 -VHDL=1 -EDIF=1 -Destination=Synplicity -Expression=None -Order=None -IO=0 -Type=ehxpllb -mode=normal -IFrq=125 -Div=1 -ClkOPBp=0 -Post=8 -U_OFrq=125 -OP_Tol=0.0 -OFrq=125.000000 -DutyTrimP=Rising -DelayMultP=0 -fb_mode=User Clock -Mult=1 -Phase=0.0 -Duty=8 -DelayMultS=0 -DPD=50% Duty -DutyTrimS=Rising -DelayMultD=0 -ClkOSDelay=0 -PhaseDuty=Static -CLKOK_INPUT=CLKOP -SecD=2 -U_KFrq=50 -OK_Tol=0.0 -KFrq= -ClkRst=0 -PCDR=0 -FINDELA=0 -VcoRate= -Bandwidth=1.485393 -;DelayControl=No -EnCLKOS=0 -ClkOSBp=0 -EnCLKOK=0 -ClkOKBp=0 -enClkOK2=0 diff --git a/nxyter/cores/nxyter_input_pll.vhd b/nxyter/cores/nxyter_input_pll.vhd deleted file mode 100644 index e0c92c3..0000000 --- a/nxyter/cores/nxyter_input_pll.vhd +++ /dev/null @@ -1,98 +0,0 @@ --- VHDL netlist generated by SCUBA Diamond_2.0_Production (151) --- Module Version: 5.3 ---/d/jspc29/lattice/diamond/2.01/ispfpga/bin/lin/scuba -w -n nxyter_input_pll -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 125 -phase_cntl STATIC -fclkop 125 -fclkop_tol 0.0 -fb_mode USERCLOCK -noclkos -noclkok -norst -noclkok2 -bw -e - --- Wed Mar 27 23:26:48 2013 - -library IEEE; -use IEEE.std_logic_1164.all; --- synopsys translate_off -library ecp3; -use ecp3.components.all; --- synopsys translate_on - -entity nxyter_input_pll is - port ( - CLK: in std_logic; - CLKFB: in std_logic; - CLKOP: out std_logic; - LOCK: out std_logic); - attribute dont_touch : boolean; - attribute dont_touch of nxyter_input_pll : entity is true; -end nxyter_input_pll; - -architecture Structure of nxyter_input_pll is - - -- internal signal declarations - signal CLKOP_t: std_logic; - signal scuba_vlo: std_logic; - - -- local component declarations - component EHXPLLF - generic (FEEDBK_PATH : in String; CLKOK_INPUT : in String; - DELAY_PWD : in String; DELAY_VAL : in Integer; - CLKOS_TRIM_DELAY : in Integer; - CLKOS_TRIM_POL : in String; - CLKOP_TRIM_DELAY : in Integer; - CLKOP_TRIM_POL : in String; CLKOK_BYPASS : in String; - CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; - PHASE_DELAY_CNTL : in String; DUTY : in Integer; - PHASEADJ : in String; CLKOK_DIV : in Integer; - CLKOP_DIV : in Integer; CLKFB_DIV : in Integer; - CLKI_DIV : in Integer; FIN : in String); - port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; - RSTK: in std_logic; WRDEL: in std_logic; DRPAI3: in std_logic; - DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; - DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; - DFPAI0: in std_logic; FDA3: in std_logic; FDA2: in std_logic; - FDA1: in std_logic; FDA0: in std_logic; CLKOP: out std_logic; - CLKOS: out std_logic; CLKOK: out std_logic; CLKOK2: out std_logic; - LOCK: out std_logic; CLKINTFB: out std_logic); - end component; - component VLO - port (Z: out std_logic); - end component; - attribute FREQUENCY_PIN_CLKOP : string; - attribute FREQUENCY_PIN_CLKI : string; - attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "125.000000"; - attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "125.000000"; - attribute syn_keep : boolean; - attribute syn_noprune : boolean; - attribute syn_noprune of Structure : architecture is true; - -begin - -- component instantiation statements - scuba_vlo_inst: VLO - port map (Z=>scuba_vlo); - - PLLInst_0: EHXPLLF - generic map (FEEDBK_PATH=> "USERCLOCK", CLKOK_BYPASS=> "DISABLED", - CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", - CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, - CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", - CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", - PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", - CLKOK_DIV=> 2, CLKOP_DIV=> 8, CLKFB_DIV=> 1, CLKI_DIV=> 1, - FIN=> "125.000000") - port map (CLKI=>CLK, CLKFB=>CLKFB, RST=>scuba_vlo, - RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, - DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, - DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, - DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, - FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, - CLKOS=>open, CLKOK=>open, CLKOK2=>open, LOCK=>LOCK, - CLKINTFB=>open); - - CLKOP <= CLKOP_t; -end Structure; - --- synopsys translate_off -library ecp3; -configuration Structure_CON of nxyter_input_pll is - for Structure - for all:EHXPLLF use entity ecp3.EHXPLLF(V); end for; - for all:VLO use entity ecp3.VLO(V); end for; - end for; -end Structure_CON; - --- synopsys translate_on diff --git a/nxyter/source/nx_timestamp_decode.vhd b/nxyter/source/nx_timestamp_decode.vhd index c2a42c3..9ab9b7e 100644 --- a/nxyter/source/nx_timestamp_decode.vhd +++ b/nxyter/source/nx_timestamp_decode.vhd @@ -39,7 +39,7 @@ entity nx_timestamp_decode is end entity; architecture Behavioral of nx_timestamp_decode is - + -- Gray Decoder signal nx_timestamp : std_logic_vector(13 downto 0); signal nx_channel_id : std_logic_vector( 6 downto 0); @@ -85,15 +85,15 @@ begin -- Debug Line DEBUG_OUT(0) <= CLK_IN; DEBUG_OUT(1) <= NX_NEW_TIMESTAMP_IN; - DEBUG_OUT(2) <= TIMESTAMP_VALID_OUT; - DEBUG_OUT(3) <= new_timestamp; + DEBUG_OUT(2) <= timestamp_valid_o; + DEBUG_OUT(3) <= '0'; DEBUG_OUT(5 downto 4) <= status_bits; DEBUG_OUT(6) <= parity; - DEBUG_OUT(7) <= '0'; - - DEBUG_OUT(14 downto 8) <= nx_channel_id; - DEBUG_OUT(15) <= '0'; + DEBUG_OUT(7) <= nx_token_return_o; + DEBUG_OUT(8) <= nx_nomore_data_o; + DEBUG_OUT(15 downto 9) <= nx_channel_id; + ----------------------------------------------------------------------------- -- Gray Decoder for Timestamp and Chgannel Id ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_timestamp_fifo_read.vhd b/nxyter/source/nx_timestamp_fifo_read.vhd index 8c87424..07110b9 100644 --- a/nxyter/source/nx_timestamp_fifo_read.vhd +++ b/nxyter/source/nx_timestamp_fifo_read.vhd @@ -3,20 +3,21 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; +use work.trb_net_std.all; +use work.trb_net_components.all; use work.nxyter_components.all; entity nx_timestamp_fifo_read is port( CLK_IN : in std_logic; RESET_IN : in std_logic; - + -- nXyter Timestamp Ports NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_FRAME_CLOCK_OUT : out std_logic; NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); NX_NEW_TIMESTAMP_OUT : out std_logic; - + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -38,53 +39,63 @@ architecture Behavioral of nx_timestamp_fifo_read is ----------------------------------------------------------------------------- -- FIFO Input Handler + signal nx_timestamp_reg_t : std_logic_vector(7 downto 0); + signal nx_timestamp_reg : std_logic_vector(7 downto 0); signal fifo_full : std_logic; - signal fifo_write_enable : std_logic; - signal frame_tag_o : std_logic; signal fifo_reset : std_logic; - -- FRAME_CLOCK_GENERATOR - signal frame_clock_ctr : unsigned(1 downto 0); - signal nx_frame_clock_o : std_logic; + -- NX_TIMESTAMP_IN Process + signal frame_byte_ctr : unsigned(1 downto 0); + signal fifo_32bit_word : std_logic_vector(31 downto 0); + signal nx_new_frame : std_logic; + + -- Frame Sync Process + signal frame_byte_pos : unsigned(1 downto 0); + + -- RS Sync FlipFlop + signal nx_frame_synced : std_logic; + signal rs_sync_set : std_logic; + signal rs_sync_reset : std_logic; + + -- Parity Check + signal parity_error : std_logic; + + -- Write to FIFO Handler + signal fifo_data_input : std_logic_vector(31 downto 0); + signal fifo_write_enable : std_logic; - signal frame_clock_ctr_inc_x : std_logic; - signal frame_clock_ctr_inc_l : std_logic; - signal frame_clock_ctr_inc : std_logic; - ----------------------------------------------------------------------------- -- CLK_IN Domain ----------------------------------------------------------------------------- + -- PROC FIFO_READ + signal nx_new_timestamp_o : std_logic; + signal register_fifo_data : std_logic_vector(31 downto 0); + + signal fifo_almost_empty_tt : std_logic; + signal fifo_almost_empty_t : std_logic; + + -- FIFO Output Handler - signal fifo_out : std_logic_vector(35 downto 0); + signal fifo_out : std_logic_vector(31 downto 0); signal fifo_empty : std_logic; signal fifo_almost_empty : std_logic; - signal fifo_almost_empty_prev : std_logic; signal fifo_read_enable : std_logic; - signal fifo_data_valid_x : std_logic; + signal fifo_data_valid_t : std_logic; signal fifo_data_valid : std_logic; - signal register_fifo_data : std_logic_vector(31 downto 0); - signal fifo_new_frame : std_logic; - - signal frame_clock_ctr_inc_o : std_logic; - - -- RS Sync FlipFlop - signal nx_frame_synced : std_logic; - - -- Frame Sync Process - type STATES_SYNC is (S_SYNC_CHECK, - S_SYNC_RESYNC, - S_SYNC_WAIT - ); + signal read_enable_pause : std_logic; - signal STATE_SYNC : STATES_SYNC; + -- Resync Counter Process + signal resync_counter : unsigned(11 downto 0); + signal resync_ctr_inc : std_logic; + signal nx_clk_active : std_logic; + + -- Parity Error Counter Process + signal parity_error_counter : unsigned(11 downto 0); + signal parity_error_ctr_inc : std_logic; - signal rs_sync_set : std_logic; - signal rs_sync_reset : std_logic; - signal frame_clock_ctr_inc_s : std_logic; - signal frame_sync_wait_ctr : unsigned(7 downto 0); - signal nx_frame_resync_ctr : unsigned(7 downto 0); - signal frame_sync_wait_done : std_logic; + signal reg_nx_frame_synced_t : std_logic; + signal reg_nx_frame_synced : std_logic; -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); @@ -92,327 +103,337 @@ architecture Behavioral of nx_timestamp_fifo_read is signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal reset_ctr : std_logic; - signal frame_clock_ctr_inc_r : std_logic; + signal reset_resync_ctr : std_logic; + signal reset_parity_error_ctr : std_logic; signal fifo_delay_r : std_logic_vector(5 downto 0); signal fifo_reset_r : std_logic; - - signal pll_lock : std_logic; - signal nx_clk_in_delayed : std_logic; - signal nx_timestamp_reg : std_logic_vector(7 downto 0); - + begin - DEBUG_OUT(0) <= '0'; - DEBUG_OUT(1) <= '0'; - DEBUG_OUT(2) <= fifo_empty; - DEBUG_OUT(3) <= fifo_read_enable; - DEBUG_OUT(4) <= fifo_data_valid; - DEBUG_OUT(5) <= fifo_new_frame; - DEBUG_OUT(6) <= NX_NEW_TIMESTAMP_OUT; - DEBUG_OUT(7) <= fifo_almost_empty; - DEBUG_OUT(15 downto 8) <= (others => '0'); - --- DEBUG_OUT(0) <= CLK_IN; --- --- DEBUG_OUT(1) <= NX_TIMESTAMP_CLK_IN; --- DEBUG_OUT(2) <= NX_FRAME_CLOCK_OUT; --- DEBUG_OUT(3) <= NX_FRAME_SYNC_OUT; --- -- DEBUG_OUT(4) <= NX_NEW_FRAME_OUT; --- -- DEBUG_OUT(5) <= frame_clock_ctr_inc_o; --- -- DEBUG_OUT(6) <= frame_tag_o; --- -- DEBUG_OUT(7) <= '0'; --- DEBUG_OUT(7 downto 4) <= fifo_out(3 downto 0); --- DEBUG_OUT(15 downto 8) <= fifo_out(34 downto 27); - - THE_INPUT_PLL : entity work.nxyter_input_pll - port map( - CLK => NX_TIMESTAMP_CLK_IN, - CLKFB => nx_clk_in_delayed, - CLKOP => nx_clk_in_delayed, - LOCK => pll_lock --use this to generate FIFO reset! - ); - - nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(nx_clk_in_delayed); + DEBUG_OUT(0) <= NX_TIMESTAMP_CLK_IN; + DEBUG_OUT(1) <= parity_error; + DEBUG_OUT(2) <= nx_new_frame; + DEBUG_OUT(3) <= rs_sync_set; + DEBUG_OUT(4) <= rs_sync_reset; + DEBUG_OUT(5) <= nx_frame_synced; + DEBUG_OUT(7 downto 6) <= frame_byte_pos; + + DEBUG_OUT(8) <= fifo_write_enable; + DEBUG_OUT(9) <= fifo_read_enable; + DEBUG_OUT(10) <= nx_new_timestamp_o; + DEBUG_OUT(11) <= fifo_data_valid; + DEBUG_OUT(12) <= nx_clk_active; + DEBUG_OUT(13) <= resync_ctr_inc; + DEBUG_OUT(14) <= parity_error_ctr_inc; + DEBUG_OUT(15) <= reg_nx_frame_synced; - ----------------------------------------------------------------------------- - -- Dual Clock FIFO 9bit to 36bit - ----------------------------------------------------------------------------- - -- Send data to FIFO, depth is 256 - fifo_dc_9to36_dyn_1: fifo_dc_9to36_dyn - port map ( - Data(7 downto 0) => nx_timestamp_reg, - Data(8) => frame_tag_o, - WrClock => nx_clk_in_delayed, - RdClock => CLK_IN, - WrEn => fifo_write_enable, - RdEn => fifo_read_enable, - Reset => fifo_reset, - RPReset => fifo_reset, - AmEmptyThresh => fifo_delay_r, - Q => fifo_out, - Empty => fifo_empty, - Full => fifo_full, - AlmostEmpty => fifo_almost_empty - ); - fifo_write_enable <= not RESET_IN and pll_lock; - fifo_reset <= (RESET_IN or fifo_reset_r) and not pll_lock; +--DEBUG_OUT(15 downto 8) <= fifo_32bit_word(15 downto 8); + + +-- DEBUG_OUT(6) <= nx_new_timestamp_o; +-- DEBUG_OUT(7) <= fifo_almost_empty; +-- DEBUG_OUT(8) <= nx_frame_synced; +-- DEBUG_OUT(9) <= rs_sync_reset; +-- DEBUG_OUT(11 downto 10) <= frame_tag_pos; +-- DEBUG_OUT(12) <= fifo_full; +-- DEBUG_OUT(15 downto 13) <= (others => '0'); + + + --DEBUG_OUT(8 downto 1) <= fifo_out(7 downto 0); --nx_timestamp_reg_t when rising_edge(NX_TIMESTAMP_CLK_IN) ; ----------------------------------------------------------------------------- - -- FIFO Input Handler + -- NX_TIMESTAMP_CLK_IN Domain ----------------------------------------------------------------------------- - - -- Cross ClockDomain CLK_IN --> NX_TIMESTAMP_CLK_IN for signal - -- frame_clock_ctr_inc - PROC_FIFO_IN_HANDLER_SYNC: process(nx_clk_in_delayed) + + nx_timestamp_reg <= NX_TIMESTAMP_IN when rising_edge(NX_TIMESTAMP_CLK_IN); + + -- Transfer 8 to 32Bit + PROC_8_TO_32_BIT: process(NX_TIMESTAMP_CLK_IN) begin - if( rising_edge(nx_clk_in_delayed) ) then + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then if( RESET_IN = '1' ) then - frame_clock_ctr_inc_x <= '0'; - frame_clock_ctr_inc_l <= '0'; + frame_byte_ctr <= (others => '0'); + fifo_32bit_word <= (others => '0'); + nx_new_frame <= '0'; else - frame_clock_ctr_inc_x <= frame_clock_ctr_inc_o; - frame_clock_ctr_inc_l <= frame_clock_ctr_inc_x; + nx_new_frame <= '0'; + + case frame_byte_pos is + when "11" => fifo_32bit_word(31 downto 24) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "10" => fifo_32bit_word(23 downto 16) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "01" => fifo_32bit_word(15 downto 8) <= nx_timestamp_reg; + frame_byte_ctr <= frame_byte_ctr + 1; + + when "00" => fifo_32bit_word( 7 downto 0) <= nx_timestamp_reg; + if (frame_byte_ctr = "11") then + nx_new_frame <= '1'; + end if; + frame_byte_ctr <= (others => '0'); + end case; end if; end if; - end process PROC_FIFO_IN_HANDLER_SYNC; - - -- Signal frame_tag_ctr_inc_l might be 2 clocks long --> I need 1 - level_to_pulse_1: level_to_pulse - port map ( - CLK_IN => nx_clk_in_delayed, - RESET_IN => RESET_IN, - LEVEL_IN => frame_clock_ctr_inc_l, - PULSE_OUT => frame_clock_ctr_inc - ); - - PROC_FRAME_CLOCK_GENERATOR: process(nx_clk_in_delayed) + end process PROC_8_TO_32_BIT; + + -- Frame Sync process + PROC_SYNC_TO_NX_FRAME: process(NX_TIMESTAMP_CLK_IN) begin - if( rising_edge(nx_clk_in_delayed) ) then + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then if( RESET_IN = '1' ) then - frame_clock_ctr <= (others => '0'); - nx_frame_clock_o <= '0'; - frame_tag_o <= '0'; + frame_byte_pos <= "11"; + rs_sync_set <= '0'; + rs_sync_reset <= '0'; else - case frame_clock_ctr is - - when "00" => - nx_frame_clock_o <= '0'; - frame_tag_o <= '1'; - when "01" => - nx_frame_clock_o <= '1'; - frame_tag_o <= '0'; - when "10" => - nx_frame_clock_o <= '1'; - frame_tag_o <= '0'; - when "11" => - nx_frame_clock_o <= '0'; - frame_tag_o <= '0'; - when others => null; + rs_sync_set <= '0'; + rs_sync_reset <= '0'; + if (nx_new_frame = '1') then + case fifo_32bit_word is + when x"7f7f7f06" => + rs_sync_set <= '1'; + frame_byte_pos <= frame_byte_pos - 1; + + when x"7f7f067f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 2; + + when x"7f067f7f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 3; + + when x"067f7f7f" => + rs_sync_reset <= '1'; + frame_byte_pos <= frame_byte_pos - 4; + + when others => + frame_byte_pos <= frame_byte_pos - 1; + end case; + else + frame_byte_pos <= frame_byte_pos - 1; + end if; + end if; + end if; + end process PROC_SYNC_TO_NX_FRAME; - end case; + -- RS FlipFlop to hold Sync Status + PROC_RS_FRAME_SYNCED: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1' or rs_sync_reset = '1') then + nx_frame_synced <= '0'; + elsif (rs_sync_set = '1') then + nx_frame_synced <= '1'; + end if; + end if; + end process PROC_RS_FRAME_SYNCED; - if (frame_clock_ctr_inc = '1') then - frame_clock_ctr <= frame_clock_ctr + 2; - else - frame_clock_ctr <= frame_clock_ctr + 1; + -- Check Parity + PROC_PARITY_CHECK: process(NX_TIMESTAMP_CLK_IN) + variable parity_bits : std_logic_vector(22 downto 0); + variable parity : std_logic; + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1') then + parity_error <= '0'; + else + parity_error <= '0'; + if (nx_new_frame = '1' and nx_frame_synced = '1') then + -- Timestamp Bit #6 is excluded (funny nxyter-bug) + parity_bits := fifo_32bit_word(31 downto 24) & + fifo_32bit_word(21 downto 16) & + fifo_32bit_word(14 downto 8) & + fifo_32bit_word( 2 downto 1); + parity := xor_all(parity_bits); + + if (parity /= fifo_32bit_word(0)) then + parity_error <= '1'; + end if; end if; - end if; end if; - end process PROC_FRAME_CLOCK_GENERATOR; + end process PROC_PARITY_CHECK; - + -- Write to FIFO + PROC_WRITE_TO_FIFO: process(NX_TIMESTAMP_CLK_IN) + begin + if( rising_edge(NX_TIMESTAMP_CLK_IN) ) then + if (RESET_IN = '1') then + fifo_data_input <= (others => '0'); + fifo_write_enable <= '0'; + else + fifo_data_input <= x"deadbeef"; + fifo_write_enable <= '0'; + if (nx_new_frame = '1' and nx_frame_synced = '1') then + fifo_data_input <= fifo_32bit_word; + fifo_write_enable <= '1'; + end if; + end if; + end if; + end process PROC_WRITE_TO_FIFO; + + fifo_32to32_dc_1: fifo_32to32_dc + port map ( + Data => fifo_data_input, + WrClock => NX_TIMESTAMP_CLK_IN, + RdClock => CLK_IN, + WrEn => fifo_write_enable, + RdEn => fifo_read_enable, + Reset => fifo_reset, + RPReset => fifo_reset, + AmEmptyThresh => fifo_delay_r, + Q => fifo_out, + Empty => fifo_empty, + Full => fifo_full, + AlmostEmpty => fifo_almost_empty + ); + + fifo_reset <= (RESET_IN or fifo_reset_r); + +-- -- Reset NX_TIMESTAMP_CLK Domain +-- PROC_NX_CLK_DOMAIN_RESET: process(CLK_IN) +-- begin +-- if( rising_edge(CLK_IN) ) then +-- if( RESET_IN = '1' ) then +-- reset_nx_domain_ctr <= (others => '0'); +-- reset_nx_domain <= '1'; +-- else +-- if (nx_clk_pulse = '1') then +-- nx_clk_pulse_ctr <= nx_clk_pulse_ctr + 1; +-- end if; +-- +-- end if; +-- +-- end if; +-- end process PROC_NX_CLK_DOMAIN_RESET; + + PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) + begin + if(rising_edge(NX_TIMESTAMP_CLK_IN)) then + if(RESET_IN = '1' ) then + nx_clk_active <= '0'; + else + nx_clk_active <= not nx_clk_active; + end if; + end if; + end process PROC_NX_CLK_ACT; + ----------------------------------------------------------------------------- - -- FIFO Output Handler and Sync FIFO + -- CLK_IN Domain ----------------------------------------------------------------------------- + -- FIFO Read Handler PROC_FIFO_READ_ENABLE: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - fifo_almost_empty_prev <= '0'; fifo_read_enable <= '0'; - fifo_data_valid_x <= '0'; + read_enable_pause <= '0'; + fifo_data_valid_t <= '0'; fifo_data_valid <= '0'; else - if (fifo_almost_empty = '0' and fifo_almost_empty_prev = '1') then + if (fifo_almost_empty = '0' and read_enable_pause = '0') then fifo_read_enable <= '1'; + read_enable_pause <= '1'; else fifo_read_enable <= '0'; - + read_enable_pause <= '0'; end if; - fifo_almost_empty_prev <= fifo_almost_empty; - fifo_data_valid_x <= fifo_read_enable; - fifo_data_valid <= fifo_data_valid_x; + + -- Delay read signal by one CLK + fifo_data_valid_t <= fifo_read_enable; + fifo_data_valid <= fifo_data_valid_t; + end if; end if; end process PROC_FIFO_READ_ENABLE; - - -- Read only in case FIFO is not empty, i.e. data_valid is set PROC_FIFO_READ: process(CLK_IN) - - variable frame_tag : std_logic_vector(3 downto 0); - begin if( rising_edge(CLK_IN) ) then if (RESET_IN = '1') then - fifo_new_frame <= '0'; + nx_new_timestamp_o <= '0'; register_fifo_data <= (others => '0'); else - frame_tag := fifo_out( 8) & fifo_out(17) & - fifo_out(26) & fifo_out(35); - fifo_new_frame <= '0'; - register_fifo_data <= x"deadbeef"; - + nx_new_timestamp_o <= '0'; + register_fifo_data <= x"affebabe"; + if (fifo_data_valid = '1') then - - case frame_tag is - - when "1000" => - register_fifo_data(31 downto 24) <= fifo_out( 7 downto 0); - register_fifo_data(23 downto 16) <= fifo_out(16 downto 9); - register_fifo_data(15 downto 8) <= fifo_out(25 downto 18); - register_fifo_data( 7 downto 0) <= fifo_out(34 downto 27); - fifo_new_frame <= '1'; - - when "0100" => - register_fifo_data(31 downto 24) <= fifo_out(16 downto 9); - register_fifo_data(23 downto 16) <= fifo_out(25 downto 18); - register_fifo_data(15 downto 8) <= fifo_out(34 downto 27); - register_fifo_data( 7 downto 0) <= fifo_out( 7 downto 0); - fifo_new_frame <= '1'; - - when "0010" => - register_fifo_data(31 downto 24) <= fifo_out(25 downto 18); - register_fifo_data(23 downto 16) <= fifo_out(34 downto 27); - register_fifo_data(15 downto 8) <= fifo_out( 7 downto 0); - register_fifo_data( 7 downto 0) <= fifo_out(16 downto 9); - fifo_new_frame <= '1'; - - when "0001" => - register_fifo_data(31 downto 24) <= fifo_out(34 downto 27); - register_fifo_data(23 downto 16) <= fifo_out( 7 downto 0); - register_fifo_data(15 downto 8) <= fifo_out(16 downto 9); - register_fifo_data( 7 downto 0) <= fifo_out(25 downto 18); - fifo_new_frame <= '1'; - - when others => null; - - end case; - + register_fifo_data <= fifo_out; + nx_new_timestamp_o <= '1'; end if; end if; end if; end process PROC_FIFO_READ; - ----------------------------------------------------------------------------- - -- Sync to NX_DATA FRAME + -- Status Counters ----------------------------------------------------------------------------- - - -- RS FlipFlop to hold Sync Status - PROC_RS_FRAME_SYNCED: process(CLK_IN) - begin - if( rising_edge(CLK_IN) ) then - if (RESET_IN = '1' or rs_sync_reset = '1') then - nx_frame_synced <= '0'; - elsif (rs_sync_set = '1') then - nx_frame_synced <= '1'; - end if; - end if; - end process PROC_RS_FRAME_SYNCED; - -- Frame Resync Timer_done Timer - nx_timer_1: nx_timer - generic map ( - CTR_WIDTH => 8 - ) + -- Domain Transfers + pulse_sync_1: pulse_sync port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - TIMER_START_IN => frame_sync_wait_ctr, - TIMER_DONE_OUT => frame_sync_wait_done + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => rs_sync_reset, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => resync_ctr_inc ); - -- Frame Sync process - PROC_SYNC_TO_NX_FRAME: process(CLK_IN) - - variable fifo_tag_given : std_logic_vector(3 downto 0); + pulse_sync_2: pulse_sync + port map ( + CLK_A_IN => NX_TIMESTAMP_CLK_IN, + RESET_A_IN => RESET_IN, + PULSE_A_IN => parity_error, + CLK_B_IN => CLK_IN, + RESET_B_IN => RESET_IN, + PULSE_B_OUT => parity_error_ctr_inc + ); + PROC_SYNC_FRAME_SYNC: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then - if( RESET_IN = '1' ) then - rs_sync_set <= '0'; - rs_sync_reset <= '1'; - frame_clock_ctr_inc_s <= '0'; - nx_frame_resync_ctr <= (others => '0'); - frame_sync_wait_ctr <= (others => '0'); - STATE_SYNC <= S_SYNC_CHECK; + if(RESET_IN = '1' ) then + reg_nx_frame_synced_t <= '0'; + reg_nx_frame_synced <= '0'; else - rs_sync_set <= '0'; - rs_sync_reset <= '0'; - frame_clock_ctr_inc_s <= '0'; - nx_frame_resync_ctr <= nx_frame_resync_ctr; - frame_sync_wait_ctr <= (others => '0'); - - fifo_tag_given := fifo_out(35) & fifo_out(26) & - fifo_out(17) & fifo_out(8); - - case STATE_SYNC is - when S_SYNC_CHECK => - if (fifo_new_frame = '1') then - case register_fifo_data is - when x"7f7f7f06" => - rs_sync_set <= '1'; - STATE_SYNC <= S_SYNC_CHECK; - - when x"067f7f7f" => - STATE_SYNC <= S_SYNC_RESYNC; - - when x"7f067f7f" => - STATE_SYNC <= S_SYNC_RESYNC; - - when x"7f7f067f" => - STATE_SYNC <= S_SYNC_RESYNC; - - when others => - STATE_SYNC <= S_SYNC_CHECK; - - end case; - else - STATE_SYNC <= S_SYNC_CHECK; - end if; - - when S_SYNC_RESYNC => - rs_sync_reset <= '1'; - frame_clock_ctr_inc_s <= '1'; - if (reset_ctr = '0') then - nx_frame_resync_ctr <= nx_frame_resync_ctr + 1; - end if; - - frame_sync_wait_ctr <= x"14"; - STATE_SYNC <= S_SYNC_WAIT; - - when S_SYNC_WAIT => - if (frame_sync_wait_done = '0') then - STATE_SYNC <= S_SYNC_WAIT; - else - STATE_SYNC <= S_SYNC_CHECK; - end if; - - end case; - - if (reset_ctr = '1') then - nx_frame_resync_ctr <= (others => '0'); + reg_nx_frame_synced_t <= nx_frame_synced; + reg_nx_frame_synced <= reg_nx_frame_synced_t; + end if; + end if; + end process PROC_SYNC_FRAME_SYNC; + + -- Counters + PROC_RESYNC_COUNTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_resync_ctr = '1') then + resync_counter <= (others => '0'); + else + if (resync_ctr_inc = '1') then + resync_counter <= resync_counter + 1; end if; end if; end if; - end process PROC_SYNC_TO_NX_FRAME; + end process PROC_RESYNC_COUNTER; + PROC_PARITY_ERROR_COUNTER: process(CLK_IN) + begin + if( rising_edge(CLK_IN) ) then + if (RESET_IN = '1' or reset_parity_error_ctr = '1') then + parity_error_counter <= (others => '0'); + else + if (parity_error_ctr_inc = '1') then + parity_error_counter <= parity_error_counter + 1; + end if; + end if; + end if; + end process PROC_PARITY_ERROR_COUNTER; + ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- @@ -422,23 +443,23 @@ begin begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - frame_clock_ctr_inc_r <= '0'; - reset_ctr <= '0'; - fifo_delay_r <= "000010"; - fifo_reset_r <= '0'; - else - slv_data_out_o <= (others => '0'); - slv_ack_o <= '0'; - slv_unknown_addr_o <= '0'; - slv_no_more_data_o <= '0'; - frame_clock_ctr_inc_r <= '0'; - reset_ctr <= '0'; - fifo_reset_r <= '0'; - + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + reset_resync_ctr <= '0'; + reset_parity_error_ctr <= '0'; + fifo_delay_r <= "000010"; + fifo_reset_r <= '0'; + else + slv_data_out_o <= (others => '0'); + slv_ack_o <= '0'; + slv_unknown_addr_o <= '0'; + slv_no_more_data_o <= '0'; + reset_resync_ctr <= '0'; + reset_parity_error_ctr <= '0'; + fifo_reset_r <= '0'; + if (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => @@ -448,63 +469,66 @@ begin when x"0001" => slv_data_out_o(0) <= fifo_full; slv_data_out_o(1) <= fifo_empty; - slv_data_out_o(3 downto 2) <= (others => '0'); + slv_data_out_o(2) <= fifo_almost_empty; + slv_data_out_o(3) <= '0'; slv_data_out_o(4) <= fifo_data_valid; - slv_data_out_o(5) <= fifo_new_frame; - slv_data_out_o(30 downto 6) <= (others => '0'); - slv_data_out_o(31) <= nx_frame_synced; + slv_data_out_o(29 downto 5) <= (others => '0'); + slv_data_out_o(30) <= '0'; + slv_data_out_o(31) <= reg_nx_frame_synced; slv_ack_o <= '1'; when x"0002" => - slv_data_out_o(7 downto 0) <= nx_frame_resync_ctr; - slv_data_out_o(31 downto 8) <= (others => '0'); + slv_data_out_o(11 downto 0) <= resync_counter; + slv_data_out_o(31 downto 12) <= (others => '0'); slv_ack_o <= '1'; when x"0003" => - slv_data_out_o(5 downto 0) <= fifo_delay_r; + slv_data_out_o(11 downto 0) <= parity_error_counter; + slv_data_out_o(31 downto 12) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0004" => + slv_data_out_o( 5 downto 0) <= fifo_delay_r; slv_data_out_o(31 downto 6) <= (others => '0'); slv_ack_o <= '1'; - + when others => slv_unknown_addr_o <= '1'; end case; elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is - when x"0001" => - frame_clock_ctr_inc_r <= '1'; - slv_ack_o <= '1'; - when x"0002" => - reset_ctr <= '1'; - slv_ack_o <= '1'; - + reset_resync_ctr <= '1'; + slv_ack_o <= '1'; + when x"0003" => - if (SLV_DATA_IN < x"0000003c" and - SLV_DATA_IN > x"00000001") then - fifo_delay_r <= SLV_DATA_IN(5 downto 0); - fifo_reset_r <= '1'; + reset_parity_error_ctr <= '1'; + slv_ack_o <= '1'; + + when x"0004" => + if (SLV_DATA_IN < x"0000003c" and + SLV_DATA_IN > x"00000001") then + fifo_delay_r <= SLV_DATA_IN(5 downto 0); + fifo_reset_r <= '1'; end if; - slv_ack_o <= '1'; + slv_ack_o <= '1'; when others => - slv_unknown_addr_o <= '1'; + slv_unknown_addr_o <= '1'; end case; end if; end if; end if; end process PROC_FIFO_REGISTERS; - frame_clock_ctr_inc_o <= frame_clock_ctr_inc_r or frame_clock_ctr_inc_s; - -- Output Signals + NX_TIMESTAMP_OUT <= register_fifo_data; + NX_NEW_TIMESTAMP_OUT <= nx_new_timestamp_o; + SLV_DATA_OUT <= slv_data_out_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; SLV_ACK_OUT <= slv_ack_o; - - NX_FRAME_CLOCK_OUT <= nx_frame_clock_o; - NX_TIMESTAMP_OUT <= register_fifo_data; - NX_NEW_TIMESTAMP_OUT <= fifo_new_frame and nx_frame_synced; - + end Behavioral; diff --git a/nxyter/source/nxyter.vhd b/nxyter/source/nxyter.vhd index 01e38af..f99ae31 100644 --- a/nxyter/source/nxyter.vhd +++ b/nxyter/source/nxyter.vhd @@ -19,7 +19,7 @@ entity nXyter_FEE_board is port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - + -- I2C Ports I2C_SDA_INOUT : inout std_logic; -- nXyter I2C fdata line I2C_SCL_INOUT : inout std_logic; -- nXyter I2C Clock line @@ -35,7 +35,6 @@ entity nXyter_FEE_board is NX_CLK128_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_RESET_OUT : out std_logic; - NX_CLK256A_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; -- ADC nXyter Pulse Hight Ports @@ -60,7 +59,6 @@ entity nXyter_FEE_board is REGIO_UNKNOWN_ADDR_OUT : out std_logic; -- Debug Signals - CLK_128_IN : in std_logic; DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) ); @@ -73,8 +71,8 @@ architecture Behavioral of nXyter_FEE_board is -- Signals ------------------------------------------------------------------------------- -- Clock 256 - signal clk_256_o : std_logic; - + signal clk_250_o : std_logic; + -- Bus Handler signal slv_read : std_logic_vector(10-1 downto 0); signal slv_write : std_logic_vector(10-1 downto 0); @@ -99,7 +97,7 @@ architecture Behavioral of nXyter_FEE_board is -- Timestamp FIFO Read signal nx_timestamp : std_logic_vector(31 downto 0); signal nx_new_timestamp : std_logic; - signal nx_frame_clock_o : std_logic; + signal adc_clk_o : std_logic; -- Timestamp Decode Handlers signal timestamp_data : std_logic_vector(31 downto 0); @@ -180,22 +178,26 @@ begin -- DEBUG_LINE_OUT(14 downto 13) <= timestamp_status; -- DEBUG_LINE_OUT(15) <= slv_ack(3); - --DEBUG_LINE_OUT(0) <= CLK_IN; - --DEBUG_LINE_OUT(1) <= trigger; - --DEBUG_LINE_OUT(2) <= trigger_ack; - --DEBUG_LINE_OUT(3) <= trigger_busy; - --DEBUG_LINE_OUT(4) <= nx_new_timestamp; +-- DEBUG_LINE_OUT(0) <= CLK_IN; +-- DEBUG_LINE_OUT(1) <= CLK_125_IN; +-- DEBUG_LINE_OUT(2) <= clk_250_o; +-- DEBUG_LINE_OUT(3) <= NX_CLK128_IN; +-- DEBUG_LINE_OUT(4) <= nx_timestamp(0); +-- DEBUG_LINE_OUT(15 downto 5) <= (others => '0'); --DEBUG_LINE_OUT(5) <= timestamp_valid; --DEBUG_LINE_OUT(6) <= nx_token_return; --DEBUG_LINE_OUT(7) <= nx_nomore_data; --- DEBUG_LINE_OUT(4) <= '0'; +-- DEBUG_LINE_OUT(0) <= NX_CLK128_IN; +-- DEBUG_LINE_OUT(8 downto 1) <= NX_TIMESTAMP_IN; +-- DEBUG_LINE_OUT(13 downto 9) <= (others => '0'); +-- DEBUG_LINE_OUT(15) <= CLK_IN; -- DEBUG_LINE_OUT(5) <= '0'; -- DEBUG_LINE_OUT(6) <= '0'; -- DEBUG_LINE_OUT(7) <= '0'; -- -- --- DEBUG_LINE_OUT(8) <= ADC_FCLK_IN; +-- DEBUG_gLINE_OUT(8) <= ADC_FCLK_IN; -- DEBUG_LINE_OUT(9) <= ADC_DCLK_IN; -- DEBUG_LINE_OUT(10) <= ADC_SC_CLK32_OUT; -- DEBUG_LINE_OUT(11) <= ADC_A_IN; @@ -205,22 +207,11 @@ begin -- DEBUG_LINE_OUT(15) <= '0'; --DEBUG_LINE_OUT(15 downto 8) <= (others => '0'); - - + ------------------------------------------------------------------------------- -- Port Maps ------------------------------------------------------------------------------- - pll_nx_clk256_1: pll_nx_clk256 - port map ( - CLK => CLK_IN, - CLKOP => clk_256_o, - LOCK => open - ); - - NX_CLK256A_OUT <= clk_256_o; - - THE_BUS_HANDLER: trb_net16_regio_bus_handler generic map( PORT_NUMBER => 9, @@ -238,7 +229,7 @@ begin PORT_ADDR_MASK => ( 0 => 3, -- Control Register Handler 1 => 0, -- I2C master - 2 => 2, -- Timestamp Fifo + 2 => 3, -- Timestamp Fifo 3 => 1, -- Data Buffer 4 => 0, -- SPI Master 5 => 3, -- Trigger Generator @@ -291,8 +282,8 @@ begin BUS_WRITE_ENABLE_OUT(2) => slv_write(2), BUS_DATA_OUT(2*32+31 downto 2*32) => slv_data_wr(2*32+31 downto 2*32), BUS_DATA_IN(2*32+31 downto 2*32) => slv_data_rd(2*32+31 downto 2*32), - BUS_ADDR_OUT(2*16+1 downto 2*16) => slv_addr(2*16+1 downto 2*16), - BUS_ADDR_OUT(2*16+15 downto 2*16+2) => open, + BUS_ADDR_OUT(2*16+2 downto 2*16) => slv_addr(2*16+2 downto 2*16), + BUS_ADDR_OUT(2*16+15 downto 2*16+3) => open, BUS_TIMEOUT_OUT(2) => open, BUS_DATAREADY_IN(2) => slv_ack(2), BUS_WRITE_ACK_IN(2) => slv_ack(2), @@ -459,7 +450,7 @@ begin nx_fpga_timestamp_1: nx_fpga_timestamp port map ( - CLK_IN => clk_256_o, + CLK_IN => clk_250_o, RESET_IN => RESET_IN, TIMESTAMP_SYNC_IN => nx_ts_reset_o, TRIGGER_IN => timestamp_hold, @@ -533,12 +524,12 @@ begin port map ( CLK_IN => CLK_IN, RESET_IN => RESET_IN, - + NX_TIMESTAMP_CLK_IN => NX_CLK128_IN, NX_TIMESTAMP_IN => NX_TIMESTAMP_IN, - NX_FRAME_CLOCK_OUT => nx_frame_clock_o, NX_TIMESTAMP_OUT => nx_timestamp, NX_NEW_TIMESTAMP_OUT => nx_new_timestamp, + SLV_READ_IN => slv_read(2), SLV_WRITE_IN => slv_write(2), SLV_DATA_OUT => slv_data_rd(2*32+31 downto 2*32), @@ -548,8 +539,8 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(2), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(2), - -- DEBUG_OUT => DEBUG_LINE_OUT - DEBUG_OUT => open + DEBUG_OUT => DEBUG_LINE_OUT + -- DEBUG_OUT => open ); @@ -579,7 +570,7 @@ begin SLV_ACK_OUT => slv_ack(6), SLV_NO_MORE_DATA_OUT => slv_no_more_data(6), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(6), - --DEBUG_OUT => DEBUG_OUT + -- DEBUG_OUT => DEBUG_LINE_OUT DEBUG_OUT => open ); @@ -657,8 +648,8 @@ begin -- ) -- port map ( -- CLK => CLK_IN, --- CLK_ADCREF => nx_frame_clock_o, -- adc_ref_clk, --- CLK_ADCDAT => nx_frame_clock_o, -- adc_dat_clk, +-- CLK_ADCREF => adc_clk, -- adc_ref_clk, +-- CLK_ADCDAT => adc_clk, -- adc_dat_clk, -- RESTART_IN => '0', -- adc_restart, -- ADCCLK_OUT => ADC_SC_CLK32_OUT, -- adc_sc_clk32_o, -- ADC_DATA(0) => ADC_A_IN, -- adc_data_i, @@ -673,6 +664,9 @@ begin -- DEBUG => open -- ); + + ADC_SC_CLK32_OUT <= adc_clk_o; + ------------------------------------------------------------------------------- -- nXyter Signals ------------------------------------------------------------------------------- @@ -683,7 +677,7 @@ begin ------------------------------------------------------------------------------- -- ADC Signals ------------------------------------------------------------------------------- - + ------------------------------------------------------------------------------- diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 8a6c82c..ae004f6 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -25,7 +25,6 @@ component nXyter_FEE_board NX_CLK128_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); NX_RESET_OUT : out std_logic; - NX_CLK256A_OUT : out std_logic; NX_TESTPULSE_OUT : out std_logic; ADC_FCLK_IN : in std_logic; @@ -47,7 +46,6 @@ component nXyter_FEE_board REGIO_NO_MORE_DATA_OUT : out std_logic; REGIO_UNKNOWN_ADDR_OUT : out std_logic; - CLK_128_IN : in std_logic; DEBUG_LINE_OUT : out std_logic_vector(15 downto 0) ); end component; @@ -250,6 +248,40 @@ component clock10MHz ); end component; +component fifo_32to32_dc + port ( + Data : in std_logic_vector(31 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + AmEmptyThresh : in std_logic_vector(5 downto 0); + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic + ); +end component; + +component fifo_dc_8to32_dyn + port ( + Data : in std_logic_vector(7 downto 0); + WrClock : in std_logic; + RdClock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + RPReset : in std_logic; + AmEmptyThresh : in std_logic_vector(5 downto 0); + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostEmpty : out std_logic + ); +end component; + component fifo_dc_9to36_dyn port ( Data : in std_logic_vector(8 downto 0); @@ -271,10 +303,9 @@ component nx_timestamp_fifo_read port ( CLK_IN : in std_logic; RESET_IN : in std_logic; - NX_TIMESTAMP_CLK_IN : in std_logic; + NX_TIMESTAMP_CLK_IN : in std_logic; NX_TIMESTAMP_IN : in std_logic_vector (7 downto 0); - NX_FRAME_CLOCK_OUT : out std_logic; NX_TIMESTAMP_OUT : out std_logic_vector(31 downto 0); NX_NEW_TIMESTAMP_OUT : out std_logic; @@ -413,6 +444,21 @@ component pll_nx_clk256 LOCK : out std_logic); end component; +component pll_nx_clk250 + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic); +end component; + +component pll_adc_clk3125 + port ( + CLK : in std_logic; + CLKOP : out std_logic; + LOCK : out std_logic + ); +end component; + component nx_fpga_timestamp port ( CLK_IN : in std_logic; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index bbae5cb..8a73412 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -36,11 +36,18 @@ -- Timestamp Fifo 0x8500 : r current FIFO value -0x8501 : r/w r: FIFO Status ...... - w: trigger resync -0x8502 : r/w r: get resync counter(8bit) - w: clear resync counter -0x8503 : r/w FIFO Delay, i.e. Trigger Delay (6bit, in 3.1ns, range 2 .. 60) +0x8501 : r/w r: FIFO Status + 0: fifo_full + 1: fifo_empty + 2: fifo_almost_empty + 4..29: ignore + 31: nx_frame_synced + w: pll reset +0x8502 : r/w r: Resync Counter(12bit) + w: clear Resync Counter +0x8503 : r/w r: Parity Error Counter (12bit) + w: clear Parity Error Counter +0x8504 : r/w FIFO Delay, i.e. Trigger Delay (6bit, in 3.1ns, range 2 .. 60) -- Data Buffer 0x8600 : r read FIFO buffer diff --git a/nxyter/trb3_periph.prj b/nxyter/trb3_periph.prj index a7be974..c563fd9 100644 --- a/nxyter/trb3_periph.prj +++ b/nxyter/trb3_periph.prj @@ -137,9 +137,14 @@ add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_1_125_int.v add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" -add_file -vhdl -lib "work" "cores/nxyter_input_pll.vhd" add_file -vhdl -lib "work" "../base/cores/pll_in200_out100.vhd" +add_file -vhdl -lib "work" "cores/pll_nx_clk250.vhd" +add_file -vhdl -lib "work" "cores/pll_adc_clk3125.vhd" +add_file -vhdl -lib "work" "cores/fifo_32to32_dc.vhd" +add_file -vhdl -lib "work" "cores/fifo_dc_8to32_dyn.vhd" +add_file -vhdl -lib "work" "source/fifo_dc_9to36_dyn.vhd" + add_file -vhdl -lib "work" "trb3_periph.vhd" # nXyter Files @@ -151,7 +156,6 @@ add_file -vhdl -lib "work" "./source/nxyter.vhd" add_file -vhdl -lib "work" "./source/nxyter_data_handler.vhd" add_file -vhdl -lib "work" "./source/pll_nx_clk256.vhd" add_file -vhdl -lib "work" "./source/nxyter_registers.vhd" -add_file -vhdl -lib "work" "./source/fifo_dc_9to36_dyn.vhd" add_file -vhdl -lib "work" "./source/nx_timestamp_fifo_read.vhd" add_file -vhdl -lib "work" "./source/level_to_pulse.vhd" add_file -vhdl -lib "work" "./source/gray_decoder.vhd" @@ -177,7 +181,6 @@ add_file -vhdl -lib "work" "./source/nx_trigger_generator.vhd" add_file -vhdl -lib "work" "./source/nx_trigger_handler.vhd" add_file -vhdl -lib "work" "./source/nx_timestamp_sim.vhd" - # Needed by ADC9222 Entity add_file -vhdl -lib "work" "../base/cores/dqsinput.vhd" add_file -vhdl -lib "work" "../base/cores/dqsinput1x4.vhd" diff --git a/nxyter/trb3_periph.vhd b/nxyter/trb3_periph.vhd index 919e241..83987e5 100644 --- a/nxyter/trb3_periph.vhd +++ b/nxyter/trb3_periph.vhd @@ -9,12 +9,15 @@ use work.trb3_components.all; use work.version.all; use work.nxyter_components.all; +library ecp3; +use ecp3.components.all; + entity trb3_periph is port( --Clocks - CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz CLK_GPLL_RIGHT : in std_logic; --Clock Manager 2/(2468), 200 MHz <-- MAIN CLOCK for FPGA + CLK_GPLL_LEFT : in std_logic; --Clock Manager 1/(2468), 125 MHz CLK_PCLK_LEFT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! CLK_PCLK_RIGHT : in std_logic; --Clock Fan-out, 200/400 MHz <-- For TDC. Same oscillator as GPLL right! --Trigger @@ -122,12 +125,14 @@ entity trb3_periph is attribute syn_useioff of FPGA5_COMM : signal is true; attribute syn_useioff of TEST_LINE : signal is true; --attribute syn_useioff of INP : signal is false; - --attribute syn_useioff of SPARE_LINE : signal is true; + attribute syn_useioff of NX1_TIMESTAMP_IN : signal is true; + attribute syn_useioff of NX2_TIMESTAMP_IN : signal is true; --attribute syn_useioff of DAC_SDO : signal is true; --attribute syn_useioff of DAC_SDI : signal is true; --attribute syn_useioff of DAC_SCK : signal is true; --attribute syn_useioff of DAC_CS : signal is true; + end entity; @@ -139,6 +144,11 @@ architecture trb3_periph_arch of trb3_periph is attribute syn_keep : boolean; attribute syn_preserve : boolean; + -- For 250MHz PLL nxyter clock, THE_256M_ODDR_1 + attribute ODDRAPPS : string; + attribute ODDRAPPS of THE_256M_ODDR_1 : label is "SCLK_ALIGNED"; + + --Clock / Reset signal clk_100_i : std_logic; --clock for main logic, 100 MHz, via Clock Manager and internal PLL signal clk_200_i : std_logic; --clock for logic at 200 MHz, via Clock Manager and bypassed PLL @@ -267,7 +277,9 @@ architecture trb3_periph_arch of trb3_periph is signal nx1_timestamp_sim_o : std_logic_vector(7 downto 0); signal nx1_clk128_sim_o : std_logic; - -- nXyter 1 Regio Bus + signal nx1_clk256_o : std_logic; + + -- nXyter 2 Regio Bus signal nx2_regio_addr_in : std_logic_vector (15 downto 0); signal nx2_regio_data_in : std_logic_vector (31 downto 0); signal nx2_regio_data_out : std_logic_vector (31 downto 0); @@ -279,6 +291,8 @@ architecture trb3_periph_arch of trb3_periph is signal nx2_regio_no_more_data_out : std_logic; signal nx2_regio_unknown_addr_out : std_logic; + signal nx2_clk256_o : std_logic; + begin --------------------------------------------------------------------------- -- Reset Generation @@ -635,7 +649,6 @@ begin LED_RED <= timing_trg_received_i; LED_YELLOW <= not med_stat_op(11); - ------------------------------------------------------------------------------- -- nXyter Data Handler ------------------------------------------------------------------------------- @@ -684,7 +697,7 @@ begin port map ( CLK_IN => clk_100_i, RESET_IN => reset_i, - + I2C_SDA_INOUT => NX1_I2C_SDA_INOUT, I2C_SCL_INOUT => NX1_I2C_SCL_INOUT, I2C_SM_RESET_OUT => NX1_I2C_SM_RESET_OUT, @@ -700,7 +713,6 @@ begin -- NX_TIMESTAMP_IN => nx1_timestamp_sim_o, NX_RESET_OUT => NX1_RESET_OUT, - NX_CLK256A_OUT => NX1_CLK256A_OUT, NX_TESTPULSE_OUT => NX1_TESTPULSE_OUT, ADC_FCLK_IN => NX1_ADC_FCLK_IN, @@ -722,29 +734,54 @@ begin REGIO_NO_MORE_DATA_OUT => nx1_regio_no_more_data_out, REGIO_UNKNOWN_ADDR_OUT => nx1_regio_unknown_addr_out, - CLK_128_IN => CLK_GPLL_LEFT, DEBUG_LINE_OUT => TEST_LINE -- DEBUG_LINE_OUT => open ); + + pll_nx_clk256_1: pll_nx_clk256 + port map ( + CLK => clk_100_i, + CLKOP => NX1_CLK256A_OUT, + LOCK => open + ); + +-- -- 250MHz Clock to nXyters +-- pll_nx_clk250_1: pll_nx_clk250 +-- port map ( +-- CLK => CLK_GPLL_LEFT, +-- CLKOP => NX1_CLK256A_OUT, -- nx1_clk256_o, +-- LOCK => open +-- ); + + THE_256M_ODDR_1: ODDRXD1 + port map( + SCLK => nx1_clk256_o, + DA => '1', + DB => '0', + Q => open --NX1_CLK256A_OUT + ); + + ------------------------------------------------------------------------------- -- Timestamp Simulator ------------------------------------------------------------------------------- - nxyter_timestamp_sim_1: nxyter_timestamp_sim - port map ( - CLK_IN => CLK_GPLL_LEFT, - RESET_IN => reset_i, - TIMESTAMP_OUT => nx1_timestamp_sim_o, - CLK128_OUT => nx1_clk128_sim_o - ); +-- nxyter_timestamp_sim_1: nxyter_timestamp_sim +-- port map ( +-- CLK_IN => CLK_GPLL_LEFT, +-- RESET_IN => reset_i, +-- TIMESTAMP_OUT => nx1_timestamp_sim_o, +-- CLK128_OUT => nx1_clk128_sim_o +-- ); --------------------------------------------------------------------------- -- Test Connector - Logic Analyser --------------------------------------------------------------------------- - - -- TEST_LINE(15 downto 0) <= (others => '0'); + -- TEST_LINE(0) <= clk_100_i; + -- TEST_LINE(1) <= NX1_CLK128_IN; + -- TEST_LINE(15 downto 2) <= (others => '0'); end architecture; diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 51a39c1..11058a3 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -10,8 +10,10 @@ FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; - FREQUENCY PORT CLK_GPLL_RIGHT 125 MHz; - FREQUENCY PORT CLK_GPLL_LEFT 200 MHz; + FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; + FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; + + FREQUENCY PORT NX1_CLK256A_OUT 250 MHz; #Put the names of your nxyter inputs here: FREQUENCY PORT NX1_ADC_DCLK_IN 192 MHz; @@ -54,15 +56,15 @@ MULTICYCLE TO CELL "THE_ADC/restart_i" 20 ns; # Constraints for nxyter inputs ################################################################# -USE PRIMARY NET "*nx_clk_in_delayed"; -DEFINE PORT GROUP "NX_IN" "NX1_TIMESTAMP_*"; -INPUT_SETUP GROUP "NX_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ; - +# look at .par and .twr.setup file for clocks +# and .mrp or errors +PROHIBIT PRIMARY NET "NX1_CLK128_IN_c"; +PROHIBIT SECONDARY NET "NX1_CLK128_IN_c"; +PROHIBIT PRIMARY NET "TEST_LINE_c_0"; +PROHIBIT SECONDARY NET "TEST_LINE_c_0"; -#DEFINE PORT GROUP "ADC7_INPUTS" "PRE_IN_17" "PRE_IN_18" "PRE_IN_19" -# "PRE_IN_20" "PRE_IN_21" "PRE_IN_22" "PRE_IN_23" "PRE_IN_24" ; -#INPUT_SETUP GROUP "ADC7_INPUTS" 1.500000 ns HOLD 1.500000 ns CLKPORT "DCO_IN_7" ; - +DEFINE PORT GROUP "NX_IN" "NX1_TIMESTAMP_*"; +INPUT_SETUP GROUP "NX_IN" 3.0 ns HOLD 3.0 ns CLKPORT="NX1_CLK128_IN" ; MULTICYCLE FROM CLKNET "NX1_CLK256A_OUT_c_c" 50 ns; diff --git a/nxyter/version.vhd b/nxyter/version.vhd index e4dd338..35fd798 100644 --- a/nxyter/version.vhd +++ b/nxyter/version.vhd @@ -8,6 +8,6 @@ use ieee.numeric_std.all; package version is - constant VERSION_NUMBER_TIME : integer := 1365031432; + constant VERSION_NUMBER_TIME : integer := 1365511005; end package version; -- 2.43.0