From 4ec7e4545f82da0a452803557d97551f43b07286 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Thu, 10 Jan 2019 18:06:08 +0100 Subject: [PATCH] update TDC template to handle more than 48 channels --- tdctemplate/config_48_crate_4conn.vhd | 1 + tdctemplate/trb3sc_tdctemplate.vhd | 6 +++--- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/tdctemplate/config_48_crate_4conn.vhd b/tdctemplate/config_48_crate_4conn.vhd index 43522d0..33b672a 100644 --- a/tdctemplate/config_48_crate_4conn.vhd +++ b/tdctemplate/config_48_crate_4conn.vhd @@ -38,6 +38,7 @@ package config is --Runs with 120 MHz instead of 100 MHz constant USE_120_MHZ : integer := c_NO; constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_CALIBRATION_200MHZ : integer := c_NO; constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? diff --git a/tdctemplate/trb3sc_tdctemplate.vhd b/tdctemplate/trb3sc_tdctemplate.vhd index fa12ed3..6b8b743 100644 --- a/tdctemplate/trb3sc_tdctemplate.vhd +++ b/tdctemplate/trb3sc_tdctemplate.vhd @@ -113,7 +113,7 @@ architecture trb3sc_arch of trb3sc_tdctemplate is signal time_counter : unsigned(31 downto 0) := (others => '0'); signal led : std_logic_vector(1 downto 0); signal debug_clock_reset : std_logic_vector(31 downto 0); - signal inputs : std_logic_vector(51 downto 0); + signal inputs : std_logic_vector(67 downto 0); signal monitor_inputs_i : std_logic_vector(MONITOR_INPUT_NUM-1 downto 0); signal trigger_inputs_i : std_logic_vector(TRIG_GEN_INPUT_NUM-1 downto 0); @@ -416,8 +416,8 @@ gen_32pin : if PINOUT = 0 generate end generate; gen_4conn : if PINOUT = 1 generate - inputs(47 downto 0) <= INP(47 downto 0); - inputs(51 downto 48) <= trig_gen_out_i; + inputs(63 downto 0) <= INP(63 downto 0); + inputs(67 downto 64) <= trig_gen_out_i; spi_miso(3 downto 0) <= DAC_IN_SDI(4 downto 1); DAC_OUT_SCK(4 downto 1) <= spi_clk(3 downto 0); -- 2.43.0