From 4f17e213fdac64b8a174744757322ef293f61a36 Mon Sep 17 00:00:00 2001 From: hadaq Date: Sat, 19 Nov 2011 23:04:27 +0000 Subject: [PATCH] new error handling --- libtrbnet/trberror.c | 10 ++++-- libtrbnet/trberror.h | 6 +++- libtrbnet/trbnet.c | 85 ++++++++++++++++++++++++++++++-------------- 3 files changed, 70 insertions(+), 31 deletions(-) diff --git a/libtrbnet/trberror.c b/libtrbnet/trberror.c index 305303d..755aebf 100644 --- a/libtrbnet/trberror.c +++ b/libtrbnet/trberror.c @@ -74,11 +74,15 @@ const char* trb_errorstr(int trberrno) "FIFO Shared Memory Error", "Termination Status Warning", "RPC Error", - "Pexor DMA Error", - "Pexor Device Error ioctl call" + "Pexor DMA Error, Kernel fatal, call SysAdmin", + "Pexor Device Error ioctl call, Kernel Fatal, call SysAdmin", + "Pexor Device Error ioctl call, TRBNet Timeout", + "Pexor Device Error ioctl call, DMA Polling Timeout", + "Pexor Device Error ioctl call, Out of DMA buffers", + "Pexor Device Error ioctl call, Invalid DMA Size" }; - if (trberrno < 30) { + if (trberrno < 34) { return errorstring[trberrno]; } else { return "Unknown Error"; diff --git a/libtrbnet/trberror.h b/libtrbnet/trberror.h index 78e5e0c..64c7b6b 100644 --- a/libtrbnet/trberror.h +++ b/libtrbnet/trberror.h @@ -37,7 +37,11 @@ typedef enum { TRB_STATUS_WARNING = 26, TRB_RPC_ERROR = 27, TRB_PEXOR_DMA_ERROR = 28, - TRB_PEXOR_DEVICE_ERROR = 29 + TRB_PEXOR_DEVICE_ERROR = 29, + TRB_PEXOR_DEVICE_TRB_TIMEOUT = 30, + TRB_PEXOR_DEVICE_POLLING_TIMEOUT = 31, + TRB_PEXOR_DEVICE_DMA_EMPTY = 32, + TRB_PEXOR_DEVICE_INVALID_DMA_SIZE = 33 } TRB_ERROR; /* last TRBNet-TermPackage */ diff --git a/libtrbnet/trbnet.c b/libtrbnet/trbnet.c index 64d72fa..06ea2b6 100644 --- a/libtrbnet/trbnet.c +++ b/libtrbnet/trbnet.c @@ -1,4 +1,4 @@ -const char trbnet_version[] = "$Revision: 4.12 $ Local"; +const char trbnet_version[] = "$Revision: 4.13 $ Local"; #include #include @@ -260,7 +260,34 @@ static inline void com_reset_FPGA() #else /* PEXOR */ -static inline int write32_to_FPGA(uint32_t address, uint32_t value) +static int pexor_to_trb_error(int error) +{ + switch (error) { + case -129: + return TRB_PEXOR_DEVICE_ERROR; + break; + + case -130: + return TRB_PEXOR_DEVICE_TRB_TIMEOUT; + break; + + case -131: + return TRB_PEXOR_DEVICE_POLLING_TIMEOUT; + break; + + case -132: + return TRB_PEXOR_DEVICE_DMA_EMPTY; + break; + + case -133: + return TRB_PEXOR_DEVICE_INVALID_DMA_SIZE; + break; + } + + return TRB_PEXOR_DEVICE_ERROR; +} + +static int write32_to_FPGA(uint32_t address, uint32_t value) { struct pexor_reg_io descriptor; int status = 0; @@ -276,7 +303,7 @@ static inline int write32_to_FPGA(uint32_t address, uint32_t value) status = ioctl(pexorFileHandle, PEXOR_IOC_WRITE_REGISTER, &descriptor); if(status == -1) { - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } @@ -299,7 +326,7 @@ static inline int read32_from_FPGA(uint32_t address, uint32_t* value) status = ioctl(pexorFileHandle, PEXOR_IOC_READ_REGISTER, &descriptor); if(status == -1) { - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } @@ -429,7 +456,8 @@ static void fifo_flush(uint8_t channel) unsigned int timeout = 0; do { read32_from_FPGA(fifoAddress, &tmp); - } while (((tmp & MASK_FIFO_VALID) == 0) && (++timeout < 10/*MAX_TIMEOUT*/)); + } while (((tmp & MASK_FIFO_VALID) == 0) && + (++timeout < 10/*MAX_TIMEOUT*/)); /* DEBUG INFO */ if ((trb_debug > 1) && ((tmp & MASK_FIFO_VALID) != 0)) { fprintf(stderr, "FLUSH_FIFO_%03d: 0x%08x\n", counter, tmp); @@ -448,19 +476,23 @@ static int trb_init_transfer(uint8_t channel) } /* Check for TX not Busy */ -#ifdef ETRAX read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); if (tmp != 0) { +#ifdef ETRAX /* FIFO_TOGGLE_BIT-BUG Workaround */ com_reset_FPGA(); +#else + /* First try to resolve it by flushing the fifo */ + fifo_flush(channel); +#endif + /* Try again */ + read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); + if (tmp != 0) { + trb_errno = TRB_TX_BUSY; + return -1; + } } -#endif - read32_from_FPGA(CHANNEL_N_SENDER_STATUS | ((channel * 2 + 1) << 4), &tmp); - if (tmp != 0) { - trb_errno = TRB_TX_BUSY; - return -1; - } - + /* Check receiver FIFO empty */ #ifdef ETRAX read32_from_FPGA(CHANNEL_N_RECEIVER_FIFO_STATUS | ((channel * 2 + 1) << 4), @@ -1431,7 +1463,7 @@ int trb_register_read(uint16_t trb_address, if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1496,7 +1528,7 @@ int trb_registertime_read(uint16_t trb_address, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1574,7 +1606,7 @@ int trb_register_read_mem(uint16_t trb_address, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1663,7 +1695,7 @@ int trb_registertime_read_mem(uint16_t trb_address, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1740,7 +1772,7 @@ int trb_register_write(uint16_t trb_address, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1820,9 +1852,8 @@ int trb_register_write_mem(uint16_t trb_address, /* Send command to pexor driver */ if (write(pexorFileHandle, (void*)(data + ctr), len * 4) != len * 4) { - trb_errno = TRB_PEXOR_DEVICE_ERROR; unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } @@ -1842,7 +1873,7 @@ int trb_register_write_mem(uint16_t trb_address, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1902,7 +1933,7 @@ int trb_read_uid(uint16_t trb_address, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -1978,7 +2009,7 @@ int trb_set_address(uint64_t uid, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -2050,7 +2081,7 @@ int trb_ipu_data_read(uint8_t type, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -2120,7 +2151,7 @@ int trb_send_trigger(uint8_t type, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -2193,7 +2224,7 @@ int trb_send_trigger_rich(uint8_t trg_input, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; @@ -2230,7 +2261,7 @@ int trb_send_trigger_rich(uint8_t trg_input, &pexorDescriptor); if (status < 0) { unlockPorts(0); - trb_errno = TRB_PEXOR_DEVICE_ERROR; + trb_errno = pexor_to_trb_error(status); return -1; } dataBufferSize = status; -- 2.43.0