From 4f2b7bc38ea85b63c454261e5588d541d72f07d2 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Thu, 6 Aug 2009 15:01:08 +0000 Subject: [PATCH] *** empty log message *** --- lattice/ecp2m/fifo_dualclock_width_16_reg.lpc | 47 + lattice/ecp2m/fifo_dualclock_width_16_reg.vhd | 1399 +++++++++++++++++ lattice/ecp2m/pll_in100_out100.lpc | 56 + lattice/ecp2m/pll_in100_out100.vhd | 120 ++ lattice/ecp2m/pll_in100_out200.vhd | 120 ++ media_interfaces/ecp2m_sfp/msg_file.log | 76 +- .../ecp2m_sfp/serdes_sfp_0_extclock.lpc | 140 ++ pinout/mdc_oep3.lpf | 2 + trb_net16_hub_ipu_logic.vhd | 20 +- trb_net16_med_tlk.vhd | 403 ++--- trb_net16_regIO.vhd | 2 +- 11 files changed, 2129 insertions(+), 256 deletions(-) create mode 100644 lattice/ecp2m/fifo_dualclock_width_16_reg.lpc create mode 100644 lattice/ecp2m/fifo_dualclock_width_16_reg.vhd create mode 100644 lattice/ecp2m/pll_in100_out100.lpc create mode 100644 lattice/ecp2m/pll_in100_out100.vhd create mode 100644 lattice/ecp2m/pll_in100_out200.vhd create mode 100644 media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.lpc diff --git a/lattice/ecp2m/fifo_dualclock_width_16_reg.lpc b/lattice/ecp2m/fifo_dualclock_width_16_reg.lpc new file mode 100644 index 0000000..8f1ea61 --- /dev/null +++ b/lattice/ecp2m/fifo_dualclock_width_16_reg.lpc @@ -0,0 +1,47 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=FIFO_DC +CoreRevision=5.2 +ModuleName=fifo_dualclock_width_16_reg +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=07/29/2009 +Time=18:43:03 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +FIFOImp=EBR Based +Depth=64 +Width=18 +RDepth=64 +RWidth=18 +regout=1 +CtrlByRdEn=0 +EmpFlg=0 +PeMode=Static - Dual Threshold +PeAssert=10 +PeDeassert=12 +FullFlg=0 +PfMode=Static - Dual Threshold +PfAssert=508 +PfDeassert=506 +RDataCount=0 +WDataCount=0 +EnECC=0 diff --git a/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd b/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd new file mode 100644 index 0000000..75a3fc0 --- /dev/null +++ b/lattice/ecp2m/fifo_dualclock_width_16_reg.vhd @@ -0,0 +1,1399 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.2 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type ebfifo -depth 64 -width 18 -depth 64 -rdata_width 18 -regout -no_enable -pe -1 -pf -1 -e + +-- Wed Jul 29 18:43:04 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity fifo_dualclock_width_16_reg is + port ( + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic); +end fifo_dualclock_width_16_reg; + +architecture Structure of fifo_dualclock_width_16_reg is + + -- internal signal declarations + signal invout_1: std_logic; + signal invout_0: std_logic; + signal w_gdata_0: std_logic; + signal w_gdata_1: std_logic; + signal w_gdata_2: std_logic; + signal w_gdata_3: std_logic; + signal w_gdata_4: std_logic; + signal w_gdata_5: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal r_gdata_0: std_logic; + signal r_gdata_1: std_logic; + signal r_gdata_2: std_logic; + signal r_gdata_3: std_logic; + signal r_gdata_4: std_logic; + signal r_gdata_5: std_logic; + signal rptr_0: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal ffidata_0: std_logic; + signal ffidata_1: std_logic; + signal ffidata_2: std_logic; + signal ffidata_3: std_logic; + signal ffidata_4: std_logic; + signal ffidata_5: std_logic; + signal ffidata_6: std_logic; + signal ffidata_7: std_logic; + signal ffidata_8: std_logic; + signal ffidata_9: std_logic; + signal ffidata_10: std_logic; + signal ffidata_11: std_logic; + signal ffidata_12: std_logic; + signal ffidata_13: std_logic; + signal ffidata_14: std_logic; + signal ffidata_15: std_logic; + signal ffidata_16: std_logic; + signal ffidata_17: std_logic; + signal w_gcount_0: std_logic; + signal w_gcount_1: std_logic; + signal w_gcount_2: std_logic; + signal w_gcount_3: std_logic; + signal w_gcount_4: std_logic; + signal w_gcount_5: std_logic; + signal w_gcount_6: std_logic; + signal r_gcount_0: std_logic; + signal r_gcount_1: std_logic; + signal r_gcount_2: std_logic; + signal r_gcount_3: std_logic; + signal r_gcount_4: std_logic; + signal r_gcount_5: std_logic; + signal r_gcount_6: std_logic; + signal w_gcount_r20: std_logic; + signal w_gcount_r0: std_logic; + signal w_gcount_r21: std_logic; + signal w_gcount_r1: std_logic; + signal w_gcount_r22: std_logic; + signal w_gcount_r2: std_logic; + signal w_gcount_r23: std_logic; + signal w_gcount_r3: std_logic; + signal w_gcount_r24: std_logic; + signal w_gcount_r4: std_logic; + signal w_gcount_r25: std_logic; + signal w_gcount_r5: std_logic; + signal w_gcount_r26: std_logic; + signal w_gcount_r6: std_logic; + signal r_gcount_w20: std_logic; + signal r_gcount_w0: std_logic; + signal r_gcount_w21: std_logic; + signal r_gcount_w1: std_logic; + signal r_gcount_w22: std_logic; + signal r_gcount_w2: std_logic; + signal r_gcount_w23: std_logic; + signal r_gcount_w3: std_logic; + signal r_gcount_w24: std_logic; + signal r_gcount_w4: std_logic; + signal r_gcount_w25: std_logic; + signal r_gcount_w5: std_logic; + signal r_gcount_w26: std_logic; + signal r_gcount_w6: std_logic; + signal empty_i: std_logic; + signal rRst: std_logic; + signal full_i: std_logic; + signal iwcount_0: std_logic; + signal iwcount_1: std_logic; + signal w_gctr_ci: std_logic; + signal iwcount_2: std_logic; + signal iwcount_3: std_logic; + signal co0: std_logic; + signal iwcount_4: std_logic; + signal iwcount_5: std_logic; + signal co1: std_logic; + signal iwcount_6: std_logic; + signal co3: std_logic; + signal wcount_6: std_logic; + signal co2: std_logic; + signal scuba_vhi: std_logic; + signal ircount_0: std_logic; + signal ircount_1: std_logic; + signal r_gctr_ci: std_logic; + signal ircount_2: std_logic; + signal ircount_3: std_logic; + signal co0_1: std_logic; + signal ircount_4: std_logic; + signal ircount_5: std_logic; + signal co1_1: std_logic; + signal ircount_6: std_logic; + signal co3_1: std_logic; + signal rcount_6: std_logic; + signal co2_1: std_logic; + signal rden_i: std_logic; + signal cmp_ci: std_logic; + signal wcount_r0: std_logic; + signal wcount_r1: std_logic; + signal rcount_0: std_logic; + signal rcount_1: std_logic; + signal co0_2: std_logic; + signal wcount_r2: std_logic; + signal w_g2b_xor_cluster_0: std_logic; + signal rcount_2: std_logic; + signal rcount_3: std_logic; + signal co1_2: std_logic; + signal wcount_r4: std_logic; + signal wcount_r5: std_logic; + signal rcount_4: std_logic; + signal rcount_5: std_logic; + signal co2_2: std_logic; + signal empty_cmp_clr: std_logic; + signal empty_cmp_set: std_logic; + signal empty_d: std_logic; + signal empty_d_c: std_logic; + signal wren_i: std_logic; + signal cmp_ci_1: std_logic; + signal rcount_w0: std_logic; + signal rcount_w1: std_logic; + signal wcount_0: std_logic; + signal wcount_1: std_logic; + signal co0_3: std_logic; + signal rcount_w2: std_logic; + signal r_g2b_xor_cluster_0: std_logic; + signal wcount_2: std_logic; + signal wcount_3: std_logic; + signal co1_3: std_logic; + signal rcount_w4: std_logic; + signal rcount_w5: std_logic; + signal wcount_4: std_logic; + signal wcount_5: std_logic; + signal co2_3: std_logic; + signal full_cmp_clr: std_logic; + signal full_cmp_set: std_logic; + signal full_d: std_logic; + signal full_d_c: std_logic; + signal scuba_vlo: std_logic; + + -- local component declarations + component AGEB2 + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; GE: out std_logic); + end component; + component AND2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component CU2 + port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic; + CO: out std_logic; NC0: out std_logic; NC1: out std_logic); + end component; + component FADD2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; CI: in std_logic; COUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; + component FD1P3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + CD: in std_logic; Q: out std_logic); + end component; + component FD1S3BX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; PD: in std_logic; + Q: out std_logic); + end component; + component FD1S3DX + -- synopsys translate_off + generic (GSR : in String); + -- synopsys translate_on + port (D: in std_logic; CK: in std_logic; CD: in std_logic; + Q: out std_logic); + end component; + component INV + port (A: in std_logic; Z: out std_logic); + end component; + component OR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component ROM16X1 + -- synopsys translate_off + generic (initval : in String); + -- synopsys translate_on + port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic; + AD0: in std_logic; DO0: out std_logic); + end component; + component VHI + port (Z: out std_logic); + end component; + component VLO + port (Z: out std_logic); + end component; + component XOR2 + port (A: in std_logic; B: in std_logic; Z: out std_logic); + end component; + component DP16KB + -- synopsys translate_off + generic (GSR : in String; WRITEMODE_B : in String; + CSDECODE_B : in std_logic_vector(2 downto 0); + CSDECODE_A : in std_logic_vector(2 downto 0); + WRITEMODE_A : in String; RESETMODE : in String; + REGMODE_B : in String; REGMODE_A : in String; + DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer); + -- synopsys translate_on + port (DIA0: in std_logic; DIA1: in std_logic; + DIA2: in std_logic; DIA3: in std_logic; + DIA4: in std_logic; DIA5: in std_logic; + DIA6: in std_logic; DIA7: in std_logic; + DIA8: in std_logic; DIA9: in std_logic; + DIA10: in std_logic; DIA11: in std_logic; + DIA12: in std_logic; DIA13: in std_logic; + DIA14: in std_logic; DIA15: in std_logic; + DIA16: in std_logic; DIA17: in std_logic; + ADA0: in std_logic; ADA1: in std_logic; + ADA2: in std_logic; ADA3: in std_logic; + ADA4: in std_logic; ADA5: in std_logic; + ADA6: in std_logic; ADA7: in std_logic; + ADA8: in std_logic; ADA9: in std_logic; + ADA10: in std_logic; ADA11: in std_logic; + ADA12: in std_logic; ADA13: in std_logic; + CEA: in std_logic; CLKA: in std_logic; WEA: in std_logic; + CSA0: in std_logic; CSA1: in std_logic; + CSA2: in std_logic; RSTA: in std_logic; + DIB0: in std_logic; DIB1: in std_logic; + DIB2: in std_logic; DIB3: in std_logic; + DIB4: in std_logic; DIB5: in std_logic; + DIB6: in std_logic; DIB7: in std_logic; + DIB8: in std_logic; DIB9: in std_logic; + DIB10: in std_logic; DIB11: in std_logic; + DIB12: in std_logic; DIB13: in std_logic; + DIB14: in std_logic; DIB15: in std_logic; + DIB16: in std_logic; DIB17: in std_logic; + ADB0: in std_logic; ADB1: in std_logic; + ADB2: in std_logic; ADB3: in std_logic; + ADB4: in std_logic; ADB5: in std_logic; + ADB6: in std_logic; ADB7: in std_logic; + ADB8: in std_logic; ADB9: in std_logic; + ADB10: in std_logic; ADB11: in std_logic; + ADB12: in std_logic; ADB13: in std_logic; + CEB: in std_logic; CLKB: in std_logic; WEB: in std_logic; + CSB0: in std_logic; CSB1: in std_logic; + CSB2: in std_logic; RSTB: in std_logic; + DOA0: out std_logic; DOA1: out std_logic; + DOA2: out std_logic; DOA3: out std_logic; + DOA4: out std_logic; DOA5: out std_logic; + DOA6: out std_logic; DOA7: out std_logic; + DOA8: out std_logic; DOA9: out std_logic; + DOA10: out std_logic; DOA11: out std_logic; + DOA12: out std_logic; DOA13: out std_logic; + DOA14: out std_logic; DOA15: out std_logic; + DOA16: out std_logic; DOA17: out std_logic; + DOB0: out std_logic; DOB1: out std_logic; + DOB2: out std_logic; DOB3: out std_logic; + DOB4: out std_logic; DOB5: out std_logic; + DOB6: out std_logic; DOB7: out std_logic; + DOB8: out std_logic; DOB9: out std_logic; + DOB10: out std_logic; DOB11: out std_logic; + DOB12: out std_logic; DOB13: out std_logic; + DOB14: out std_logic; DOB15: out std_logic; + DOB16: out std_logic; DOB17: out std_logic); + end component; + attribute initval : string; + attribute MEM_LPC_FILE : string; + attribute MEM_INIT_FILE : string; + attribute CSDECODE_B : string; + attribute CSDECODE_A : string; + attribute WRITEMODE_B : string; + attribute WRITEMODE_A : string; + attribute RESETMODE : string; + attribute REGMODE_B : string; + attribute REGMODE_A : string; + attribute DATA_WIDTH_B : string; + attribute DATA_WIDTH_A : string; + attribute GSR : string; + attribute initval of LUT4_15 : label is "0x6996"; + attribute initval of LUT4_14 : label is "0x6996"; + attribute initval of LUT4_13 : label is "0x6996"; + attribute initval of LUT4_12 : label is "0x6996"; + attribute initval of LUT4_11 : label is "0x6996"; + attribute initval of LUT4_10 : label is "0x6996"; + attribute initval of LUT4_9 : label is "0x6996"; + attribute initval of LUT4_8 : label is "0x6996"; + attribute initval of LUT4_7 : label is "0x6996"; + attribute initval of LUT4_6 : label is "0x6996"; + attribute initval of LUT4_5 : label is "0x6996"; + attribute initval of LUT4_4 : label is "0x6996"; + attribute initval of LUT4_3 : label is "0x0410"; + attribute initval of LUT4_2 : label is "0x1004"; + attribute initval of LUT4_1 : label is "0x0140"; + attribute initval of LUT4_0 : label is "0x4001"; + attribute MEM_LPC_FILE of pdp_ram_0_0_0 : label is "fifo_dualclock_width_16_reg.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_0 : label is ""; + attribute CSDECODE_B of pdp_ram_0_0_0 : label is "0b000"; + attribute CSDECODE_A of pdp_ram_0_0_0 : label is "0b000"; + attribute WRITEMODE_B of pdp_ram_0_0_0 : label is "NORMAL"; + attribute WRITEMODE_A of pdp_ram_0_0_0 : label is "NORMAL"; + attribute GSR of pdp_ram_0_0_0 : label is "DISABLED"; + attribute RESETMODE of pdp_ram_0_0_0 : label is "ASYNC"; + attribute REGMODE_B of pdp_ram_0_0_0 : label is "NOREG"; + attribute REGMODE_A of pdp_ram_0_0_0 : label is "NOREG"; + attribute DATA_WIDTH_B of pdp_ram_0_0_0 : label is "18"; + attribute DATA_WIDTH_A of pdp_ram_0_0_0 : label is "18"; + attribute GSR of FF_89 : label is "ENABLED"; + attribute GSR of FF_88 : label is "ENABLED"; + attribute GSR of FF_87 : label is "ENABLED"; + attribute GSR of FF_86 : label is "ENABLED"; + attribute GSR of FF_85 : label is "ENABLED"; + attribute GSR of FF_84 : label is "ENABLED"; + attribute GSR of FF_83 : label is "ENABLED"; + attribute GSR of FF_82 : label is "ENABLED"; + attribute GSR of FF_81 : label is "ENABLED"; + attribute GSR of FF_80 : label is "ENABLED"; + attribute GSR of FF_79 : label is "ENABLED"; + attribute GSR of FF_78 : label is "ENABLED"; + attribute GSR of FF_77 : label is "ENABLED"; + attribute GSR of FF_76 : label is "ENABLED"; + attribute GSR of FF_75 : label is "ENABLED"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; + attribute GSR of FF_35 : label is "ENABLED"; + attribute GSR of FF_34 : label is "ENABLED"; + attribute GSR of FF_33 : label is "ENABLED"; + attribute GSR of FF_32 : label is "ENABLED"; + attribute GSR of FF_31 : label is "ENABLED"; + attribute GSR of FF_30 : label is "ENABLED"; + attribute GSR of FF_29 : label is "ENABLED"; + attribute GSR of FF_28 : label is "ENABLED"; + attribute GSR of FF_27 : label is "ENABLED"; + attribute GSR of FF_26 : label is "ENABLED"; + attribute GSR of FF_25 : label is "ENABLED"; + attribute GSR of FF_24 : label is "ENABLED"; + attribute GSR of FF_23 : label is "ENABLED"; + attribute GSR of FF_22 : label is "ENABLED"; + attribute GSR of FF_21 : label is "ENABLED"; + attribute GSR of FF_20 : label is "ENABLED"; + attribute GSR of FF_19 : label is "ENABLED"; + attribute GSR of FF_18 : label is "ENABLED"; + attribute GSR of FF_17 : label is "ENABLED"; + attribute GSR of FF_16 : label is "ENABLED"; + attribute GSR of FF_15 : label is "ENABLED"; + attribute GSR of FF_14 : label is "ENABLED"; + attribute GSR of FF_13 : label is "ENABLED"; + attribute GSR of FF_12 : label is "ENABLED"; + attribute GSR of FF_11 : label is "ENABLED"; + attribute GSR of FF_10 : label is "ENABLED"; + attribute GSR of FF_9 : label is "ENABLED"; + attribute GSR of FF_8 : label is "ENABLED"; + attribute GSR of FF_7 : label is "ENABLED"; + attribute GSR of FF_6 : label is "ENABLED"; + attribute GSR of FF_5 : label is "ENABLED"; + attribute GSR of FF_4 : label is "ENABLED"; + attribute GSR of FF_3 : label is "ENABLED"; + attribute GSR of FF_2 : label is "ENABLED"; + attribute GSR of FF_1 : label is "ENABLED"; + attribute GSR of FF_0 : label is "ENABLED"; + attribute syn_keep : boolean; + +begin + -- component instantiation statements + AND2_t14: AND2 + port map (A=>WrEn, B=>invout_1, Z=>wren_i); + + INV_1: INV + port map (A=>full_i, Z=>invout_1); + + AND2_t13: AND2 + port map (A=>RdEn, B=>invout_0, Z=>rden_i); + + INV_0: INV + port map (A=>empty_i, Z=>invout_0); + + OR2_t12: OR2 + port map (A=>Reset, B=>RPReset, Z=>rRst); + + XOR2_t11: XOR2 + port map (A=>wcount_0, B=>wcount_1, Z=>w_gdata_0); + + XOR2_t10: XOR2 + port map (A=>wcount_1, B=>wcount_2, Z=>w_gdata_1); + + XOR2_t9: XOR2 + port map (A=>wcount_2, B=>wcount_3, Z=>w_gdata_2); + + XOR2_t8: XOR2 + port map (A=>wcount_3, B=>wcount_4, Z=>w_gdata_3); + + XOR2_t7: XOR2 + port map (A=>wcount_4, B=>wcount_5, Z=>w_gdata_4); + + XOR2_t6: XOR2 + port map (A=>wcount_5, B=>wcount_6, Z=>w_gdata_5); + + XOR2_t5: XOR2 + port map (A=>rcount_0, B=>rcount_1, Z=>r_gdata_0); + + XOR2_t4: XOR2 + port map (A=>rcount_1, B=>rcount_2, Z=>r_gdata_1); + + XOR2_t3: XOR2 + port map (A=>rcount_2, B=>rcount_3, Z=>r_gdata_2); + + XOR2_t2: XOR2 + port map (A=>rcount_3, B=>rcount_4, Z=>r_gdata_3); + + XOR2_t1: XOR2 + port map (A=>rcount_4, B=>rcount_5, Z=>r_gdata_4); + + XOR2_t0: XOR2 + port map (A=>rcount_5, B=>rcount_6, Z=>r_gdata_5); + + LUT4_15: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r23, AD2=>w_gcount_r24, + AD1=>w_gcount_r25, AD0=>w_gcount_r26, + DO0=>w_g2b_xor_cluster_0); + + LUT4_14: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r25, AD2=>w_gcount_r26, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>wcount_r5); + + LUT4_13: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r24, AD2=>w_gcount_r25, + AD1=>w_gcount_r26, AD0=>scuba_vlo, DO0=>wcount_r4); + + LUT4_12: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r22, AD2=>w_gcount_r23, + AD1=>w_gcount_r24, AD0=>wcount_r5, DO0=>wcount_r2); + + LUT4_11: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r21, AD2=>w_gcount_r22, + AD1=>w_gcount_r23, AD0=>wcount_r4, DO0=>wcount_r1); + + LUT4_10: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>w_gcount_r20, AD2=>w_gcount_r21, + AD1=>w_gcount_r22, AD0=>w_g2b_xor_cluster_0, DO0=>wcount_r0); + + LUT4_9: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w23, AD2=>r_gcount_w24, + AD1=>r_gcount_w25, AD0=>r_gcount_w26, + DO0=>r_g2b_xor_cluster_0); + + LUT4_8: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w25, AD2=>r_gcount_w26, AD1=>scuba_vlo, + AD0=>scuba_vlo, DO0=>rcount_w5); + + LUT4_7: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w24, AD2=>r_gcount_w25, + AD1=>r_gcount_w26, AD0=>scuba_vlo, DO0=>rcount_w4); + + LUT4_6: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w22, AD2=>r_gcount_w23, + AD1=>r_gcount_w24, AD0=>rcount_w5, DO0=>rcount_w2); + + LUT4_5: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w21, AD2=>r_gcount_w22, + AD1=>r_gcount_w23, AD0=>rcount_w4, DO0=>rcount_w1); + + LUT4_4: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x6996") + -- synopsys translate_on + port map (AD3=>r_gcount_w20, AD2=>r_gcount_w21, + AD1=>r_gcount_w22, AD0=>r_g2b_xor_cluster_0, DO0=>rcount_w0); + + LUT4_3: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0410") + -- synopsys translate_on + port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, + AD0=>scuba_vlo, DO0=>empty_cmp_set); + + LUT4_2: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x1004") + -- synopsys translate_on + port map (AD3=>rptr_6, AD2=>rcount_6, AD1=>w_gcount_r26, + AD0=>scuba_vlo, DO0=>empty_cmp_clr); + + LUT4_1: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x0140") + -- synopsys translate_on + port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, + AD0=>scuba_vlo, DO0=>full_cmp_set); + + LUT4_0: ROM16X1 + -- synopsys translate_off + generic map (initval=> "0x4001") + -- synopsys translate_on + port map (AD3=>wptr_6, AD2=>wcount_6, AD1=>r_gcount_w26, + AD0=>scuba_vlo, DO0=>full_cmp_clr); + + pdp_ram_0_0_0: DP16KB + -- synopsys translate_off + generic map (CSDECODE_B=> "000", CSDECODE_A=> "000", WRITEMODE_B=> "NORMAL", + WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", RESETMODE=> "ASYNC", + REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 18, + DATA_WIDTH_A=> 18) + -- synopsys translate_on + port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), + DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), + DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), + DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), + DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), + DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, + ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wptr_0, ADA5=>wptr_1, + ADA6=>wptr_2, ADA7=>wptr_3, ADA8=>wptr_4, ADA9=>wptr_5, + ADA10=>scuba_vlo, ADA11=>scuba_vlo, ADA12=>scuba_vlo, + ADA13=>scuba_vlo, CEA=>wren_i, CLKA=>WrClock, WEA=>scuba_vhi, + CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, + RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, + DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, + DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, + DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, + DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, + DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, + DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, + ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rptr_0, ADB5=>rptr_1, + ADB6=>rptr_2, ADB7=>rptr_3, ADB8=>rptr_4, ADB9=>rptr_5, + ADB10=>scuba_vlo, ADB11=>scuba_vlo, ADB12=>scuba_vlo, + ADB13=>scuba_vlo, CEB=>rden_i, CLKB=>RdClock, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>ffidata_0, DOB1=>ffidata_1, + DOB2=>ffidata_2, DOB3=>ffidata_3, DOB4=>ffidata_4, + DOB5=>ffidata_5, DOB6=>ffidata_6, DOB7=>ffidata_7, + DOB8=>ffidata_8, DOB9=>ffidata_9, DOB10=>ffidata_10, + DOB11=>ffidata_11, DOB12=>ffidata_12, DOB13=>ffidata_13, + DOB14=>ffidata_14, DOB15=>ffidata_15, DOB16=>ffidata_16, + DOB17=>ffidata_17); + + FF_89: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_0, SP=>wren_i, CK=>WrClock, PD=>Reset, + Q=>wcount_0); + + FF_88: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_1); + + FF_87: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_2); + + FF_86: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_3); + + FF_85: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_4); + + FF_84: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_5); + + FF_83: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>iwcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wcount_6); + + FF_82: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_0); + + FF_81: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_1); + + FF_80: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_2); + + FF_79: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_3); + + FF_78: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_4); + + FF_77: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gdata_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_5); + + FF_76: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>w_gcount_6); + + FF_75: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_0, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_0); + + FF_74: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_1, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_1); + + FF_73: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_2, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_2); + + FF_72: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_3, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_3); + + FF_71: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_4, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_4); + + FF_70: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_5, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_5); + + FF_69: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>wcount_6, SP=>wren_i, CK=>WrClock, CD=>Reset, + Q=>wptr_6); + + FF_68: FD1P3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_0, SP=>rden_i, CK=>RdClock, PD=>rRst, + Q=>rcount_0); + + FF_67: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_1); + + FF_66: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_2); + + FF_65: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_3); + + FF_64: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_4); + + FF_63: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_5); + + FF_62: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ircount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rcount_6); + + FF_61: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_0); + + FF_60: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_1); + + FF_59: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_2); + + FF_58: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_3); + + FF_57: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_4); + + FF_56: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gdata_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_5); + + FF_55: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>r_gcount_6); + + FF_54: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_0, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_0); + + FF_53: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_1, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_1); + + FF_52: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_2, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_2); + + FF_51: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_3, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_3); + + FF_50: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_4, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_4); + + FF_49: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_5, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_5); + + FF_48: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>rcount_6, SP=>rden_i, CK=>RdClock, CD=>rRst, + Q=>rptr_6); + + FF_47: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_0, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(0)); + + FF_46: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_1, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(1)); + + FF_45: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_2, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(2)); + + FF_44: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_3, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(3)); + + FF_43: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_4, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(4)); + + FF_42: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_5, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(5)); + + FF_41: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_6, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(6)); + + FF_40: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_7, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(7)); + + FF_39: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_8, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(8)); + + FF_38: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_9, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(9)); + + FF_37: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_10, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(10)); + + FF_36: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_11, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(11)); + + FF_35: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_12, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(12)); + + FF_34: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_13, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(13)); + + FF_33: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_14, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(14)); + + FF_32: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_15, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(15)); + + FF_31: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_16, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(16)); + + FF_30: FD1P3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>ffidata_17, SP=>scuba_vhi, CK=>RdClock, CD=>rRst, + Q=>Q(17)); + + FF_29: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_0, CK=>RdClock, CD=>Reset, Q=>w_gcount_r0); + + FF_28: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_1, CK=>RdClock, CD=>Reset, Q=>w_gcount_r1); + + FF_27: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_2, CK=>RdClock, CD=>Reset, Q=>w_gcount_r2); + + FF_26: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_3, CK=>RdClock, CD=>Reset, Q=>w_gcount_r3); + + FF_25: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_4, CK=>RdClock, CD=>Reset, Q=>w_gcount_r4); + + FF_24: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_5, CK=>RdClock, CD=>Reset, Q=>w_gcount_r5); + + FF_23: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_6, CK=>RdClock, CD=>Reset, Q=>w_gcount_r6); + + FF_22: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w0); + + FF_21: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w1); + + FF_20: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w2); + + FF_19: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w3); + + FF_18: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w4); + + FF_17: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w5); + + FF_16: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w6); + + FF_15: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r0, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r20); + + FF_14: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r1, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r21); + + FF_13: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r2, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r22); + + FF_12: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r3, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r23); + + FF_11: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r4, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r24); + + FF_10: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r5, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r25); + + FF_9: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>w_gcount_r6, CK=>RdClock, CD=>Reset, + Q=>w_gcount_r26); + + FF_8: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w0, CK=>WrClock, CD=>rRst, Q=>r_gcount_w20); + + FF_7: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w1, CK=>WrClock, CD=>rRst, Q=>r_gcount_w21); + + FF_6: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w2, CK=>WrClock, CD=>rRst, Q=>r_gcount_w22); + + FF_5: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w3, CK=>WrClock, CD=>rRst, Q=>r_gcount_w23); + + FF_4: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w4, CK=>WrClock, CD=>rRst, Q=>r_gcount_w24); + + FF_3: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w5, CK=>WrClock, CD=>rRst, Q=>r_gcount_w25); + + FF_2: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>r_gcount_w6, CK=>WrClock, CD=>rRst, Q=>r_gcount_w26); + + FF_1: FD1S3BX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>empty_d, CK=>RdClock, PD=>rRst, Q=>empty_i); + + FF_0: FD1S3DX + -- synopsys translate_off + generic map (GSR=> "ENABLED") + -- synopsys translate_on + port map (D=>full_d, CK=>WrClock, CD=>Reset, Q=>full_i); + + w_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>w_gctr_ci, S0=>open, + S1=>open); + + w_gctr_0: CU2 + port map (CI=>w_gctr_ci, PC0=>wcount_0, PC1=>wcount_1, CO=>co0, + NC0=>iwcount_0, NC1=>iwcount_1); + + w_gctr_1: CU2 + port map (CI=>co0, PC0=>wcount_2, PC1=>wcount_3, CO=>co1, + NC0=>iwcount_2, NC1=>iwcount_3); + + w_gctr_2: CU2 + port map (CI=>co1, PC0=>wcount_4, PC1=>wcount_5, CO=>co2, + NC0=>iwcount_4, NC1=>iwcount_5); + + w_gctr_3: CU2 + port map (CI=>co2, PC0=>wcount_6, PC1=>scuba_vlo, CO=>co3, + NC0=>iwcount_6, NC1=>open); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + r_gctr_cia: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, + B1=>scuba_vhi, CI=>scuba_vlo, COUT=>r_gctr_ci, S0=>open, + S1=>open); + + r_gctr_0: CU2 + port map (CI=>r_gctr_ci, PC0=>rcount_0, PC1=>rcount_1, CO=>co0_1, + NC0=>ircount_0, NC1=>ircount_1); + + r_gctr_1: CU2 + port map (CI=>co0_1, PC0=>rcount_2, PC1=>rcount_3, CO=>co1_1, + NC0=>ircount_2, NC1=>ircount_3); + + r_gctr_2: CU2 + port map (CI=>co1_1, PC0=>rcount_4, PC1=>rcount_5, CO=>co2_1, + NC0=>ircount_4, NC1=>ircount_5); + + r_gctr_3: CU2 + port map (CI=>co2_1, PC0=>rcount_6, PC1=>scuba_vlo, CO=>co3_1, + NC0=>ircount_6, NC1=>open); + + empty_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>rden_i, B0=>scuba_vlo, B1=>rden_i, + CI=>scuba_vlo, COUT=>cmp_ci, S0=>open, S1=>open); + + empty_cmp_0: AGEB2 + port map (A0=>rcount_0, A1=>rcount_1, B0=>wcount_r0, + B1=>wcount_r1, CI=>cmp_ci, GE=>co0_2); + + empty_cmp_1: AGEB2 + port map (A0=>rcount_2, A1=>rcount_3, B0=>wcount_r2, + B1=>w_g2b_xor_cluster_0, CI=>co0_2, GE=>co1_2); + + empty_cmp_2: AGEB2 + port map (A0=>rcount_4, A1=>rcount_5, B0=>wcount_r4, + B1=>wcount_r5, CI=>co1_2, GE=>co2_2); + + empty_cmp_3: AGEB2 + port map (A0=>empty_cmp_set, A1=>scuba_vlo, B0=>empty_cmp_clr, + B1=>scuba_vlo, CI=>co2_2, GE=>empty_d_c); + + a0: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>empty_d_c, COUT=>open, S0=>empty_d, + S1=>open); + + full_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_1, S0=>open, S1=>open); + + full_cmp_0: AGEB2 + port map (A0=>wcount_0, A1=>wcount_1, B0=>rcount_w0, + B1=>rcount_w1, CI=>cmp_ci_1, GE=>co0_3); + + full_cmp_1: AGEB2 + port map (A0=>wcount_2, A1=>wcount_3, B0=>rcount_w2, + B1=>r_g2b_xor_cluster_0, CI=>co0_3, GE=>co1_3); + + full_cmp_2: AGEB2 + port map (A0=>wcount_4, A1=>wcount_5, B0=>rcount_w4, + B1=>rcount_w5, CI=>co1_3, GE=>co2_3); + + full_cmp_3: AGEB2 + port map (A0=>full_cmp_set, A1=>scuba_vlo, B0=>full_cmp_clr, + B1=>scuba_vlo, CI=>co2_3, GE=>full_d_c); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + a1: FADD2B + port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, CI=>full_d_c, COUT=>open, S0=>full_d, + S1=>open); + + Empty <= empty_i; + Full <= full_i; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of fifo_dualclock_width_16_reg is + for Structure + for all:AGEB2 use entity ecp2m.AGEB2(V); end for; + for all:AND2 use entity ecp2m.AND2(V); end for; + for all:CU2 use entity ecp2m.CU2(V); end for; + for all:FADD2B use entity ecp2m.FADD2B(V); end for; + for all:FD1P3BX use entity ecp2m.FD1P3BX(V); end for; + for all:FD1P3DX use entity ecp2m.FD1P3DX(V); end for; + for all:FD1S3BX use entity ecp2m.FD1S3BX(V); end for; + for all:FD1S3DX use entity ecp2m.FD1S3DX(V); end for; + for all:INV use entity ecp2m.INV(V); end for; + for all:OR2 use entity ecp2m.OR2(V); end for; + for all:ROM16X1 use entity ecp2m.ROM16X1(V); end for; + for all:VHI use entity ecp2m.VHI(V); end for; + for all:VLO use entity ecp2m.VLO(V); end for; + for all:XOR2 use entity ecp2m.XOR2(V); end for; + for all:DP16KB use entity ecp2m.DP16KB(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/pll_in100_out100.lpc b/lattice/ecp2m/pll_in100_out100.lpc new file mode 100644 index 0000000..3dcd8af --- /dev/null +++ b/lattice/ecp2m/pll_in100_out100.lpc @@ -0,0 +1,56 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.0 +ModuleName=pll_in100_out100 +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=07/06/2009 +Time=13:48:26 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=None +Order=None +IO=0 +Type=ehxpllb +mode=normal +IFrq=100 +OFrq=100.000000 +KFrq= +U_OFrq=100 +U_KFrq=50 +OP_Tol=0.0 +OK_Tol=0.0 +Div=1 +Mult=1 +Post=8 +SecD=2 +fb_mode=CLKOP +PhaseDuty=Static +DelayControl=AUTO_NO_DELAY +External=DISABLED +PCDR=0 +ClkOPBp=0 +EnCLKOS=0 +ClkOSBp=0 +Phase=0.0 +Duty=8 +DPD=50% Duty +EnCLKOK=0 +ClkOKBp=0 +ClkRst=0 diff --git a/lattice/ecp2m/pll_in100_out100.vhd b/lattice/ecp2m/pll_in100_out100.vhd new file mode 100644 index 0000000..58336fe --- /dev/null +++ b/lattice/ecp2m/pll_in100_out100.vhd @@ -0,0 +1,120 @@ +-- VHDL netlist generated by SCUBA ispLever_v72_SP2_Build (23) +-- Module Version: 5.0 +--/opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out100 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 100 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e + +-- Mon Jul 6 13:48:27 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity pll_in100_out100 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : string; + attribute dont_touch of pll_in100_out100 : entity is "true"; +end pll_in100_out100; + +architecture Structure of pll_in100_out100 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "AUTO"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "8"; + attribute CLKFB_DIV of PLLDInst_0 : label is "1"; + attribute CLKI_DIV of PLLDInst_0 : label is "1"; + attribute FIN of PLLDInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 8, + CLKFB_DIV=> 1, CLKI_DIV=> 1) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of pll_in100_out100 is + for Structure + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/lattice/ecp2m/pll_in100_out200.vhd b/lattice/ecp2m/pll_in100_out200.vhd new file mode 100644 index 0000000..281c83b --- /dev/null +++ b/lattice/ecp2m/pll_in100_out200.vhd @@ -0,0 +1,120 @@ +-- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) +-- Module Version: 4.1 +--/opt/lattice/ispLEVER7.1/isptools/ispfpga/bin/lin/scuba -w -n pll_in100_out200 -lang vhdl -synth synplify -arch ep5m00 -type pll -fin 100 -phase_cntl STATIC -fclkop 200 -fclkop_tol 0.0 -delay_cntl AUTO_NO_DELAY -fb_mode CLOCKTREE -extcap DISABLED -noclkos -noclkok -norst -e + +-- Wed Apr 15 17:19:06 2009 + +library IEEE; +use IEEE.std_logic_1164.all; +-- synopsys translate_off +library ecp2m; +use ecp2m.components.all; +-- synopsys translate_on + +entity pll_in100_out200 is + port ( + CLK: in std_logic; + CLKOP: out std_logic; + LOCK: out std_logic); + attribute dont_touch : string; + attribute dont_touch of pll_in100_out200 : entity is "true"; +end pll_in100_out200; + +architecture Structure of pll_in100_out200 is + + -- internal signal declarations + signal CLKOP_t: std_logic; + signal scuba_vlo: std_logic; + signal CLK_t: std_logic; + + -- local component declarations + component VLO + port (Z: out std_logic); + end component; + component EPLLD + -- synopsys translate_off + generic (PLLCAP : in String; CLKOK_BYPASS : in String; + CLKOS_BYPASS : in String; CLKOP_BYPASS : in String; + DUTY : in Integer; PHASEADJ : in String; + PHASE_CNTL : in String; CLKOK_DIV : in Integer; + CLKFB_DIV : in Integer; CLKOP_DIV : in Integer; + CLKI_DIV : in Integer); + -- synopsys translate_on + port (CLKI: in std_logic; CLKFB: in std_logic; RST: in std_logic; + RSTK: in std_logic; DPAMODE: in std_logic; DRPAI3: in std_logic; + DRPAI2: in std_logic; DRPAI1: in std_logic; DRPAI0: in std_logic; + DFPAI3: in std_logic; DFPAI2: in std_logic; DFPAI1: in std_logic; + DFPAI0: in std_logic; CLKOP: out std_logic; CLKOS: out std_logic; + CLKOK: out std_logic; LOCK: out std_logic; CLKINTFB: out std_logic); + end component; + attribute PLLCAP : string; + attribute PLLTYPE : string; + attribute CLKOK_BYPASS : string; + attribute FREQUENCY_PIN_CLKOK : string; + attribute CLKOK_DIV : string; + attribute CLKOS_BYPASS : string; + attribute FREQUENCY_PIN_CLKOP : string; + attribute CLKOP_BYPASS : string; + attribute PHASE_CNTL : string; + attribute FDEL : string; + attribute DUTY : string; + attribute PHASEADJ : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute CLKOP_DIV : string; + attribute CLKFB_DIV : string; + attribute CLKI_DIV : string; + attribute FIN : string; + attribute PLLCAP of PLLDInst_0 : label is "DISABLED"; + attribute PLLTYPE of PLLDInst_0 : label is "AUTO"; + attribute CLKOK_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOK of PLLDInst_0 : label is "50.000000"; + attribute CLKOK_DIV of PLLDInst_0 : label is "2"; + attribute CLKOS_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute FREQUENCY_PIN_CLKOP of PLLDInst_0 : label is "200.000000"; + attribute CLKOP_BYPASS of PLLDInst_0 : label is "DISABLED"; + attribute PHASE_CNTL of PLLDInst_0 : label is "STATIC"; + attribute FDEL of PLLDInst_0 : label is "0"; + attribute DUTY of PLLDInst_0 : label is "8"; + attribute PHASEADJ of PLLDInst_0 : label is "0.0"; + attribute FREQUENCY_PIN_CLKI of PLLDInst_0 : label is "100.000000"; + attribute CLKOP_DIV of PLLDInst_0 : label is "4"; + attribute CLKFB_DIV of PLLDInst_0 : label is "2"; + attribute CLKI_DIV of PLLDInst_0 : label is "1"; + attribute FIN of PLLDInst_0 : label is "100.000000"; + attribute syn_keep : boolean; + attribute syn_noprune : boolean; + attribute syn_noprune of Structure : architecture is true; + +begin + -- component instantiation statements + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLDInst_0: EPLLD + -- synopsys translate_off + generic map (PLLCAP=> "DISABLED", CLKOK_BYPASS=> "DISABLED", + CLKOK_DIV=> 2, CLKOS_BYPASS=> "DISABLED", CLKOP_BYPASS=> "DISABLED", + PHASE_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOP_DIV=> 4, + CLKFB_DIV=> 2, CLKI_DIV=> 1) + -- synopsys translate_on + port map (CLKI=>CLK_t, CLKFB=>CLKOP_t, RST=>scuba_vlo, + RSTK=>scuba_vlo, DPAMODE=>scuba_vlo, DRPAI3=>scuba_vlo, + DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, + DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, + DFPAI0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, CLKOK=>open, + LOCK=>LOCK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; + CLK_t <= CLK; +end Structure; + +-- synopsys translate_off +library ecp2m; +configuration Structure_CON of pll_in100_out200 is + for Structure + for all:VLO use entity ecp2m.VLO(V); end for; + for all:EPLLD use entity ecp2m.EPLLD(V); end for; + end for; +end Structure_CON; + +-- synopsys translate_on diff --git a/media_interfaces/ecp2m_sfp/msg_file.log b/media_interfaces/ecp2m_sfp/msg_file.log index b8a571d..b52c60f 100644 --- a/media_interfaces/ecp2m_sfp/msg_file.log +++ b/media_interfaces/ecp2m_sfp/msg_file.log @@ -1,65 +1,13 @@ -SCUBA, Version ispLever_v72_SP2_Build (23) -Fri Jul 10 17:06:38 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n test -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 9 -data_width 36 -num_words 512 -rdata_width 18 -no_enable -pe -1 -pf -1 -e - Circuit name : test - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[35:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[17:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : test.vhd - VHDL template : test_tmpl.vhd - VHDL testbench : tb_test_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : test.srp - Estimated Resource Usage: - LUT : 104 - EBR : 1 - Reg : 107 - -END SCUBA Module Synthesis -SCUBA, Version ispLever_v72_SP2_Build (23) -Fri Jul 10 17:07:18 2009 - -Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. -Copyright (c) 1995 AT&T Corp. All rights reserved. -Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. -Copyright (c) 2001 Agere Systems All rights reserved. -Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - -BEGIN SCUBA Module Synthesis - - Issued command : /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/scuba -w -n test -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5m00 -type fifodc -addr_width 11 -data_width 8 -num_words 2048 -rdata_width 16 -no_enable -pe -1 -pf -1 -e - Circuit name : test - Module type : ebfifo - Module Version : 5.2 - Ports : - Inputs : Data[7:0], WrClock, RdClock, WrEn, RdEn, Reset, RPReset - Outputs : Q[15:0], Empty, Full - I/O buffer : not inserted - EDIF output : suppressed - VHDL output : test.vhd - VHDL template : test_tmpl.vhd - VHDL testbench : tb_test_tmpl.vhd - VHDL purpose : for synthesis and simulation - Bus notation : big endian - Report output : test.srp - Estimated Resource Usage: - LUT : 114 - EBR : 1 - Reg : 117 - -END SCUBA Module Synthesis + Module Name: serdes_full_quad_8bit + Core Name: PCS + LPC file : serdes_full_quad_8bit.lpc + Parameter File : serdes_full_quad_8bit.pp + Command line: /opt/lattice/ispLEVER7.2/isptools/ispfpga/bin/lin/orcapp -Fmaco serdes_full_quad_8bit.pp + Return Value: + + + Module PCS has been generated in /home/hadaq/jan/cvs/trbnet/media_interfaces/ecp2m_sfp/. successfully! +/home/hadaq/.isplever_lin/ispcpld/bin/hdl2jhd -tfi -mod serdes_full_quad_8bit -ext readme -out serdes_full_quad_8bit -tpl serdes_full_quad_8bit.tft serdes_full_quad_8bit.vhd + +Done successfully! diff --git a/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.lpc b/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.lpc new file mode 100644 index 0000000..4b8a9f3 --- /dev/null +++ b/media_interfaces/ecp2m_sfp/serdes_sfp_0_extclock.lpc @@ -0,0 +1,140 @@ +[Device] +Family=latticeecp2m +PartType=LFE2M20E +PartName=LFE2M20E-5F256C +SpeedGrade=-5 +Package=FPBGA256 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PCS +CoreRevision=7.0 +ModuleName=serdes_sfp_0_extclock +SourceFormat=Schematic/VHDL +ParameterFileVersion=1.0 +Date=07/08/2009 +Time=11:51:55 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +Protocol=Quad +mode=Generic 8B10B +Channel0=SINGLE +Channel1=DISABLE +Channel2=DISABLE +Channel3=DISABLE +Rate0=None +Rate1=None +Rate2=None +Rate3=None +TxRefClk=REFCLK +RxRefClk=REFCLK +ClkRate=2 +ClkMult=20X +CalClkRate=100 +DataWidth=16 +FPGAClkRate=100 +TxRefClkCM=REFCLK +RxRefClk0CM=REFCLK +RxRefClk1CM=REFCLK +RxRefClk2CM=REFCLK +RxRefClk3CM=REFCLK +ClkRateH=1 +ClkMultH=20XH +CalClkRateH=100 +DataWidthH=8 +FPGAClkRateH=100 +VCh0=0 +VCh1=0 +VCh2=0 +VCh3=0 +PreCh0=DISABLE +PreCh1=DISABLE +PreCh2=DISABLE +PreCh3=DISABLE +TxCh0=50 +TxCh1=50 +TxCh2=50 +TxCh3=50 +EqCh0=DISABLE +EqCh1=DISABLE +EqCh2=DISABLE +EqCh3=DISABLE +RxTermCh0=50 +RxTermCh1=50 +RxTermCh2=50 +RxTermCh3=50 +RxCoupCh0=DC +RxCoupCh1=AC +RxCoupCh2=AC +RxCoupCh3=AC +Loss=0 +CDRLoss=0 +TxTerm=50 +TxCoup=DC +TxPllLoss=0 +TxInvCh0=NORMAL +TxInvCh1=NORMAL +TxInvCh2=NORMAL +TxInvCh3=NORMAL +RxInvCh0=NORMAL +RxInvCh1=NORMAL +RxInvCh2=NORMAL +RxInvCh3=NORMAL +RxModeCh0=NORMAL +RxModeCh1=NORMAL +RxModeCh2=NORMAL +RxModeCh3=NORMAL +Plus=1100000101 +Minus=0011111010 +Mask=1111111111 +Align=AUTO +CTCCh0=BYPASS +CTCCh1=BYPASS +CTCCh2=BYPASS +CTCCh3=BYPASS +CC_MATCH1=0000000000 +CC_MATCH2=0000000000 +CC_MATCH3=0100011100 +CC_MATCH4=0100011100 +MinIPG=0 +High=4 +Low=4 +CC_MATCH_MODE=MATCH_4 +RxDataCh0=FALSE +RxDataCh1=FALSE +RxDataCh2=FALSE +RxDataCh3=FALSE +AlignerCh0=FALSE +AlignerCh1=FALSE +AlignerCh2=FALSE +AlignerCh3=FALSE +DetectCh0=FALSE +DetectCh1=FALSE +DetectCh2=FALSE +DetectCh3=FALSE +ELSMCh0=FALSE +ELSMCh1=FALSE +ELSMCh2=FALSE +ELSMCh3=FALSE +_teidleCh0=FALSE +_teidleCh1=FALSE +_teidleCh2=FALSE +_teidleCh3=FALSE +Ports0=FALSE +rdoPorts0=Serial Loopback +Ports1=TRUE +Ports2=TRUE +Ports3=FALSE +Ports3_1=FALSE +Ports4=FALSE diff --git a/pinout/mdc_oep3.lpf b/pinout/mdc_oep3.lpf index d45105f..49e4d21 100644 --- a/pinout/mdc_oep3.lpf +++ b/pinout/mdc_oep3.lpf @@ -95,6 +95,8 @@ BLOCK ASYNCPATHS ; LOCATE COMP "TAD_6" SITE "R9"; LOCATE COMP "TAD_7" SITE "T9"; LOCATE COMP "TAD_8" SITE "R10"; + DEFINE PORT GROUP "tad_grp" "TAD*" ; + IOBUF GROUP "tad_grp" IO_TYPE=LVTTL33 PULLMODE=UP ; LOCATE COMP "CMS" SITE "R2"; LOCATE COMP "GDE" SITE "F16"; diff --git a/trb_net16_hub_ipu_logic.vhd b/trb_net16_hub_ipu_logic.vhd index 828d225..25ea92e 100644 --- a/trb_net16_hub_ipu_logic.vhd +++ b/trb_net16_hub_ipu_logic.vhd @@ -114,6 +114,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal packet_counter : std_logic_vector(c_NUM_WIDTH-1 downto 0); signal reply_data_counter : unsigned(15 downto 0); signal reply_data_counter_reset : std_logic; + signal next_reply_data_counter_reset : std_logic; signal comb_REPLY_POOL_DATAREADY : std_logic; signal comb_REPLY_POOL_DATA : std_logic_vector(c_DATA_WIDTH-1 downto 0); signal comb_REPLY_POOL_PACKET_NUM : std_logic_vector(c_NUM_WIDTH-1 downto 0); @@ -184,7 +185,7 @@ architecture trb_net16_hub_ipu_logic_arch of trb_net16_hub_ipu_logic is signal next_reply_adder_final_result : std_logic_vector(15 downto 0); signal last_reply_adder_ready: std_logic; - signal last_comb_reply_pool_dataready : std_logic; + signal enable_reply_data_counter : std_logic; signal evt_code_mismatch : std_logic; signal evt_number_mismatch : std_logic; signal enable_packing : std_logic; @@ -467,6 +468,8 @@ begin end if; end process; + +--Problematic stuff here... needing reply_packet_num_in to determine read_out ... PROC_auto_read_DHDR : process(current_reply_reading_DHDR, current_reply_reading_HDR, REPLY_PACKET_NUM_IN) begin if (current_reply_reading_DHDR(i) = '1' and REPLY_PACKET_NUM_IN(i*c_NUM_WIDTH+1) = '0') @@ -714,9 +717,9 @@ begin gen_data_counter : process(CLK) begin if rising_edge(CLK) then - if RESET = '1' or reply_data_counter_reset = '1' then - reply_data_counter <= (others => '0'); - elsif last_comb_REPLY_POOL_DATAREADY = '1' and (packet_counter = c_F0 or packet_counter = c_F2) then + if reply_data_counter_reset = '1' then + reply_data_counter <= (others => '0'); --length/source word is not included in word count, so this is word -1 + elsif enable_reply_data_counter = '1' then reply_data_counter <= reply_data_counter + 1; end if; end if; @@ -725,7 +728,8 @@ begin PROC_REG_COMB_DATAREADY : process(CLK) begin if rising_edge(CLK) then - last_comb_REPLY_POOL_DATAREADY <= comb_REPLY_POOL_DATAREADY; + enable_reply_data_counter <= comb_REPLY_POOL_DATAREADY and packet_counter(0); --F1 or F3 + reply_data_counter_reset <= next_reply_data_counter_reset or RESET; end if; end process; @@ -860,7 +864,7 @@ begin reply_arbiter_enable <= '0'; next_reply_compare_start <= '0'; reply_arbiter_CLK_EN <= '0'; - reply_data_counter_reset <= '0'; + next_reply_data_counter_reset <= '0'; start_read_padding <= (others => '0'); next_reply_adder_final_result <= reply_adder_final_result; @@ -957,7 +961,7 @@ begin reply_arbiter_CLK_EN <= '1'; reply_arbiter_enable <= '1'; dhdr_addr <= "110"; - reply_data_counter_reset <= '1'; + next_reply_data_counter_reset <= '1'; end if; end case; @@ -983,7 +987,7 @@ begin if (reply_data_counter = current_point_length and packet_counter(0) = '1' and comb_REPLY_muxed_DATAREADY = '1') or or_all(current_reply_reading_TRM and reply_arbiter_result) = '1' then reply_arbiter_CLK_EN <= '1'; - reply_data_counter_reset <= '1'; + next_reply_data_counter_reset <= '1'; --either padding or trm follows. So: start reading in any case. start_read_padding <= reply_arbiter_result; end if; diff --git a/trb_net16_med_tlk.vhd b/trb_net16_med_tlk.vhd index e253309..4cc1c2f 100644 --- a/trb_net16_med_tlk.vhd +++ b/trb_net16_med_tlk.vhd @@ -112,6 +112,7 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal reg_RX_ER : std_logic; signal reg_TXD : std_logic_vector(15 downto 0); signal reg_TX_EN : std_logic; + signal reg_TX_ER : std_logic; signal TLK_CLK_neg : std_logic; signal CLK_FB_Out, FB_CLK : std_logic; @@ -125,10 +126,15 @@ architecture trb_net16_med_tlk_arch of trb_net16_med_tlk is signal state_bits : std_logic_vector(2 downto 0); signal counter_reset : std_logic; - signal resync_counter : std_logic_vector(2 downto 0); - signal send_resync : std_logic_vector(0 downto 0); - signal send_resync_counter : std_logic_vector(11 downto 0); - signal next_send_resync : std_logic_vector(0 downto 0); + signal reg_SFP_LOS : std_logic; + + signal send_reset : std_logic; + signal make_reset : std_logic; + signal send_reset_counter : std_logic_vector(6 downto 0); + signal send_reset_q : std_logic; + signal make_reset_q : std_logic; + signal sending_reset: std_logic; + signal buf_RESET_TRBNET_OUT : std_logic; signal led_counter : std_logic_vector(18 downto 0); @@ -145,12 +151,12 @@ begin TLK_LOOPEN <= '0'; SFP_TX_DIS <= RESET; - buf_MED_READ_OUT <= tx_allow; - MED_READ_OUT <= buf_MED_READ_OUT; -------------- ---Receiver -------------- + + +--------------------------------------------- +--Receiver FIFO +--------------------------------------------- FIFO_OPT_TO_MED: trb_net_fifo_16bit_bram_dualport generic map( @@ -173,193 +179,107 @@ begin ); fifo_rd_en_a <= rx_allow; - comb_fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) ) and rx_allow; - comb_fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD; - - --- fifo_wr_en_a <= ((reg_RX_DV and not reg_RX_ER) or fifo_almost_empty_a) and rx_allow; --- fifo_rd_en_a <= not fifo_almost_empty_a and rx_allow; + fifo_reset <= internal_reset; + buf_MED_READ_OUT <= tx_allow; buf_MED_DATAREADY_OUT <= fifo_valid_read_a and fifo_dout_a(16) and not fifo_dout_a(17) and rx_allow; - fifo_reset <= internal_reset; - process(TLK_RX_CLK) - begin - if rising_edge(TLK_RX_CLK) then - fifo_wr_en_a <= comb_fifo_wr_en_a; - fifo_din_a <= comb_fifo_din_a; - end if; - end process; - ---STAT_OP & LED ---------------- - process(CLK) + PROC_PACKET_COUNTER : process(CLK) begin if rising_edge(CLK) then - if led_counter(18) = '1' then - led_counter <= (others => '0'); - else - led_counter <= led_counter + 1; - end if; - if buf_med_dataready_out = '1' then - rx_led <= '1'; - elsif led_counter(18) = '1' then - rx_led <= '0'; - end if; - - if MED_DATAREADY_IN = '1' then - tx_led <= '1'; - elsif led_counter(18) = '1' then - tx_led <= '0'; + if internal_reset = '1' or buf_RESET_TRBNET_OUT = '1' then + buf_MED_PACKET_NUM_OUT <= c_H0; + elsif buf_MED_DATAREADY_OUT = '1' then + if buf_MED_PACKET_NUM_OUT = c_max_word_number then + buf_MED_PACKET_NUM_OUT <= (others => '0'); + else + buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; + end if; end if; - end if; end process; - link_led <= (counter(24) or tx_allow) and not sfp_los; - - stat_op(2 downto 0) <= buf_MED_ERROR_OUT; - stat_op(8 downto 3) <= (others => '0'); -- unused - stat_op(9) <= link_led; - stat_op(10) <= rx_led; --rx led - stat_op(11) <= tx_led; --tx led - stat_op(12) <= '0'; -- unused - stat_op(13) <= buf_RESET_TRBNET_OUT; - stat_op(14) <= SFP_LOS; -- reset out - stat_op(15) <= buf_RESET_TRBNET_OUT; -- protocol error - - - process(CLK) + REG_MED_OUTPUTS : process(CLK) begin if rising_edge(CLK) then MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT; MED_DATAREADY_OUT <= buf_MED_DATAREADY_OUT; MED_DATA_OUT <= fifo_dout_a(15 downto 0); + MED_READ_OUT <= buf_MED_READ_OUT; end if; end process; - STAT(0) <= counter(24) or tx_allow; - STAT(1) <= rx_allow; - STAT(2) <= tx_allow; - STAT(3) <= fifo_wr_en_a; - STAT(4) <= fifo_rd_en_a; - STAT(5) <= fifo_empty_a; - STAT(6) <= fifo_rd_en_m; - STAT(7) <= fifo_empty_m; - STAT(8) <= fifo_full_a; - STAT(9) <= fifo_full_m; - STAT(10)<= fifo_dout_m(14); - STAT(11)<= fifo_dout_a(14); - STAT(12)<= fifo_din_a(14); --- STAT(11)<= last_fifo_rd_en_a; - STAT(13) <= internal_reset; - STAT(14) <= reg_RX_DV; - STAT(15) <= reg_RX_ER; - STAT(31 downto 16) <= reg_RXD; - STAT(32) <= fifo_valid_read_m; - STAT(33) <= fifo_valid_read_a; - STAT(36 downto 34) <= state_bits; - STAT(40 downto 37) <= fifo_status_a; - STAT(44 downto 41) <= fifo_status_m; - STAT(48 downto 45) <= fifo_dout_m(3 downto 0); - STAT(50 downto 49) <= fifo_dout_m(17 downto 16); - STAT(54 downto 51) <= fifo_din_a(3 downto 0); - STAT(56 downto 55) <= fifo_din_a(17 downto 16); - STAT(58 downto 57) <= "00"; - STAT(59) <= TLK_CLK_neg; - STAT(60) <= fifo_wr_en_m; - STAT(63 downto 61) <= resync_counter(2 downto 0); - --STAT(63 downto 57) <= (others => '0'); - STAT_MONITOR(17 downto 0) <= fifo_din_a; - STAT_MONITOR(18) <= fifo_almost_full_m; - STAT_MONITOR(19) <= fifo_almost_full_a; - STAT_MONITOR(20) <= fifo_almost_empty_m; - STAT_MONITOR(21) <= fifo_almost_empty_a; - STAT_MONITOR(37 downto 22) <= CTRL_OP; - STAT_MONITOR(46 downto 38) <= (others => '0'); - STAT_MONITOR(47) <= reg_TX_EN; - STAT_MONITOR(63 downto 48) <= reg_TXD; - STAT_MONITOR(81 downto 64) <= fifo_din_a; -- RX_ER & RX_DV & RX_DATA - STAT_MONITOR(100 downto 82) <= (others => '0'); - process(TLK_RX_CLK) + REG_RX_FIFO_INPUTS : process(TLK_RX_CLK) begin if rising_edge(TLK_RX_CLK) then - reg_RXD <= TLK_RXD; - reg_RX_DV <= TLK_RX_DV; - reg_RX_ER <= TLK_RX_ER; + fifo_wr_en_a <= (reg_RX_DV and not reg_RX_ER) and rx_allow; + fifo_din_a <= reg_RX_ER & reg_RX_DV & reg_RXD; end if; end process; - process(CLK) + SYNC_TLK_RX_INPUT : process(TLK_RX_CLK) begin - if rising_edge(CLK) then - if internal_reset = '1' or buf_RESET_TRBNET_OUT = '1' then - buf_MED_PACKET_NUM_OUT <= c_H0; - elsif buf_MED_DATAREADY_OUT = '1' then - if buf_MED_PACKET_NUM_OUT = c_max_word_number then - buf_MED_PACKET_NUM_OUT <= (others => '0'); - else - buf_MED_PACKET_NUM_OUT <= buf_MED_PACKET_NUM_OUT + 1; - end if; - end if; + if rising_edge(TLK_RX_CLK) then + reg_RXD <= TLK_RXD; + reg_RX_DV <= TLK_RX_DV; + reg_RX_ER <= TLK_RX_ER; end if; end process; ---Detect resync (incl. SFP_LOS) ---------------- - process(CLK) - begin - if rising_edge(CLK) then - buf_RESET_TRBNET_OUT <= '0'; - if RESET = '1' or internal_reset = '1' then - buf_RESET_TRBNET_OUT <= '1'; - resync_counter <= "000"; - end if; - if buf_MED_DATAREADY_OUT = '1' then - if fifo_dout_a(15 downto 0) = x"7F7F" then - resync_counter <= resync_counter + 1; - else - resync_counter <= "000"; - end if; - end if; - if resync_counter(2) = '1' or SFP_LOS = '1' then - resync_counter <= resync_counter + 1; - buf_RESET_TRBNET_OUT <= '1'; - end if; - if resync_counter = "111" then - buf_RESET_TRBNET_OUT <= '0'; - end if; - end if; - end process; +--------------------------------------------- +--Detect Reset (Error Propagation) +--------------------------------------------- - process(CLK) + + process(TLK_RX_CLK) begin - if rising_edge(CLK) then + if rising_edge(TLK_RX_CLK) then if RESET = '1' then - next_send_resync <= "0"; - send_resync_counter <= (others => '0'); + send_reset_counter <= (others => '0'); + send_reset <= '0'; + make_reset <= '0'; else - if not (send_resync_counter = 0) then - send_resync_counter <= send_resync_counter + 1; + if reg_RX_DV = '1' and reg_RX_ER = '1' and send_reset_counter(5) = '0' then + send_reset_counter <= send_reset_counter + 1; + elsif reg_RX_ER = '0' then + send_reset_counter <= (others => '0'); end if; - if CTRL_OP(15) = '1' and send_resync_counter(11 downto 4) = 0 then - next_send_resync <= "1"; - send_resync_counter <= x"001"; - end if; - if send_resync_counter = x"00F" then - next_send_resync <= "0"; + if send_reset = '1' and reg_RX_ER = '0' then --do reset + make_reset <= '1'; + send_reset <= '0'; + elsif send_reset_counter(5) = '1' and reg_RX_ER = '1' then --send reset + send_reset <= '1'; + make_reset <= '0'; + else + send_reset <= '0'; + make_reset <= '0'; end if; end if; end if; end process; - INST_SYNC_RESYNC : signal_sync + SYNC_SEND_RESET : signal_sync + generic map( + WIDTH => 2, + DEPTH => 2 + ) + port map( + RESET => RESET, + CLK0 => CLK, + CLK1 => CLK, + D_IN(0) => send_reset, + D_IN(1) => make_reset, + D_OUT(0) => send_reset_q, + D_OUT(1) => make_reset_q + ); + + SYNC_SENDING_RESET : signal_sync generic map( WIDTH => 1, DEPTH => 2 @@ -368,13 +288,27 @@ begin RESET => RESET, CLK0 => TLK_CLK_neg, CLK1 => TLK_CLK_neg, - D_IN => next_send_resync, - D_OUT => send_resync + D_IN(0) => CTRL_OP(15), + D_OUT(0) => sending_reset ); -------------- ---Sender -------------- + + SYNC_SFP_LOS : signal_sync + generic map( + WIDTH => 1, + DEPTH => 2 + ) + port map( + RESET => RESET, + CLK0 => CLK, + CLK1 => CLK, + D_IN(0) => SFP_LOS, + D_OUT(0) => reg_SFP_LOS + ); + +--------------------------------------------- +--A DCM - not really used +--------------------------------------------- U_DCM_Transmitter: DCM --no_sim-- generic map( --no_sim-- @@ -401,6 +335,12 @@ U0_BUFG: BUFG port map (I => CLK_FB_Out, O => TLK_CLK_neg);--no_sim-- U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim-- --sim--TLK_CLK_neg <= not TLK_CLK; + + +--------------------------------------------- +--TX FIFO +--------------------------------------------- + FIFO_MED_TO_OPT: trb_net_fifo_16bit_bram_dualport generic map( USE_STATUS_FLAGS => c_NO @@ -421,46 +361,46 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim-- almost_full_out => fifo_almost_full_m ); - TLK_TX_ER <= '0'; - process(TLK_CLK_neg,reg_TXD,reg_TX_EN) + + REG_TLK_TX_OUT : process(TLK_CLK_neg) begin if rising_edge(TLK_CLK_neg) then TLK_TX_EN <= reg_TX_EN; + TLK_TX_ER <= reg_TX_ER; TLK_TXD <= reg_TXD; end if; end process; - process(CLK) + REG_TLK_TX_buffers : process(TLK_CLK_neg) begin - if rising_edge(CLK) then - fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT);-- or fifo_almost_empty_m; - fifo_din_m <= MED_PACKET_NUM_IN(2) & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN; + if rising_edge(TLK_CLK_neg) then + reg_TXD <= fifo_dout_m(15 downto 0); + reg_TX_ER <= sending_reset; + reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or sending_reset; end if; end process; - fifo_rd_en_m <= tx_allow; -- and not fifo_empty_m; and not fifo_almost_empty_m; - - process(TLK_CLK_neg) + PROC_TX_FIFO_INPUT : process(CLK) begin - if rising_edge(TLK_CLK_neg) then - if send_resync(0) = '0' then - reg_TXD <= fifo_dout_m(15 downto 0); - else - reg_TXD <= x"7F7F"; - end if; - reg_TX_EN <= (fifo_valid_read_m and fifo_dout_m(16)) or send_resync(0); --last_fifo_rd_en_m; + if rising_edge(CLK) then + fifo_wr_en_m <= (MED_DATAREADY_IN and buf_MED_READ_OUT); + fifo_din_m <= MED_PACKET_NUM_IN(2) & (MED_DATAREADY_IN and buf_MED_READ_OUT) & MED_DATA_IN; end if; end process; + fifo_rd_en_m <= tx_allow; + + + -------------- ---Medium states -------------- +--------------------------------------------- +--Link State Machine +--------------------------------------------- medium_states : process(current_state, tx_allow, rx_allow, internal_reset, MED_READ_IN, - reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter, send_resync) + reg_RX_ER, reg_RX_DV, buf_MED_ERROR_OUT, counter, make_reset_q) begin next_state <= current_state; next_tx_allow <= tx_allow; @@ -496,8 +436,8 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim-- end if; when WORKING => next_MED_ERROR_OUT <= ERROR_OK; - --sim-- next_tx_allow <='1'; - --sim-- next_rx_allow <= '1'; + next_tx_allow <= '1'; + next_rx_allow <= '1'; next_internal_reset <= '0'; end case; if reg_RX_ER = '1' and reg_RX_DV = '0' and internal_reset = '0' then @@ -509,8 +449,8 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim-- if MED_READ_IN = '0' then next_MED_ERROR_OUT <= ERROR_NC; end if; - if send_resync(0) = '1' then - next_state <= WAIT_FOR_RX_LOCK; + if make_reset_q = '1' or reg_SFP_LOS = '1' then + next_state <= RESETTING; next_MED_ERROR_OUT <= ERROR_NC; counter_reset <= '1'; end if; @@ -565,4 +505,101 @@ U1_BUFG: BUFG port map (I => CLK_FB_Out, O => FB_CLK);--no_sim-- end process; + + + +--------------------------------------------- +--STAT_OP & LED +--------------------------------------------- + process(CLK) + begin + if rising_edge(CLK) then + if led_counter(18) = '1' then + led_counter <= (others => '0'); + else + led_counter <= led_counter + 1; + end if; + if buf_med_dataready_out = '1' then + rx_led <= '1'; + elsif led_counter(18) = '1' then + rx_led <= '0'; + end if; + + if MED_DATAREADY_IN = '1' then + tx_led <= '1'; + elsif led_counter(18) = '1' then + tx_led <= '0'; + end if; + + end if; + end process; + + link_led <= (counter(24) or tx_allow) and not reg_sfp_los; + + stat_op(2 downto 0) <= buf_MED_ERROR_OUT; + stat_op(8 downto 3) <= (others => '0'); -- unused + stat_op(9) <= link_led; + stat_op(10) <= rx_led; --rx led + stat_op(11) <= tx_led; --tx led + stat_op(12) <= '0'; -- unused + stat_op(13) <= '0'; + stat_op(14) <= reg_SFP_LOS or make_reset_q; -- reset out + stat_op(15) <= send_reset_q; -- protocol error + +--------------------------------------------- +--Debugging +--------------------------------------------- + + + STAT(0) <= counter(24) or tx_allow; + STAT(1) <= rx_allow; + STAT(2) <= tx_allow; + STAT(3) <= fifo_wr_en_a; + STAT(4) <= fifo_rd_en_a; + STAT(5) <= fifo_empty_a; + STAT(6) <= fifo_rd_en_m; + STAT(7) <= fifo_empty_m; + STAT(8) <= fifo_full_a; + STAT(9) <= fifo_full_m; + STAT(10)<= fifo_dout_m(14); + STAT(11)<= fifo_dout_a(14); + STAT(12)<= fifo_din_a(14); +-- STAT(11)<= last_fifo_rd_en_a; + STAT(13) <= internal_reset; + STAT(14) <= reg_RX_DV; + STAT(15) <= reg_RX_ER; + STAT(31 downto 16) <= reg_RXD; + STAT(32) <= fifo_valid_read_m; + STAT(33) <= fifo_valid_read_a; + STAT(36 downto 34) <= state_bits; + STAT(40 downto 37) <= fifo_status_a; + STAT(44 downto 41) <= fifo_status_m; + STAT(48 downto 45) <= fifo_dout_m(3 downto 0); + STAT(50 downto 49) <= fifo_dout_m(17 downto 16); + STAT(54 downto 51) <= fifo_din_a(3 downto 0); + STAT(56 downto 55) <= fifo_din_a(17 downto 16); + STAT(57) <= make_reset; + STAT(58) <= send_reset; + STAT(59) <= TLK_CLK_neg; + STAT(60) <= fifo_wr_en_m; + STAT(63 downto 61) <= send_reset_counter(2 downto 0); + --STAT(63 downto 57) <= (others => '0'); + + STAT_MONITOR(17 downto 0) <= fifo_din_a; + STAT_MONITOR(18) <= fifo_almost_full_m; + STAT_MONITOR(19) <= fifo_almost_full_a; + STAT_MONITOR(20) <= fifo_almost_empty_m; + STAT_MONITOR(21) <= fifo_almost_empty_a; + STAT_MONITOR(37 downto 22) <= CTRL_OP; + STAT_MONITOR(45 downto 38) <= (others => '0'); + STAT_MONITOR(46) <= reg_TX_ER; + STAT_MONITOR(47) <= reg_TX_EN; + STAT_MONITOR(63 downto 48) <= reg_TXD; + STAT_MONITOR(81 downto 64) <= fifo_din_a; -- RX_ER & RX_DV & RX_DATA + STAT_MONITOR(88 downto 82) <= send_reset_counter; + STAT_MONITOR(100 downto 89) <= (others => '0'); + + + + end architecture; diff --git a/trb_net16_regIO.vhd b/trb_net16_regIO.vhd index adb8d0b..7123784 100644 --- a/trb_net16_regIO.vhd +++ b/trb_net16_regIO.vhd @@ -300,7 +300,7 @@ begin buf_rom_read_addr, ADR_SEND_OUT, rom_read_dout, COMMON_STAT_REG_IN, buf_COMMON_CTRL_REG_OUT, timeout, unknown, addr_counter_enable, DAT_UNKNOWN_ADDR_IN, dat_data_counter, DAT_WRITE_ACK_IN, DAT_DATAREADY_IN_before, ADR_DONT_UNDERSTAND, - global_time_i, time_since_last_trg_i + global_time_i, time_since_last_trg_i ) variable regnum_STAT : integer range 0 to 2**NUM_STAT_REGS-1; variable regnum_CTRL : integer range 0 to 2**NUM_CTRL_REGS-1; -- 2.43.0