From 4fc86d48ffdf8bda8d94c8868273afdf32f7c5d0 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Thu, 15 Apr 2021 10:14:10 +0200 Subject: [PATCH] add sync for preload signal with additional variable to suppress multiple read signals due to signal delay --- src/cri_trbnet_dca_bridge.vhd | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/src/cri_trbnet_dca_bridge.vhd b/src/cri_trbnet_dca_bridge.vhd index eddf4db..e6d43c0 100644 --- a/src/cri_trbnet_dca_bridge.vhd +++ b/src/cri_trbnet_dca_bridge.vhd @@ -122,7 +122,7 @@ signal tx_rd_size_ack, last_tx_rd_size_ack, tx_rd_size_ack_sync : std_logic; signal WB_RESPONSE_READY : std_logic; signal tx_data_size_dca : std_logic_vector(15 downto 0); -signal preload_word_tx_fifo : std_logic; +signal preload_word_tx_fifo, preload_word_tx_fifo_sync : std_logic; signal tx_data_out : std_logic_vector(31 downto 0); @@ -351,6 +351,7 @@ end process TX_FIFO_WR_SYNC; TX_FIFO_READ_PROC : process(CLK_DCA) + variable preload : std_logic := '0'; begin if rising_edge(CLK_DCA) then @@ -364,9 +365,10 @@ begin end if; -- controls the readout of the fifo. fifo gets the first word already loaded before first readout as only an ack from readout is available. - if (dissect_current_state = WAIT_FOR_LOAD) then + if ((dissect_current_state = WAIT_FOR_LOAD) and (preload = '0')) then tx_fifo_rd <= '1'; preload_word_tx_fifo <= '1'; + preload := '1'; elsif (tx_rd_ack = '1') then tx_fifo_rd <= '1'; preload_word_tx_fifo <= '0'; @@ -375,6 +377,10 @@ begin preload_word_tx_fifo <= '0'; end if; + if dissect_current_state /= WAIT_FOR_LOAD then + preload := '0'; -- reset of preload; tx only read out once, even with sync of preload signal. + end if; + if (dissect_current_state = WAIT_CNTR) then wait_cnt <= wait_cnt + 1; else @@ -400,6 +406,17 @@ THE_SYNC_WAIT_DCA : entity work.pulse_sync PULSE_B_OUT => wait_dca_sync ); +THE_SYNC_TX_PRELOAD : entity work.pulse_sync + port map( + RESET_A_IN => reset_dca, + CLK_A_IN => CLK_DCA, + PULSE_A_IN => preload_word_tx_fifo, + + RESET_B_IN => RESET, + CLK_B_IN => CLK, + PULSE_B_OUT => preload_word_tx_fifo_sync + ); + THE_SYNC_TX_LOAD_CTR : entity work.signal_sync generic map( WIDTH => 16, @@ -493,7 +510,7 @@ begin end if; end process DISSECT_MACHINE_PROC; -DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, rx_data_wr_sync, rx_data_dca_sync, preload_word_tx_fifo, DCA_INIT_READ_IN, DCA_REPLY_DATAREADY_IN, tx_loaded_ctr_sync, tx_rd_size_ack_sync, tx_data_ctr, rx_fifo_q, DCA_BUSY_IN, wait_dca_sync) +DISSECT_MACHINE : process(dissect_current_state, reset_detected, too_much_data, rx_data_wr_sync, rx_data_dca_sync, preload_word_tx_fifo_sync, DCA_INIT_READ_IN, DCA_REPLY_DATAREADY_IN, tx_loaded_ctr_sync, tx_rd_size_ack_sync, tx_data_ctr, rx_fifo_q, DCA_BUSY_IN, wait_dca_sync) begin state <= x"0"; @@ -567,7 +584,7 @@ begin when WAIT_FOR_LOAD => state <= x"8"; - if preload_word_tx_fifo = '1' then + if preload_word_tx_fifo_sync = '1' then dissect_next_state <= LOAD_FRAME; else dissect_next_state <= WAIT_FOR_LOAD; -- 2.43.0