From 50731cfcc10b92a5f57e18ffed09f478145878ef Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Mon, 11 Apr 2011 13:45:28 +0000 Subject: [PATCH] *** empty log message *** --- .../trb_net16_med_ecp_fot_4_ctc.vhd | 7 +- media_interfaces/trb_net16_rx_control.vhd | 2 +- special/handler_data.vhd | 1 + trb_net16_api_base.vhd | 2 +- trb_net16_endpoint_hades_full.vhd | 109 +++++++++--------- trb_net16_endpoint_hades_full_handler.vhd | 2 + trb_net16_hub_logic.vhd | 2 + trb_net16_obuf.vhd | 2 +- trb_net_components.vhd | 2 + 9 files changed, 69 insertions(+), 60 deletions(-) diff --git a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd index 8d818f3..917e4d9 100644 --- a/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd +++ b/media_interfaces/trb_net16_med_ecp_fot_4_ctc.vhd @@ -291,7 +291,7 @@ signal tx_lane_reset : std_logic; signal ffs_plol_counter : std_logic_vector(18 downto 0); signal ffs_plol_low_stable : std_logic; -signal statreg_rxcontrol_i : std_logic_vector(255 downto 0); +signal statreg_rxcontrol_i : std_logic_vector(96*4-1 downto 0); signal statreg_txcontrol_i : std_logic_vector(127 downto 0); @@ -663,7 +663,7 @@ gen_rx: for i in 0 to 3 generate PACKET_TIMEOUT_OUT => packet_timeout(i), -- Debugging ENABLE_CORRECTION_IN => CTRL_OP(i*16+8), - STAT_REG_OUT => statreg_rxcontrol_i(i*64+63 downto i*64), + STAT_REG_OUT => statreg_rxcontrol_i(i*96+95 downto i*96), DEBUG_OUT => debug_rxcontrol_i(i*32+31 downto i*32) ); @@ -857,8 +857,7 @@ end generate; end process; STAT_REG_OUT(128*i+31 downto 128*i+0) <= statreg_txcontrol_i(32*i+31 downto 32*i); - STAT_REG_OUT(128*i+95 downto 128*i+32) <= statreg_rxcontrol_i(64*i+63 downto 64*i); - STAT_REG_OUT(128*i+127 downto 128*i+96) <= (others => '0'); + STAT_REG_OUT(128*i+127 downto 128*i+32) <= statreg_rxcontrol_i(96*i+95 downto 96*i); end generate; diff --git a/media_interfaces/trb_net16_rx_control.vhd b/media_interfaces/trb_net16_rx_control.vhd index 9ccb6eb..c7dd5ba 100644 --- a/media_interfaces/trb_net16_rx_control.vhd +++ b/media_interfaces/trb_net16_rx_control.vhd @@ -477,7 +477,7 @@ debug(15 downto 6) <= debug_rch(15 downto 6); STAT_REG_OUT(15 downto 0) <= statreg_rxfullpackets; STAT_REG_OUT(23 downto 16) <= statreg_rxcommahandler(7 downto 0); -STAT_REG_OUT(31 downto 24) <= rx_position; --load RX buffer position +STAT_REG_OUT(31 downto 24) <= (others => '0'); --rx_position; --load RX buffer position STAT_REG_OUT(39 downto 32) <= statreg_rxchecker(7 downto 0); STAT_REG_OUT(47 downto 40) <= start_position; --restart sending from this position STAT_REG_OUT(48) <= packet_timeout; diff --git a/special/handler_data.vhd b/special/handler_data.vhd index 19d9999..0d465c8 100644 --- a/special/handler_data.vhd +++ b/special/handler_data.vhd @@ -64,6 +64,7 @@ end entity; -- 23 - 16 : trigger code -- 27 - 24 : trigger type -- 28 : suppress data +-- 29 : timing trigger error -- Fifo has an internal output register. -- Output is valid two clock cycles after read diff --git a/trb_net16_api_base.vhd b/trb_net16_api_base.vhd index 6e34136..1e89383 100644 --- a/trb_net16_api_base.vhd +++ b/trb_net16_api_base.vhd @@ -874,7 +874,7 @@ INT_MASTER_DATAREADY_OUT <= buf_INT_MASTER_DATAREADY_OUT; else --API_TYPE = 1 if master_start = '1' then buf_APL_RUN_OUT <= '1'; - elsif master_running = '0' and state_to_apl = sa_INACTIVE then + elsif master_running = '0' and state_to_apl = sa_INACTIVE and APL_DATAREADY_OUT = '0' then --add dataready on 18032011 buf_APL_RUN_OUT <= '0'; end if; end if; diff --git a/trb_net16_endpoint_hades_full.vhd b/trb_net16_endpoint_hades_full.vhd index d0a341b..4a16dc9 100644 --- a/trb_net16_endpoint_hades_full.vhd +++ b/trb_net16_endpoint_hades_full.vhd @@ -152,6 +152,7 @@ entity trb_net16_endpoint_hades_full is IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + STAT_TRIGGER_OUT : out std_logic_vector (63 downto 0); DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end trb_net16_endpoint_hades_full; @@ -263,12 +264,12 @@ architecture trb_net16_endpoint_hades_full_arch of trb_net16_endpoint_hades_full signal buf_LVL1_TRG_RELEASE_IN : std_logic; signal buf_LVL1_TRG_DATA_VALID_OUT : std_logic; - signal int_lvl1_delay : std_logic_vector(15 downto 0); - signal int_trg_reset : std_logic; - signal reset_trg_logic : std_logic; - signal stat_lvl1_handler : std_logic_vector(63 downto 0); - signal stat_counters_lvl1_handler: std_logic_vector(63 downto 0); - signal trg_invert_i : std_logic; + signal int_lvl1_delay : std_logic_vector(15 downto 0); + signal int_trg_reset : std_logic; + signal reset_trg_logic : std_logic; + signal stat_lvl1_handler : std_logic_vector(63 downto 0); + signal stat_counters_lvl1_handler: std_logic_vector(63 downto 0); + signal trg_invert_i : std_logic; signal int_multiple_trg : std_logic; signal int_lvl1_timeout_detected : std_logic; signal int_lvl1_spurious_trg : std_logic; @@ -870,53 +871,53 @@ begin -- Check LVL1 trigger number ------------------------------------------------- - THE_LVL1_HANDLER : handler_lvl1 - generic map ( - TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW - ) - port map( - RESET => reset_trg_logic, - RESET_STATS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(5), - CLOCK => CLK, - --Timing Trigger - LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN, - LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16), - --LVL1_handler connection - LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT, - LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT, - LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT, - LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT, - LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT, - LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN, - LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN, - - LVL1_INT_TRG_NUMBER_OUT => int_trigger_num, - LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1), - LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32), - - --FEE logic / Data Handler - LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT, - LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT, - LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT, - LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT, - LVL1_MULTIPLE_TRG_OUT => int_multiple_trg, - LVL1_DELAY_OUT => int_lvl1_delay, - LVL1_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected, - LVL1_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg, - LVL1_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg, - SPIKE_DETECTED_OUT => int_spike_detected, - - LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, - LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, - - --Stat/Control - STATUS_OUT => stat_lvl1_handler, - TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95), - TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93), - COUNTERS_STATUS_OUT => stat_counters_lvl1_handler, - --Debug - DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT - ); + THE_LVL1_HANDLER : handler_lvl1 + generic map ( + TIMING_TRIGGER_RAW => TIMING_TRIGGER_RAW + ) + port map( + RESET => reset_trg_logic, + RESET_STATS_IN => buf_REGIO_COMMON_CTRL_REG_OUT(5), + CLOCK => CLK, + --Timing Trigger + LVL1_TIMING_TRG_IN => TRG_TIMING_TRG_RECEIVED_IN, + LVL1_PSEUDO_TMG_TRG_IN => buf_REGIO_COMMON_CTRL_REG_OUT(16), + --LVL1_handler connection + LVL1_TRG_RECEIVED_IN => buf_LVL1_TRG_RECEIVED_OUT, + LVL1_TRG_TYPE_IN => buf_LVL1_TRG_TYPE_OUT, + LVL1_TRG_NUMBER_IN => buf_LVL1_TRG_NUMBER_OUT, + LVL1_TRG_CODE_IN => buf_LVL1_TRG_CODE_OUT, + LVL1_TRG_INFORMATION_IN => buf_LVL1_TRG_INFORMATION_OUT, + LVL1_ERROR_PATTERN_OUT => buf_LVL1_ERROR_PATTERN_IN, + LVL1_TRG_RELEASE_OUT => buf_LVL1_TRG_RELEASE_IN, + + LVL1_INT_TRG_NUMBER_OUT => int_trigger_num, + LVL1_INT_TRG_LOAD_IN => buf_COMMON_CTRL_REG_STROBE(1), + LVL1_INT_TRG_COUNTER_IN => buf_REGIO_COMMON_CTRL_REG_OUT(47 downto 32), + + --FEE logic / Data Handler + LVL1_TRG_DATA_VALID_OUT => buf_LVL1_TRG_DATA_VALID_OUT, + LVL1_VALID_TIMING_TRG_OUT => buf_LVL1_VALID_TIMING_TRG_OUT, + LVL1_VALID_NOTIMING_TRG_OUT => buf_LVL1_VALID_NOTIMING_TRG_OUT, + LVL1_INVALID_TRG_OUT => buf_LVL1_INVALID_TRG_OUT, + LVL1_MULTIPLE_TRG_OUT => int_multiple_trg, + LVL1_DELAY_OUT => int_lvl1_delay, + LVL1_TIMEOUT_DETECTED_OUT => int_lvl1_timeout_detected, + LVL1_SPURIOUS_TRG_OUT => int_lvl1_spurious_trg, + LVL1_MISSING_TMG_TRG_OUT => int_lvl1_missing_tmg_trg, + SPIKE_DETECTED_OUT => int_spike_detected, + + LVL1_ERROR_PATTERN_IN => LVL1_ERROR_PATTERN_IN, + LVL1_TRG_RELEASE_IN => LVL1_TRG_RELEASE_IN, + + --Stat/Control + STATUS_OUT => stat_lvl1_handler, + TRG_ENABLE_IN => buf_REGIO_COMMON_CTRL_REG_OUT(95), + TRG_INVERT_IN => buf_REGIO_COMMON_CTRL_REG_OUT(93), + COUNTERS_STATUS_OUT => stat_counters_lvl1_handler, + --Debug + DEBUG_OUT => DEBUG_LVL1_HANDLER_OUT + ); TRG_SPIKE_DETECTED_OUT <= int_spike_detected; TRG_SPURIOUS_TRG_OUT <= int_lvl1_spurious_trg; @@ -924,6 +925,8 @@ begin TRG_MULTIPLE_TRG_OUT <= int_multiple_trg; TRG_MISSING_TMG_TRG_OUT <= int_lvl1_missing_tmg_trg; + + -- THE_TRG_SYNC : signal_sync -- generic map( -- DEPTH => 2, diff --git a/trb_net16_endpoint_hades_full_handler.vhd b/trb_net16_endpoint_hades_full_handler.vhd index ec450d0..667771f 100644 --- a/trb_net16_endpoint_hades_full_handler.vhd +++ b/trb_net16_endpoint_hades_full_handler.vhd @@ -133,6 +133,7 @@ entity trb_net16_endpoint_hades_full_handler is IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + STAT_TRIGGER_OUT : out std_logic_vector (63 downto 0); DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end entity; @@ -344,6 +345,7 @@ begin IOBUF_CTRL_GEN => (others => '0'), STAT_ONEWIRE => open, STAT_ADDR_DEBUG => open, + STAT_TRIGGER_OUT => STAT_TRIGGER_OUT, DEBUG_LVL1_HANDLER_OUT => DEBUG_LVL1_HANDLER_OUT ); diff --git a/trb_net16_hub_logic.vhd b/trb_net16_hub_logic.vhd index ce71f7c..b620e98 100644 --- a/trb_net16_hub_logic.vhd +++ b/trb_net16_hub_logic.vhd @@ -578,6 +578,8 @@ begin timeout_counter(i) <= (others => '0'); elsif timeout_counter(i) = reg_CTRL_TIMEOUT_TIME then connection_timed_out(i) <= '1'; + elsif timer_ms_tick = '1' and INIT_READ_IN(i) = '0' and INIT_DATAREADY_OUT(i) = '1' then + timeout_counter(i) <= timeout_counter(i) + to_unsigned(2,2); elsif timer_ms_tick = '1' and REPLY_POOL_next_read = '1' and got_trm(i) = '0' then timeout_counter(i) <= timeout_counter(i) + to_unsigned(1,1); end if; diff --git a/trb_net16_obuf.vhd b/trb_net16_obuf.vhd index 979ccae..19950e2 100644 --- a/trb_net16_obuf.vhd +++ b/trb_net16_obuf.vhd @@ -545,7 +545,7 @@ begin if current_timeout_value = 0 then wait_for_ack_counter <= (others => '0'); elsif TRANSMITTED_BUFFERS(1) = '0' then - wait_for_ack_counter <= (1 => '1', others => '0'); + wait_for_ack_counter <= (0 => '1', others => '0'); elsif wait_for_ack_counter = current_timeout_value then wait_for_ack_timeout <= '1'; reset_transmitted_buffers <= '1'; diff --git a/trb_net_components.vhd b/trb_net_components.vhd index 5dd21b6..14904f5 100644 --- a/trb_net_components.vhd +++ b/trb_net_components.vhd @@ -627,6 +627,7 @@ end component; IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + STAT_TRIGGER_OUT : out std_logic_vector (63 downto 0); DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end component; @@ -756,6 +757,7 @@ end component; IOBUF_CTRL_GEN : in std_logic_vector (4*32-1 downto 0) := (others => '0'); STAT_ONEWIRE : out std_logic_vector (31 downto 0); STAT_ADDR_DEBUG : out std_logic_vector (15 downto 0); + STAT_TRIGGER_OUT : out std_logic_vector (63 downto 0); DEBUG_LVL1_HANDLER_OUT : out std_logic_vector (15 downto 0) ); end component; -- 2.43.0