From 50b332d97e3da8f25e39cda22dfe5fe1e42ca5d3 Mon Sep 17 00:00:00 2001 From: hadaq Date: Mon, 25 May 2009 13:20:10 +0000 Subject: [PATCH] new --- optical_link/flexi_PCS_channel_synch.vhd | 192 +++++++++++++++++++++-- optical_link/flexi_PCS_synch.vhd | 10 +- optical_link/hub.lpf | 2 + optical_link/hub.vhd | 40 ++--- optical_link/hub_syn.prj | 1 + 5 files changed, 215 insertions(+), 30 deletions(-) diff --git a/optical_link/flexi_PCS_channel_synch.vhd b/optical_link/flexi_PCS_channel_synch.vhd index aec9a8a..9df7a23 100644 --- a/optical_link/flexi_PCS_channel_synch.vhd +++ b/optical_link/flexi_PCS_channel_synch.vhd @@ -9,6 +9,8 @@ use work.trb_net_std.all; use work.trb_net16_hub_func.all; entity flexi_PCS_channel_synch is + generic ( + SYSTEM : positive); port ( RESET : in std_logic; SYSTEM_CLK : in std_logic; @@ -97,11 +99,54 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is PULSE : out std_logic); end component; + component cross_clk + port ( + WrAddress : in std_logic_vector(2 downto 0); + Data : in std_logic_vector(31 downto 0); + WrClock : in std_logic; + WE : in std_logic; + WrClockEn : in std_logic; + RdAddress : in std_logic_vector(2 downto 0); + RdClock : in std_logic; + RdClockEn : in std_logic; + Reset : in std_logic; + Q : out std_logic_vector(31 downto 0)); + end component; + + component trbv2_cross_clk + port ( + addra : in std_logic_vector(2 downto 0); + addrb : in std_logic_vector(2 downto 0); + clka : in std_logic; + clkb : in std_logic; + dina : in std_logic_vector(31 downto 0); + dinb : in std_logic_vector(31 downto 0); + douta : out std_logic_vector(31 downto 0); + doutb : out std_logic_vector(31 downto 0); + wea : in std_logic; + web : in std_logic); + end component; + + component trbv2_link_fifo + port ( + din : IN std_logic_VECTOR(17 downto 0); + rd_clk : IN std_logic; + rd_en : IN std_logic; + rst : IN std_logic; + wr_clk : IN std_logic; + wr_en : IN std_logic; + almost_empty : OUT std_logic; + almost_full : OUT std_logic; + dout : OUT std_logic_VECTOR(17 downto 0); + empty : OUT std_logic; + full : OUT std_logic); + end component; + type SYNC_MACHINE is (FIRST_DUMMY_STATE, START_COUNTER, RESYNC0, RESYNC1, RESYNC2, RESYNC3, WAIT_1, WAIT_2, WAIT_3, NORMAL_OPERATION_1, NORMAL_OPERATION_2); signal SYNC_CURRENT, SYNC_NEXT : SYNC_MACHINE; - attribute syn_enum_encoding : string; - attribute syn_enum_encoding of SYNC_MACHINE : type is "safe"; - attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential"; +-- attribute syn_enum_encoding : string; +-- attribute syn_enum_encoding of SYNC_MACHINE : type is "safe"; +-- attribute syn_enum_encoding of SYNC_MACHINE : type is "sequential"; signal fsm_debug_register : std_logic_vector(3 downto 0); signal resync_counter_up :std_logic; @@ -149,7 +194,7 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is signal tx_k_i : std_logic; signal fifo_opt_empty_synch_synch : std_logic; signal fifo_rd_en_hub : std_logic; - constant SYSTEM : Integer := 1; +-- constant SYSTEM : Integer := 1; signal wait_for_write_up : std_logic; signal wait_for_write_counter : std_logic_vector(28 downto 0); signal link_reset_counter : std_logic_vector(2 downto 0); @@ -168,6 +213,15 @@ architecture flexi_PCS_channel_synch of flexi_PCS_channel_synch is signal cv_counter_reset : std_logic; signal rx_comma : std_logic_vector(1 downto 0); signal rx_comma_synch : std_logic_vector(1 downto 0); + + --crossing clk memory + signal cross_wraddress_i : std_logic_vector(2 downto 0); + signal cross_data_i : std_logic_vector(31 downto 0); + signal cross_rdaddress_i : std_logic_vector(2 downto 0); + signal cross_q_i : std_logic_vector(31 downto 0); + signal rx_comma_synch_err : std_logic; + signal lost_connection_count : std_logic_vector(15 downto 0); + begin --reset from link @@ -212,7 +266,7 @@ begin end if; end process RESET_LINK_ERROR_COUNTER; - LINK_RESET_COUNTER: up_down_counter + LINK_RESET_COUNTER_INST: up_down_counter generic map ( NUMBER_OF_BITS => 3) port map ( @@ -271,7 +325,7 @@ begin LINK_DEBUG(7 downto 4) <= fifo_empty & fifo_full & fifo_opt_empty & fifo_opt_full;--fifo_almost_full & --'0'; LINK_DEBUG(15 downto 8) <= fifo_wr_cnt(3 downto 0) & fifo_rd_cnt(3 downto 0);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); -- LINK_DEBUG(11 downto 8) <= fifo_wr_cnt(4 downto 1);--resync_counter(15 downto 8);--cv_counter(15 downto 12) & cv_counter(3 downto 0); - LINK_DEBUG(31 downto 16) <= fifo_data_in(7 downto 0) & rx_k_synch_i & resync_counter_clr & RESET & CV & resync_counter(0) & MEDIA_STATUS(0) ; + LINK_DEBUG(31 downto 16) <= fifo_data_out(3 downto 0) & lost_connection_count(7 downto 0) & '0' & rx_comma_synch & MEDIA_STATUS(0) ; end if; end if; end process LINK_STATUS; @@ -280,8 +334,34 @@ begin ----------------------------------------------------------------------------- -- data from hub to link ----------------------------------------------------------------------------- + + + CROSS_WR_ADDRESS: process (RX_CLK, RESET) + begin + if rising_edge (RX_CLK) then + if RESET = '1' then + cross_wraddress_i <= "000"; + else + cross_wraddress_i <= cross_wraddress_i + 1; + end if; + end if; + end process CROSS_WR_ADDRESS; + + CROSS_RD_ADDRESS: process (SYSTEM_CLK, RESET) + begin + if rising_edge (SYSTEM_CLK) then + if RESET = '1' then + cross_rdaddress_i <= "000"; + else + cross_rdaddress_i <= cross_rdaddress_i + 1; + end if; + end if; + end process CROSS_RD_ADDRESS; + + cross_data_i <= x"0000000" & "00" & rx_comma; data_opt_in <= "00" & MED_DATA_IN; + SYSTEM_SCM_MEMa: if SYSTEM=1 generate CHANNEL_FIFO_TO_OPT: flexi_PCS_fifo_EBR port map ( @@ -298,6 +378,20 @@ begin AlmostEmpty => fifo_opt_almost_empty, AlmostFull => fifo_opt_almost_full ); + + CROSS_CLK_DPMEM: cross_clk + port map ( + WrAddress => cross_wraddress_i, + Data => cross_data_i, + WrClock => RX_CLK, + WE => '1', + WrClockEn => '1', + RdAddress => cross_rdaddress_i, + RdClock => SYSTEM_CLK, + RdClockEn => '1', + Reset => Reset, + Q => cross_q_i); + end generate SYSTEM_SCM_MEMa; SYSTEM_ECP2_MEMa: if SYSTEM=2 generate @@ -317,6 +411,37 @@ begin AlmostFull => fifo_opt_almost_full ); end generate SYSTEM_ECP2_MEMa; + + SYSTEMT_TRBv2_MEMa: if SYSTEM=6 generate + + CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo + port map ( + din => data_opt_in, + rd_clk => TX_CLK, + rd_en => fifo_opt_not_empty, + rst => fifo_rst, + wr_clk => SYSTEM_CLK, + wr_en => MED_DATAREADY_IN, + almost_empty => fifo_opt_almost_empty, + almost_full => fifo_opt_almost_full, + dout => txd_fifo_out, + empty => fifo_opt_empty, + full => fifo_opt_full); + + TRBv2_CROSS_CLK_INST: trbv2_cross_clk + port map ( + addra => cross_wraddress_i, + addrb => cross_rdaddress_i, + clka => RX_CLK, + clkb => SYSTEM_CLK, + dina => cross_data_i, + dinb => x"00000000", + douta => open, + doutb => cross_q_i, + wea => '1', + web => '0'); + + end generate SYSTEMT_TRBv2_MEMa; DATA_SEND_TO_LINK: process (TX_CLK, RESET, MED_DATAREADY_IN,fifo_opt_empty_synch,fifo_opt_empty_synch_synch) begin @@ -390,6 +515,24 @@ begin AlmostFull => fifo_almost_full ); end generate SYSTEM_ECP2_MEMb; + + SYSTEM_TRBv2: if SYSTEM=6 generate + + CHANNEL_FIFO_TO_FPGA: trbv2_link_fifo + port map ( + din => fifo_data_in, + rd_clk => SYSTEM_CLK, + rd_en => fifo_rd_en, + rst => fifo_rst, + wr_clk => RX_CLK, + wr_en => fifo_wr_en, + almost_empty => fifo_almost_empty, + almost_full => fifo_almost_full, + dout => fifo_data_out, + empty => fifo_empty, + full => fifo_full); + + end generate SYSTEM_TRBv2; not_fifo_empty <= not fifo_empty; RD_FIFO_PULSE: edge_to_pulse @@ -475,6 +618,7 @@ begin end if; end if; end process SAVE_COMA; + SYNC_CLOCK : process (SYSTEM_CLK, RESET) begin @@ -501,7 +645,7 @@ begin resync_counter_clr <= resync_counter_clr_fsm; wait_for_write_up <= wait_for_write_up_fsm; MED_READ_OUT <= MED_READ_OUT_fsm; - rx_comma_synch <= rx_comma; + rx_comma_synch <= cross_q_i(1 downto 0); end if; end if; end process SYNC_CLOCK; @@ -588,6 +732,8 @@ begin SYNC_NEXT <= NORMAL_OPERATION_2; elsif wait_for_write_counter(28)='1' and rx_comma_synch = "10" then SYNC_NEXT <= NORMAL_OPERATION_1; + elsif rx_comma_synch = "11" then + SYNC_NEXT <= START_COUNTER; else SYNC_NEXT <= WAIT_3; end if; @@ -598,6 +744,8 @@ begin resync_counter_up_fsm <= '0'; MED_READ_OUT_fsm <= '1'; if rx_comma_synch = "11" then +-- if MEDIA_STATUS(0) = '1' then + SYNC_NEXT <= START_COUNTER; else SYNC_NEXT <= NORMAL_OPERATION_1; @@ -609,6 +757,7 @@ begin resync_counter_up_fsm <= '0'; MED_READ_OUT_fsm <= '1'; if rx_comma_synch = "11" then +-- if MEDIA_STATUS(0) = '1' then SYNC_NEXT <= START_COUNTER; else SYNC_NEXT <= NORMAL_OPERATION_2; @@ -627,7 +776,7 @@ begin if rising_edge(SYSTEM_CLK) then if RESET = '1' then MED_STAT_OP(9) <= '1'; - elsif fsm_debug_register < 9 then + elsif fsm_debug_register < 9 and fsm_debug_register > 3 then MED_STAT_OP(9) <= diod_counter(23); elsif fsm_debug_register = 9 then MED_STAT_OP(9) <= diod_counter(26); @@ -659,7 +808,7 @@ begin UP_IN => wait_for_write_up, DOWN_IN => '0'); - RESYNC_COUNTER: up_down_counter + RESYNC_COUNTER_INST: up_down_counter generic map ( NUMBER_OF_BITS => 32) port map ( @@ -670,7 +819,8 @@ begin DOWN_IN => '0'); cv_or <= cv_i(0) or cv_i(1); - CV_COUNTER: up_down_counter + + CV_COUNTER_INST: up_down_counter generic map ( NUMBER_OF_BITS => 16) port map ( @@ -679,6 +829,28 @@ begin COUNT_OUT => cv_counter, UP_IN => cv_or, DOWN_IN => '0'); + SYNCH_ERR_COUNT : process (SYSTEM_CLK, RESET) + begin + if rising_edge(SYSTEM_CLK) then + if RESET = '1' then + rx_comma_synch_err <= '0'; + elsif SYNC_CURRENT = NORMAL_OPERATION_1 or SYNC_CURRENT = NORMAL_OPERATION_2 then + rx_comma_synch_err <= rx_comma_synch(1) and rx_comma_synch(0); + else + rx_comma_synch_err <= '0'; + end if; + end if; + end process SYNCH_ERR_COUNT; + + LINK_CONECTION_LOST_COUNTER: up_down_counter + generic map ( + NUMBER_OF_BITS => 16) + port map ( + CLK => RX_CLK, + RESET => RESET, + COUNT_OUT => lost_connection_count, + UP_IN => rx_comma_synch_err, + DOWN_IN => '0'); WRITE_COUNTER: up_down_counter generic map ( diff --git a/optical_link/flexi_PCS_synch.vhd b/optical_link/flexi_PCS_synch.vhd index 5dd12e3..39c2cc8 100644 --- a/optical_link/flexi_PCS_synch.vhd +++ b/optical_link/flexi_PCS_synch.vhd @@ -9,7 +9,9 @@ use work.trb_net_std.all; entity flexi_PCS_synch is generic ( - HOW_MANY_CHANNELS : positive); + HOW_MANY_CHANNELS : positive; + SYSTEM : positive + ); port ( RESET : in std_logic; SYSTEM_CLK : in std_logic; @@ -40,6 +42,9 @@ end flexi_PCS_synch; architecture flexi_PCS_synch of flexi_PCS_synch is component flexi_PCS_channel_synch + generic ( + SYSTEM : positive + ); port ( RESET : in std_logic; SYSTEM_CLK : in std_logic; @@ -73,6 +78,9 @@ begin begin CHANNEL_GENERATE: flexi_PCS_channel_synch + generic map ( + SYSTEM => SYSTEM + ) port map ( RESET => RESET, SYSTEM_CLK => SYSTEM_CLK, diff --git a/optical_link/hub.lpf b/optical_link/hub.lpf index ebb3bd4..bbc963c 100644 --- a/optical_link/hub.lpf +++ b/optical_link/hub.lpf @@ -466,6 +466,8 @@ FREQUENCY NET "rx_clk_i_15" 100.000000MHz; FREQUENCY PORT "ref_pclk_1/QUAD_GENERATE_1_QUAD" 100.000000MHz; FREQUENCY PORT "ref_pclk_2/QUAD_GENERATE_2_QUAD" 100.000000MHz; FREQUENCY PORT "ref_pclk_3/QUAD_GENERATE_3_QUAD" 100.000000MHz; +FREQUENCY PORT "ref_pclk_0/QUAD_GENERATE_0_QUAD" 100.000000MHz; + #FREQUENCY PORT "rxa_pclk_a/quad_a" 100.000000MHz; #FREQUENCY PORT "rx_1_sclk_a/quad_a" 100.000000MHz; #FREQUENCY PORT "rx_2_sclk_a/quad_a" 100.000000MHz; diff --git a/optical_link/hub.vhd b/optical_link/hub.vhd index ee86ec5..1dd4586 100644 --- a/optical_link/hub.vhd +++ b/optical_link/hub.vhd @@ -184,7 +184,8 @@ architecture hub of hub is component flexi_PCS_synch generic ( - HOW_MANY_CHANNELS : positive); + HOW_MANY_CHANNELS : positive; + SYSTEM : positive ); port ( RESET : in std_logic; SYSTEM_CLK : in std_logic; @@ -665,7 +666,8 @@ begin --sim-- end generate SIMULATION_CONNECTION; FLEXI_PCS_INT : flexi_PCS_synch generic map ( - HOW_MANY_CHANNELS => HOW_MANY_CHANNELS) + HOW_MANY_CHANNELS => HOW_MANY_CHANNELS, + SYSTEM => 1) port map ( RESET => global_reset_i, SYSTEM_CLK => LVDS_CLK_200P, @@ -711,12 +713,12 @@ begin port map ( CLK => LVDS_CLK_200P, RESET => global_reset_i, --- DATA_IN => med_data_out_i, - DATA_IN => med_data_out_i_test, + DATA_IN => med_data_out_i, +-- DATA_IN => med_data_out_i_test, DATA_OUT => med_data_in_i, DATA_IN_VALID => med_dataready_out_i, --- SEND_DATA => med_dataready_in_i, - SEND_DATA => med_dataready_in_i_test, + SEND_DATA => med_dataready_in_i, +-- SEND_DATA => med_dataready_in_i_test, ENABLE_CHANNELS => fpga_register_06_i(15 downto 0), READ_DATA => med_read_in_i, HUB_DEBUG => hub_debug_i @@ -881,7 +883,7 @@ begin -- -- fpga_register_08_i <= rxd_i(63 downto 32); -- fpga_register_0a_i(15 downto 0) <= cv_i(7 downto 0) & rx_k_i(3 downto 0) & "0000"; - + COUNT_LVL1_START: process (LVDS_CLK_200P, global_reset_i ) begin @@ -959,7 +961,7 @@ begin begin -- lok_i(synch_fsm_state+1) <= not link_debug_i(2+synch_fsm_state*31); lok_i(synch_fsm_state+1) <= med_stat_op_i(9 + synch_fsm_state*16); - media_status_i(synch_fsm_state*16) <= '0';--SFP_LOS(synch_fsm_state); + media_status_i(synch_fsm_state*16) <= SFP_LOS(synch_fsm_state+1); end generate LOK_STATUS_DIOD_EN; -- LOK_STATUS_REGISTER_0 : for synch_fsm_state in 0 to (HOW_MANY_CHANNELS-1 mod 8) generate @@ -1007,19 +1009,19 @@ begin end if; end if; end process CV_COUNTERaab; - RT(8) <= cv_counter(23); - RT(9) <= med_read_in_i(0); - RT(16 downto 10) <= link_debug_i(7 downto 1); - RT(2) <= flexi_pcs_ref_clk;--cv_counter(0); - RT(1) <= not switch_rx_clk;--ref_pclk(0); +-- RT(8) <= cv_counter(23); +-- RT(9) <= med_read_in_i(0); +-- RT(16 downto 10) <= link_debug_i(7 downto 1); +-- RT(2) <= flexi_pcs_ref_clk;--cv_counter(0); +-- RT(1) <= not switch_rx_clk;--ref_pclk(0); - RT(3) <= LVDS_CLK_200P; - - RT(4) <= rx_k_i(0); +-- RT(3) <= LVDS_CLK_200P; - RT(5) <= med_dataready_out_i(0);--serdes_ref_clk; - RT(6) <= med_data_out_i(0);--serdes_ref_clks; - RT(7) <= med_data_out_i(1);--serdes_ref_lock; +-- RT(4) <= rx_k_i(0); +-- RT(5) <= med_dataready_out_i(0);--serdes_ref_clk; +-- RT(6) <= med_data_out_i(0);--serdes_ref_clks; +-- RT(7) <= med_data_out_i(1);--serdes_ref_lock; + RT <= (others => '1'); end hub; diff --git a/optical_link/hub_syn.prj b/optical_link/hub_syn.prj index 1b25a03..10f1458 100644 --- a/optical_link/hub_syn.prj +++ b/optical_link/hub_syn.prj @@ -20,6 +20,7 @@ add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_api_base.vhd" add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_obuf.vhd" add_file -vhdl -lib work "/home/marek/trbnet/trb_net16_ibuf.vhd" add_file -vhdl -lib work "./simple_hub.vhd" +add_file -vhdl -lib work "./cross_clk.vhd" add_file -vhdl -lib work "/home/marek/trbv2/etrax_interfacev2.vhd" add_file -vhdl -lib work "./simpleupcounter_32bit.vhd" add_file -vhdl -lib work "./hub_etrax_interface.vhd" -- 2.43.0