From 528d3842214ad0d436119f537d6e984f908e7a17 Mon Sep 17 00:00:00 2001
From: Jan Michel <j.michel@gsi.de>
Date: Tue, 31 May 2016 14:38:29 +0200
Subject: [PATCH] Some cleanup and reduce of logic usage

---
 code/uart_sctrl.vhd | 14 +++++++-------
 mboasd8/mbo.vhd     | 25 ++++++++++++++++---------
 2 files changed, 23 insertions(+), 16 deletions(-)

diff --git a/code/uart_sctrl.vhd b/code/uart_sctrl.vhd
index 210709b..1f0ff38 100644
--- a/code/uart_sctrl.vhd
+++ b/code/uart_sctrl.vhd
@@ -109,21 +109,22 @@ begin
       end if;
 
     when START =>
+      if rx_data >= x"40" then  
+        tmp2 := unsigned(rx_data) + x"09";
+      else
+        tmp2 := unsigned(rx_data);
+      end if;
       if rx_ready = '1' then
-        if rx_data >= x"40" then  
-          tmp2 := unsigned(rx_data) + x"09";
-        else
-          tmp2 := unsigned(rx_data);
-        end if;
         state <= START2;
       end if;      
         
     when START2 =>    
       addr_data(bytecount*4+3 downto bytecount*4) <= std_logic_vector(tmp2(3 downto 0));
+      bytecount <= bytecount - 1;
+      
       if (bytecount = 0 and cmd_wr = '1') or (bytecount = 8 and cmd_rd = '1') then
         state <= DO_COMMAND;
       else
-        bytecount <= bytecount - 1;
         state <= START;
       end if;
       
@@ -135,7 +136,6 @@ begin
       
   if RESET = '1' or timeout = '1' then
     state <= IDLE;
-    timer <= (others => '0');
   end if;
 end process;  
       
diff --git a/mboasd8/mbo.vhd b/mboasd8/mbo.vhd
index 78746b4..aa6fd3b 100644
--- a/mboasd8/mbo.vhd
+++ b/mboasd8/mbo.vhd
@@ -72,11 +72,12 @@ architecture arch of mbo is
   signal timer_i : unsigned(31 downto 0) := (others => '0');
   signal led_highz : std_logic;
  
-  type led_timer_t is array(0 to 3) of unsigned(24 downto 0);
+  type led_timer_t is array(0 to 3) of unsigned(5 downto 0);
   signal led_timer : led_timer_t;
   signal led_state : std_logic_vector(3 downto 0);
+  signal led_clk_en : std_logic;
  
-  type counter_arr is array(0 to 7) of unsigned(23 downto 0);
+  type counter_arr is array(0 to 7) of unsigned(15 downto 0);
   signal input_counter    : counter_arr;
   signal select_i : std_logic_vector(3 downto 0);
   signal readcounter : unsigned(15 downto 0);
@@ -130,12 +131,12 @@ PROC_REGS : process begin
         f_read <= '1';
         bus_ready <= '0';
       when x"ee" => uart_tx_data <= sed_debug;
-      when x"ff" => uart_tx_data(15 downto 0) <= std_logic_vector(readcounter);
-                    readcounter <= readcounter + 1;
+--       when x"ff" => uart_tx_data(15 downto 0) <= std_logic_vector(readcounter);
+--                     readcounter <= readcounter + 1;
     end case;
     if uart_addr(7 downto 4) = x"2" then
-      uart_tx_data(31 downto 24) <= uart_addr(3 downto 0) & x"0";
-      uart_tx_data(23 downto 0)  <= std_logic_vector(input_counter(to_integer(unsigned(uart_addr(3 downto 0))))); 
+      uart_tx_data(31 downto 16) <= uart_addr(3 downto 0) & x"000";
+      uart_tx_data(15 downto 0)  <= std_logic_vector(input_counter(to_integer(unsigned(uart_addr(3 downto 0))))); 
     end if;
   elsif bus_write = '1' then
     case uart_addr is
@@ -258,13 +259,19 @@ THE_TDC :  entity work.ffarray
 
   PROC_LED_STATE : process begin
     wait until rising_edge(clk_i);
+    if timer_i(18 downto 0) = 0 then
+      led_clk_en <= '1';
+    else
+      led_clk_en <= '0';
+    end if;  
+    
     for i in 0 to 3 loop
-      if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(23 downto 21) > 0) then
+      if (input_reg_2(i) xor input_reg_1(i)) = '1' and (led_timer(i)(4 downto 2) > 0) then
         led_state(i) <= not led_state(i);
         led_timer(i) <= 0;
-      elsif led_timer(i)(23) = '1' then
+      elsif led_timer(i)(4) = '1' then
         led_state(i) <= input_reg_1(i);
-      else
+      elsif led_clk_en = '1' then
         led_timer(i) <= led_timer(i) + 1;
       end if;
     end loop;
-- 
2.43.0