From 52ce6859375e02a56f3f52b616577318a31d2d27 Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Fri, 17 Jul 2020 09:32:50 +0200 Subject: [PATCH] a trb3sc with the CRI interface to multiple combiner ( CTS in combiner) boards and the readout of data. --- criInterface/compile.pl | 1 + criInterface/config.vhd | 163 ++++ criInterface/config_compile_frankfurt.pl | 20 + criInterface/config_compile_giessen.pl | 28 + criInterface/par.p2t | 31 + criInterface/trb3sc_criInterface.lpf | 96 +++ criInterface/trb3sc_criInterface.prj | 264 +++++++ criInterface/trb3sc_criInterface.vhd | 934 +++++++++++++++++++++++ 8 files changed, 1537 insertions(+) create mode 120000 criInterface/compile.pl create mode 100644 criInterface/config.vhd create mode 100644 criInterface/config_compile_frankfurt.pl create mode 100644 criInterface/config_compile_giessen.pl create mode 100644 criInterface/par.p2t create mode 100644 criInterface/trb3sc_criInterface.lpf create mode 100644 criInterface/trb3sc_criInterface.prj create mode 100644 criInterface/trb3sc_criInterface.vhd diff --git a/criInterface/compile.pl b/criInterface/compile.pl new file mode 120000 index 0000000..4456748 --- /dev/null +++ b/criInterface/compile.pl @@ -0,0 +1 @@ +../scripts/compile.pl \ No newline at end of file diff --git a/criInterface/config.vhd b/criInterface/config.vhd new file mode 100644 index 0000000..8b3865e --- /dev/null +++ b/criInterface/config.vhd @@ -0,0 +1,163 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; +use work.trb_net16_hub_func.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of design configuration +------------------------------------------------------------------------------ + +--design options: backplane or front SFP, with or without GBE + constant USE_BACKPLANE : integer := c_NO; + constant INCLUDE_GBE : integer := c_NO; + +--Runs with 120 MHz instead of 100 MHz + constant USE_120_MHZ : integer := c_NO; + constant USE_200MHZOSCILLATOR : integer := c_YES; + constant USE_EXTERNAL_CLOCK : integer := c_YES; --'no' not implemented. + constant CLOCK_FAST_SELECT : integer := c_NO; --fast clock select (135us) or slow (280ms)? + +--Use sync mode, RX clock for all parts of the FPGA + constant USE_RXCLOCK : integer := c_NO; + +--Address settings + constant INIT_ADDRESS : std_logic_vector := x"F352"; + + + + constant INCLUDE_UART : integer := c_YES; + constant INCLUDE_SPI : integer := c_YES; + constant INCLUDE_LCD : integer := c_NO; + constant INCLUDE_DEBUG_INTERFACE: integer := c_YES; + + --input monitor and trigger generation logic + constant INCLUDE_TRIGGER_LOGIC : integer := c_NO; + constant INCLUDE_STATISTICS : integer := c_NO; + constant TRIG_GEN_INPUT_NUM : integer := 0; + constant TRIG_GEN_OUTPUT_NUM : integer := 0; + constant MONITOR_INPUT_NUM : integer := 0; + +------------------------------------------------------------------------------ +--End of design configuration +------------------------------------------------------------------------------ + + type data_t is array (0 to 1023) of std_logic_vector(7 downto 0); + constant LCD_DATA : data_t := ( + x"36",x"48",x"3A",x"55",x"29",x"2A",x"00",x"00", --config don't touch + x"00",x"EF",x"2B",x"00",x"00",x"01",x"3F",x"2C", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + x"00",x"00",x"00",x"00",x"00",x"00",x"00",x"00", --config don't touch + + x"48", x"75", x"62", x"41", x"64", x"64", x"4f", x"6e", x"0a", + x"0a", + x"41", x"64", x"64", x"72", x"65", x"73", x"73", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"80", x"0a", + x"43", x"6f", x"6d", x"70", x"69", x"6c", x"65", x"54", x"69", x"6d", x"65", x"20", x"20", x"84", x"83", x"0a", + x"54", x"69", x"6d", x"65", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"20", x"82", x"81", x"0a", + others => x"00"); + + + +--With GbE: +-- for MII_NUMBER=5 (4 downlinks, 1 uplink): +-- port 0,1,2,3: downlinks to other FPGA +-- port MII-1: LVL1/Data channel on uplink to CTS, but internal endpoint on SCTRL +-- port MII: SCTRL channel on uplink to CTS +-- port MII+1: SCTRL channel from GbE interface + + type hub_mii_t is array(0 to 3) of integer; + type hub_ct is array(0 to 16) of integer; + type hub_cfg_t is array(0 to 3) of hub_ct; + type hw_info_t is array(0 to 3) of std_logic_vector(31 downto 0); + type intlist_t is array(0 to 7) of integer; + + + --order: no backplane, no GBE 8x AddOn, SFP downlink, SFP uplink + -- backplane, no GBE 8x AddOn, 2x SFP downlink, backplane uplink + -- no backplane, GBE 7x AddOn, 1x SFP uplink, GBE sctrl + -- backplane, GBE 8x AddOn, backplane uplink, GBE sctrl + + constant INTERFACE_NUM_ARR : hub_mii_t := (10,11,8,9); +-- 0 1 2 3 4 5 6 7 8 9 a b c d e f + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,1,1,1,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,1,1,1,0,1,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,1,0,1,0,0,0,0,0), + (1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,1,1,0,0,0,0,0,0)); + + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct; + constant IS_DOWNLINK : hub_ct; + constant IS_UPLINK_ONLY : hub_ct; + +------------------------------------------------------------------------------ +--Select settings by configuration +------------------------------------------------------------------------------ + + constant HW_INFO_BASE : unsigned(31 downto 0) := x"9200A000"; + + constant CLOCK_FREQUENCY_ARR : intlist_t := (100,120, others => 0); + constant MEDIA_FREQUENCY_ARR : intlist_t := (200,240, others => 0); + + --declare constants, filled in body + constant HARDWARE_INFO : std_logic_vector(31 downto 0); + constant CLOCK_FREQUENCY : integer; + constant MEDIA_FREQUENCY : integer; + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0); + constant BROADCAST_SPECIAL_ADDR : std_logic_vector; + +end; + +package body config is +--compute correct configuration mode + + constant HARDWARE_INFO : std_logic_vector(31 downto 0) := std_logic_vector( + HW_INFO_BASE ); + constant CLOCK_FREQUENCY : integer := CLOCK_FREQUENCY_ARR(USE_120_MHZ); + constant MEDIA_FREQUENCY : integer := MEDIA_FREQUENCY_ARR(USE_120_MHZ); + + constant CFG_MODE : integer := INCLUDE_GBE*2 + USE_BACKPLANE; + + constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); + constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); + constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); + constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); + constant BROADCAST_SPECIAL_ADDR : std_logic_vector := std_logic_vector(to_unsigned(100+CFG_MODE,8)); + + +function generateIncludedFeatures return std_logic_vector is + variable t : std_logic_vector(63 downto 0); + begin + t := (others => '0'); + t(63 downto 56) := std_logic_vector(to_unsigned(1,8)); --table version 1 + if INCLUDE_GBE = c_YES then + t(22 downto 16) := "0100111"; --sctrl via GbE + end if; + t(23 downto 23) := std_logic_vector(to_unsigned(INCLUDE_GBE,1)); + t(27 downto 24) := std_logic_vector(to_unsigned(INTERFACE_NUM-USE_BACKPLANE,4)); --num SFPs with TrbNet + t(28 downto 28) := std_logic_vector(to_unsigned(USE_BACKPLANE,1)); + t(40 downto 40) := std_logic_vector(to_unsigned(INCLUDE_LCD,1)); + t(42 downto 42) := std_logic_vector(to_unsigned(INCLUDE_SPI,1)); + t(43 downto 43) := std_logic_vector(to_unsigned(INCLUDE_UART,1)); + t(44 downto 44) := std_logic_vector(to_unsigned(INCLUDE_STATISTICS,1)); + t(51 downto 48) := std_logic_vector(to_unsigned(INCLUDE_TRIGGER_LOGIC,4)); + t(52 downto 52) := std_logic_vector(to_unsigned(USE_120_MHZ,1)); + t(53 downto 53) := std_logic_vector(to_unsigned(USE_RXCLOCK,1)); + t(54 downto 54) := std_logic_vector(to_unsigned(USE_EXTERNAL_CLOCK,1)); + t(55 downto 55) := std_logic_vector(to_unsigned(USE_200MHZOSCILLATOR,1)); + return t; + end function; + + constant INCLUDED_FEATURES : std_logic_vector(63 downto 0) := generateIncludedFeatures; + +end package body; diff --git a/criInterface/config_compile_frankfurt.pl b/criInterface/config_compile_frankfurt.pl new file mode 100644 index 0000000..320a75e --- /dev/null +++ b/criInterface/config_compile_frankfurt.pl @@ -0,0 +1,20 @@ +TOPNAME => "trb3sc_criInterface", +lm_license_file_for_synplify => "27020\@jspc29", #"27000\@lxcad01.gsi.de"; +lm_license_file_for_par => "1702\@hadeb05.gsi.de", +lattice_path => '/d/jspc29/lattice/diamond/3.10_x64', +synplify_path => '/d/jspc29/lattice/synplify/O-2018.09-SP1', +#synplify_path => '/d/jspc29/lattice/synplify/L-2016.09-1/', +#synplify_command => "/d/jspc29/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/d/jspc29/lattice/synplify/J-2014.09-SP2/bin/synplify_premier_dp", + +nodelist_file => 'nodelist_frankfurt.txt', + + +#Include only necessary lpf files +#pinout_file => '', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +twr_number_of_errors => 20, diff --git a/criInterface/config_compile_giessen.pl b/criInterface/config_compile_giessen.pl new file mode 100644 index 0000000..a369eff --- /dev/null +++ b/criInterface/config_compile_giessen.pl @@ -0,0 +1,28 @@ +#Familyname => 'ECP5UM', +#Devicename => 'LFE5UM-85F', +#Package => 'CABGA381', +#Speedgrade => '8', + +TOPNAME => "trb3sc_criInterface", +lm_license_file_for_synplify => "7788\@fb07pc-u102325", +lm_license_file_for_par => "7788\@fb07pc-u102325", +lattice_path => '/usr/local/diamond/3.11_x64/', +synplify_path => '/usr/local/diamond/3.11_x64/synpbase', +#synplify_command => "/opt/lattice/diamond/3.5_x64/bin/lin64/synpwrap -fg -options", +#synplify_command => "/opt/synplicity/O-2018.09-SP1/bin/synplify_premier_dp", +#synplify_command => "synpwrap -prj ../trb3sc_criInterface.prj", +synplify_command => "synpwrap -fg -options", + +nodelist_file => '../nodes_lxhadeb07.txt', + + +#Include only necessary lpf files +pinout_file => 'trb3sc_hub', #name of pin-out file, if not equal TOPNAME +include_TDC => 0, +include_GBE => 0, + +#Report settings +firefox_open => 0, +#twr_number_of_errors => 20, +#no_ltxt2ptxt => 1, #if there is no serdes being used +#make_jed => 1, diff --git a/criInterface/par.p2t b/criInterface/par.p2t new file mode 100644 index 0000000..2be9006 --- /dev/null +++ b/criInterface/par.p2t @@ -0,0 +1,31 @@ +# -w +# -i 15 +# -l 5 +# -y +# -s 12 +# -t 26 +# -c 1 +# -e 2 +# #-g guidefile.ncd +# #-m nodelist.txt +# # -w +# # -i 6 +# # -l 5 +# # -n 1 +# # -t 1 +# # -s 1 +# # -c 0 +# # -e 0 +# # +# +-w +#-y +-l 5 +#-m nodelist.txt # Controlled by the compile.pl script. +#-n 1 # Controlled by the compile.pl script. +-s 10 +-t 3 +-c 0 +-e 0 +-i 6 +-exp parCDP=1:parCDR=1:parPlcInLimit=0:parPlcInNeighborSize=1:parPathBased=ON:parHold=ON:parHoldLimit=10000:paruseNBR=1:parHold=ON:parHoldLimit=10000:parCDP=auto:parCDR=1:parPathBased=OFF:paruseNBR=1:parHold=2 diff --git a/criInterface/trb3sc_criInterface.lpf b/criInterface/trb3sc_criInterface.lpf new file mode 100644 index 0000000..1b02182 --- /dev/null +++ b/criInterface/trb3sc_criInterface.lpf @@ -0,0 +1,96 @@ +LOCATE COMP "gen_PCSA.THE_MEDIA_PCSA/gen_pcs0.THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST" SITE "PCSB" ; +LOCATE COMP "THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST" SITE "PCSC" ; +LOCATE COMP "gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST" SITE "PCSD" ; + + + +REGION "MEDIA_DOWN1" "R102C20D" 13 120; +LOCATE UGROUP "gen_PCSA.THE_MEDIA_PCSA/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "THE_MEDIA_4_PCSC/media_interface_group" REGION "MEDIA_DOWN1" ; +LOCATE UGROUP "gen_PCSD.THE_MEDIA_4_PCSD/media_interface_group" REGION "MEDIA_DOWN1" ; + +FREQUENCY NET "gen_GBE.GBE/imp_gen.serdes_intclk_gen.PCS_SERDES/clk_int.SERDES_GBE/sd_rx_clk_1" 125.0 MHz; +FREQUENCY NET "gen_GBE.GBE/clk_125_rx_from_pcs[3]" 125 MHz; + +MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSA.THE_MEDIA_PCSA/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSA.THE_MEDIA_PCSA/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSA.THE_MEDIA_PCSA/sci_read_i"; + +MULTICYCLE TO CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_BKPL.THE_MEDIA_4_PCSB/sci_read_i"; + +MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/sci_read_i"; + +MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/sci*" 20 ns; +MULTICYCLE FROM CELL "THE_MEDIA_4_PCSC/sci*" 20 ns; +MULTICYCLE TO CELL "THE_MEDIA_4_PCSC/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_write_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_write_i"; +BLOCK PATH TO CLKNET "THE_MEDIA_4_PCSC/sci_read_i"; +BLOCK PATH FROM CLKNET "THE_MEDIA_4_PCSC/sci_read_i"; + +MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns; +MULTICYCLE FROM CELL "gen_PCSD.THE_MEDIA_4_PCSD/sci*" 20 ns; +MULTICYCLE TO CELL "gen_PCSD.THE_MEDIA_4_PCSD/PROC_SCI_CTRL.wa*" 20 ns; +BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i"; +BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_write_i"; +BLOCK PATH TO CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i"; +BLOCK PATH FROM CLKNET "gen_PCSD.THE_MEDIA_4_PCSD/sci_read_i"; + + +MULTICYCLE TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSA.THE_MEDIA_PCSA/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSB_BKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSB_noBKPL.THE_MEDIA_4_PCSB/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC THE_MEDIA_4_PCSC/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + +MULTICYCLE TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; +MAXDELAY TO ASIC gen_PCSD.THE_MEDIA_4_PCSD/THE_SERDES/PCSD_INST PIN SCIRD 15 ns; + + + +# PROHIBIT PRIMARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_INTERFACE/clk_rx_full" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[0]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[1]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[2]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_tx_full[3]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[0]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[1]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[2]" ; +# PROHIBIT PRIMARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ; +# PROHIBIT SECONDARY NET "THE_MEDIA_4_DOWN/clk_rx_full[3]" ; +# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_rx_full" 200 MHz; # HOLD_MARGIN 500 ps +# FREQUENCY NET "THE_MEDIA_INTERFACE/clk_tx_full" 200 MHz; # HOLD_MARGIN 500 ps diff --git a/criInterface/trb3sc_criInterface.prj b/criInterface/trb3sc_criInterface.prj new file mode 100644 index 0000000..fcfcf5e --- /dev/null +++ b/criInterface/trb3sc_criInterface.prj @@ -0,0 +1,264 @@ + +# implementation: "workdir" +impl -add workdir -type fpga + +# device options +set_option -technology LATTICE-ECP3 +set_option -part LFE3_150EA +set_option -package FN1156C +set_option -speed_grade -8 +set_option -part_companion "" + +# compilation/mapping options +set_option -default_enum_encoding sequential +set_option -symbolic_fsm_compiler 1 +set_option -top_module "trb3sc_criInterface" +set_option -resource_sharing false + +# map options +set_option -frequency 120 +set_option -fanout_limit 100 +set_option -disable_io_insertion 0 +set_option -retiming 1 +set_option -pipe 1 +set_option -force_gsr false +set_option -fixgatedclocks 3 +set_option -fixgeneratedclocks 3 +set_option -compiler_compatible true + +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 + +# simulation options +set_option -write_verilog 0 +set_option -write_vhdl 1 + +# automatic place and route (vendor) options +set_option -write_apr_constraint 0 + +# set result format/file last +project -result_format "edif" +project -result_file "workdir/trb3sc_criInterface.edf" + +#implementation attributes + +set_option -vlog_std v2001 +set_option -project_relative_includes 1 +impl -active "workdir" + +#################### + + + +#Packages +add_file -vhdl -lib work "workdir/version.vhd" +add_file -vhdl -lib work "config.vhd" +add_file -vhdl -lib work "../../trb3/base/trb3_components.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" + +#Basic Infrastructure +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out100.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in200_out200.vhd" +add_file -vhdl -lib work "../../trb3sc/cores/pll_in240_out240.vhd" +add_file -vhdl -lib work "../../trb3/base/cores/pll_200_4.vhd" +add_file -vhdl -lib work "../../trb3sc/code/clock_reset_handler.vhd" +add_file -vhdl -lib work "../../trb3sc/code/load_settings.vhd" +add_file -vhdl -lib work "../../trb3sc/code/spi_master_generic.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_to_trigger_logic_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/input_statistics.vhd" +add_file -vhdl -lib work "../../trbnet/special/trb_net_reset_handler.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_flash_and_fpga_reload_record.vhd" +add_file -vhdl -lib work "../../trb3/base/code/sedcheck.vhd" +add_file -vhdl -lib work "../../trbnet/basics/priority_arbiter.vhd" + + +#Fifos +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/spi_dpram_32_to_8.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x1k.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16bit_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x4k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x8k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x16k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_36x32k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x256_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x512_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x1k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_18x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp2m/fifo/fifo_var_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_16x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp3_fifo_18x16_dualport_oreg.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/ram_18x256_oreg.vhd" + + +#Flash & Reload, Tools +add_file -vhdl -lib work "../../trbnet/special/slv_register.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_master.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_slim.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_databus_memory.vhd" +add_file -vhdl -lib work "../../trbnet/special/fpga_reboot.vhd" +add_file -vhdl -lib work "../../trb3sc/code/trb3sc_tools.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trb3sc/code/lcd.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/special/spi_ltc2600.vhd" + +#SlowControl files +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regio_bus_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_regIO.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_onewire.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_addresses.vhd" + +#Media interface +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_define.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/rx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/tx_reset_fsm.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/sci_reader.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/sync/med_sync_control.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_0.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_sync_4_slave3.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/med_ecp3_sfp_sync_4_slave3.vhd" + +#TrbNet Endpoint +add_file -vhdl -lib work "../../trbnet/trb_net16_term_buf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_CRC8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/rom_16x8.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/state_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x8_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_16x16_dp.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf5.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_sbuf6.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_sbuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_encoder.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_dummy_fifo.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_term_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_priority_arbiter.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net_pattern_gen.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf_nodata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_obuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ibuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_api_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_iobuf.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_io_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_trigger.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_ipudata.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full.vhd" +add_file -vhdl -lib work "../../trbnet/basics/signal_sync.vhd" +add_file -vhdl -lib work "../../trbnet/basics/ram_dp_rw.vhd" +add_file -vhdl -lib work "../../trbnet/basics/pulse_stretch.vhd" + +#Hub +add_file -vhdl -lib work "../../trbnet/trb_net16_api_ipu_streaming.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_streaming_port_sctrl_record.vhd" +add_file -vhdl -lib work "../../cri/src/hub/trb_net16_cri_hub_base3.vhd" +add_file -vhdl -lib work "../../cri/src/hub/trb_net16_cri_hub_slwcntrl.vhd" +#add_file -vhdl -lib work "../../trbnet/trb_net16_hub_base.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_logic_2.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_hub_ipu_logic.vhd" +add_file -vhdl -lib work "../../trbnet/basics/wide_adder_17x16.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_19x16.vhd" +add_file -vhdl -lib work "../../cri/src/cri_data_receiver.vhd" + + +#GbE +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_med_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_multiplexer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_ipu_dummy.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_receiver.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_receive_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_main_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_mac_control.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_prioritizer.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_protocol_selector.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_type_validator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_trans.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_frame_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_transmit_control2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_ipu_interface.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_event_constr.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net16_gbe_setup.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/base/ip_configurator.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_ARP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Ping.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_DHCP.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_SCTRL.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_TrbNetData.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_KillPing.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/protocols/trb_net16_gbe_response_constructor_Forward.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/media/serdes_gbe_4ch.vhd" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/sgmii_channel_smi.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_pcs.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/reset_controller_cdr.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/register_interface_hb.v" +add_file -verilog -lib work "../../trbnet/gbe_trb/media/rate_resolution.v" + +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4096x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x32x8.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_512x72.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx16x8_mb2.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2048x8x16.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_65536x18x9.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/slv_mac_memory.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/ip_mem.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_32kx18x9_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_64kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_8kx9_af_cnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_2kx9x18_wcnt.vhd" +add_file -vhdl -lib work "../../trbnet/gbe_trb/ipcores/ecp3/fifo_4kx18x9_wcnt.vhd" + + +add_file -vhdl -lib work "../../trbnet/special/handler_lvl1.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_data.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_ipu.vhd" +add_file -vhdl -lib work "../../trbnet/special/handler_trigger_and_data.vhd" +add_file -vhdl -lib work "../../trbnet/trb_net16_endpoint_hades_full_handler_record.vhd" +add_file -vhdl -lib work "../../trbnet/special/bus_register_handler.vhd" + + + + +add_file -vhdl -lib work "./trb3sc_criInterface.vhd" +#add_file -fpga_constraint "./synplify.fdc" + + + diff --git a/criInterface/trb3sc_criInterface.vhd b/criInterface/trb3sc_criInterface.vhd new file mode 100644 index 0000000..81b4b8d --- /dev/null +++ b/criInterface/trb3sc_criInterface.vhd @@ -0,0 +1,934 @@ +library ieee; +use ieee.std_logic_1164.all; +use ieee.numeric_std.all; + +library work; +use work.version.all; +use work.config.all; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.trb_net16_hub_func.all; +use work.version.all; +use work.trb_net_gbe_components.all; +use work.med_sync_define.all; + +entity trb3sc_criInterface is + port( + CLK_SUPPL_PCLK : in std_logic; --125 MHz for GbE + CLK_CORE_PCLK : in std_logic; --Main Oscillator + CLK_EXT_PLL_LEFT : in std_logic; --External Clock + + --Additional IO + HDR_IO : inout std_logic_vector(10 downto 1); + BACK_LVDS : inout std_logic_vector( 1 downto 0); + BACK_GPIO : inout std_logic_vector( 3 downto 0); + + --LED + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + LED_RED : out std_logic; + LED_RJ_GREEN : out std_logic_vector( 1 downto 0); + LED_RJ_RED : out std_logic_vector( 1 downto 0); + LED_WHITE : out std_logic_vector( 1 downto 0); + LED_SFP_GREEN : out std_logic_vector( 1 downto 0); + LED_SFP_RED : out std_logic_vector( 1 downto 0); + + --SFP + SFP_LOS : in std_logic_vector( 1 downto 0); + SFP_MOD0 : in std_logic_vector( 1 downto 0); + SFP_MOD1 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_MOD2 : inout std_logic_vector( 1 downto 0) := (others => 'Z'); + SFP_TX_DIS : out std_logic_vector( 1 downto 0) := (others => '0'); + + LED_HUB_LINKOK : out std_logic_vector(8 downto 1); + LED_HUB_RX : out std_logic_vector(8 downto 1); + LED_HUB_TX : out std_logic_vector(8 downto 1); + HUB_MOD0 : in std_logic_vector(8 downto 1); + HUB_MOD1 : inout std_logic_vector(8 downto 1); + HUB_MOD2 : inout std_logic_vector(8 downto 1); + HUB_TXDIS : out std_logic_vector(8 downto 1); + HUB_LOS : in std_logic_vector(8 downto 1); + + --Serdes switch + PCSSW_ENSMB : out std_logic; + PCSSW_EQ : out std_logic_vector( 3 downto 0); + PCSSW_PE : out std_logic_vector( 3 downto 0); + PCSSW : out std_logic_vector( 7 downto 0); + + --ADC + ADC_CLK : out std_logic; + ADC_CS : out std_logic; + ADC_DIN : out std_logic; + ADC_DOUT : in std_logic; + + --Flash, 1-wire, Reload + FLASH_CLK : out std_logic; + FLASH_CS : out std_logic; + FLASH_IN : out std_logic; + FLASH_OUT : in std_logic; + PROGRAMN : out std_logic; + ENPIRION_CLOCK : out std_logic; + TEMPSENS : inout std_logic; + + --Test Connectors + TEST_LINE : out std_logic_vector(15 downto 0) + ); + + + attribute syn_useioff : boolean; + attribute syn_useioff of FLASH_CLK : signal is true; + attribute syn_useioff of FLASH_CS : signal is true; + attribute syn_useioff of FLASH_IN : signal is true; + attribute syn_useioff of FLASH_OUT : signal is true; + + + +end entity; + +architecture trb3sc_arch of trb3sc_criInterface is + attribute syn_keep : boolean; + attribute syn_preserve : boolean; + + signal clk_sys, clk_full, clk_full_osc : std_logic; + signal GSR_N : std_logic; + signal reset_i : std_logic; + signal clear_i : std_logic; + signal do_reboot_i, reboot_from_gbe : std_logic; + signal external_reset_i : std_logic; + + signal time_counter : unsigned(31 downto 0) := (others => '0'); + signal led : std_logic_vector(1 downto 0); + signal debug_clock_reset : std_logic_vector(31 downto 0); + + --Media Interface + signal med2int : med2int_array_t(0 to 10); + signal int2med : int2med_array_t(0 to 10); + signal med_stat_debug : std_logic_vector (1*64-1 downto 0); + + signal ctrlbus_rx, bussci1_rx, bussci2_rx, bussci3_rx, bussci4_rx, bustools_rx, + bustc_rx, busgbeip_rx, busgbereg_rx, bus_master_out, handlerbus_rx, bus_hub_dbg_rx : CTRLBUS_RX; + signal ctrlbus_tx, bussci1_tx, bussci2_tx, bussci3_tx, bussci4_tx, bustools_tx, + bustc_tx, busgbeip_tx, busgbereg_tx, bus_master_in, bus_hub_dbg_tx : CTRLBUS_TX; + + + signal common_stat_reg : std_logic_vector(std_COMSTATREG*32-1 downto 0) := (others => '0'); + signal common_ctrl_reg : std_logic_vector(std_COMCTRLREG*32-1 downto 0); + + signal sed_error_i : std_logic; + signal bus_master_active : std_logic; + + signal spi_cs, spi_mosi, spi_miso, spi_clk : std_logic_vector(15 downto 0); + signal uart_tx, uart_rx : std_logic; + + signal timer : TIMERS; + signal lcd_data : std_logic_vector(511 downto 0); + + signal cts_number : std_logic_vector(15 downto 0); + signal cts_code : std_logic_vector(7 downto 0); + signal cts_information : std_logic_vector(7 downto 0); + signal cts_start_readout : std_logic; + signal cts_readout_type : std_logic_vector(3 downto 0); + signal cts_data : std_logic_vector(31 downto 0); + signal cts_dataready : std_logic; + signal cts_readout_finished : std_logic; + signal cts_read : std_logic; + signal cts_length : std_logic_vector(15 downto 0); + signal cts_status_bits : std_logic_vector(31 downto 0); + signal fee_data : std_logic_vector(15 downto 0); + signal fee_dataready : std_logic; + signal fee_read : std_logic; + signal fee_status_bits : std_logic_vector(31 downto 0); + signal fee_busy : std_logic; + signal gsc_init_data, gsc_reply_data : std_logic_vector(15 downto 0); + signal gsc_init_read, gsc_reply_read : std_logic; + signal gsc_init_dataready, gsc_reply_dataready : std_logic; + signal gsc_init_packet_num, gsc_reply_packet_num : std_logic_vector(2 downto 0); + signal gsc_busy : std_logic; + signal my_address : std_logic_vector(15 downto 0); + signal mc_unique_id : std_logic_vector(63 downto 0); + signal reset_via_gbe : std_logic := '0'; + + signal med_dataready_out : std_logic_vector (11-1 downto 0); + signal med_data_out : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_out : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_in : std_logic_vector (11-1 downto 0); + signal med_dataready_in : std_logic_vector (11-1 downto 0); + signal med_data_in : std_logic_vector (11*c_DATA_WIDTH-1 downto 0); + signal med_packet_num_in : std_logic_vector (11*c_NUM_WIDTH-1 downto 0); + signal med_read_out : std_logic_vector (11-1 downto 0); + signal med_stat_op : std_logic_vector (11*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (11*16-1 downto 0); + signal rdack, wrack : std_logic; + + signal trig_gen_out_i : std_logic_vector(3 downto 0); + signal monitor_inputs_i : std_logic_vector(17 downto 0); + + signal ONEWIRE_DATA : std_logic_vector(15 downto 0); + signal ONEWIRE_ADDR : std_logic_vector( 2 downto 0); + signal ONEWIRE_WRITE : std_logic; + + signal TEMP_OUT : std_logic_vector (11 downto 0); + signal UNIQUE_ID_OUT : std_logic_vector (63 downto 0); + + + attribute syn_keep of GSR_N : signal is true; + attribute syn_preserve of GSR_N : signal is true; + attribute syn_keep of bussci1_rx : signal is true; + attribute syn_preserve of bussci1_rx : signal is true; + attribute syn_keep of bustools_rx : signal is true; + attribute syn_preserve of bustools_rx : signal is true; + attribute syn_keep of bustc_rx : signal is true; + attribute syn_preserve of bustc_rx : signal is true; + +begin + + +--------------------------------------------------------------------------- +-- Clock & Reset Handling +--------------------------------------------------------------------------- +THE_CLOCK_RESET : entity work.clock_reset_handler + port map( + INT_CLK_IN => CLK_CORE_PCLK, + EXT_CLK_IN => CLK_EXT_PLL_LEFT, + NET_CLK_FULL_IN => med2int(INTERFACE_NUM-1).clk_full, + NET_CLK_HALF_IN => med2int(INTERFACE_NUM-1).clk_half, + RESET_FROM_NET => med2int(INTERFACE_NUM-1).stat_op(13), + SEND_RESET_IN => med2int(INTERFACE_NUM-1).stat_op(15), + + BUS_RX => bustc_rx, + BUS_TX => bustc_tx, + + RESET_OUT => reset_i, + CLEAR_OUT => clear_i, + GSR_OUT => GSR_N, + + FULL_CLK_OUT => clk_full, + SYS_CLK_OUT => clk_sys, + REF_CLK_OUT => clk_full_osc, + + ENPIRION_CLOCK => ENPIRION_CLOCK, + LED_RED_OUT => LED_RJ_RED, + LED_GREEN_OUT => LED_RJ_GREEN, + DEBUG_OUT => debug_clock_reset + ); + + +--------------------------------------------------------------------------- +-- PCSA Uplink when backplane is used +--------------------------------------------------------------------------- +gen_PCSA : if USE_BACKPLANE = c_YES generate + THE_MEDIA_PCSA : entity work.med_ecp3_sfp_sync + generic map( + SERDES_NUM => 0, + IS_SYNC_SLAVE => c_YES + ) + port map( + CLK_REF_FULL => clk_full_osc, --med2int(0).clk_full, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + --Internal Connection + MEDIA_MED2INT => med2int(INTERFACE_NUM-1), --10 or 8 + MEDIA_INT2MED => int2med(INTERFACE_NUM-1), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN => BACK_GPIO(1), + SD_LOS_IN => BACK_GPIO(1), + SD_TXDIS_OUT => BACK_GPIO(0), + --Control Interface + BUS_RX => bussci1_rx, + BUS_TX => bussci1_tx, + -- Status and control port + STAT_DEBUG => med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + +--------------------------------------------------------------------------- +-- PCSB Uplink without backplane and 3/4 downlinks +--------------------------------------------------------------------------- +gen_PCSB_BKPL : if USE_BACKPLANE = c_YES generate + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(9-2*INCLUDE_GBE), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(9-2*INCLUDE_GBE), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + + +gen_PCSB_noBKPL : if USE_BACKPLANE = c_NO generate + THE_MEDIA_4_PCSB : entity work.med_ecp3_sfp_sync_4_slave3 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_YES), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(4), + MEDIA_MED2INT(1) => med2int(5), + MEDIA_MED2INT(2) => med2int(6), + MEDIA_MED2INT(3) => med2int(INTERFACE_NUM-1), + MEDIA_INT2MED(0) => int2med(4), + MEDIA_INT2MED(1) => int2med(5), + MEDIA_INT2MED(2) => int2med(6), + MEDIA_INT2MED(3) => int2med(INTERFACE_NUM-1), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(5), + SD_PRSNT_N_IN(1) => HUB_MOD0(6), + SD_PRSNT_N_IN(2) => HUB_MOD0(7), + SD_PRSNT_N_IN(3) => SFP_MOD0(1), + + SD_LOS_IN(0) => HUB_LOS(5), + SD_LOS_IN(1) => HUB_LOS(6), + SD_LOS_IN(2) => HUB_LOS(7), + SD_LOS_IN(3) => SFP_LOS(1), + + SD_TXDIS_OUT(0) => HUB_TXDIS(5), + SD_TXDIS_OUT(1) => HUB_TXDIS(6), + SD_TXDIS_OUT(2) => HUB_TXDIS(7), + SD_TXDIS_OUT(3) => SFP_TX_DIS(1), + + --Control Interface + BUS_RX => bussci2_rx, + BUS_TX => bussci2_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + +--------------------------------------------------------------------------- +-- PCSC 4 downlinks +--------------------------------------------------------------------------- + THE_MEDIA_4_PCSC : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_YES ,c_YES) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(2), + MEDIA_MED2INT(1) => med2int(3), + MEDIA_MED2INT(2) => med2int(0), + MEDIA_MED2INT(3) => med2int(1), + MEDIA_INT2MED(0) => int2med(2), + MEDIA_INT2MED(1) => int2med(3), + MEDIA_INT2MED(2) => int2med(0), + MEDIA_INT2MED(3) => int2med(1), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => HUB_MOD0(3), + SD_PRSNT_N_IN(1) => HUB_MOD0(4), + SD_PRSNT_N_IN(2) => HUB_MOD0(1), + SD_PRSNT_N_IN(3) => HUB_MOD0(2), + + SD_LOS_IN(0) => HUB_LOS(3), + SD_LOS_IN(1) => HUB_LOS(4), + SD_LOS_IN(2) => HUB_LOS(1), + SD_LOS_IN(3) => HUB_LOS(2), + + SD_TXDIS_OUT(0) => HUB_TXDIS(3), + SD_TXDIS_OUT(1) => HUB_TXDIS(4), + SD_TXDIS_OUT(2) => HUB_TXDIS(1), + SD_TXDIS_OUT(3) => HUB_TXDIS(2), + + --Control Interface + BUS_RX => bussci3_rx, + BUS_TX => bussci3_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); + +--------------------------------------------------------------------------- +-- PCSD GBE or 2 downlinks +--------------------------------------------------------------------------- +gen_PCSD : if INCLUDE_GBE = c_NO generate + THE_MEDIA_4_PCSD : entity work.med_ecp3_sfp_sync_4 + generic map( + IS_SYNC_SLAVE => (c_NO, c_NO, c_NO, c_NO), + IS_USED => (c_YES,c_YES ,c_NO ,c_NO) + ) + port map( + CLK_REF_FULL => clk_full_osc, + CLK_INTERNAL_FULL => clk_full_osc, + SYSCLK => clk_sys, + RESET => reset_i, + CLEAR => clear_i, + + --Internal Connection + MEDIA_MED2INT(0) => med2int(8), + MEDIA_MED2INT(1) => med2int(7), + MEDIA_INT2MED(0) => int2med(8), + MEDIA_INT2MED(1) => int2med(7), + + --Sync operation + RX_DLM => open, + RX_DLM_WORD => open, + TX_DLM => open, + TX_DLM_WORD => open, + + --SFP Connection + SD_PRSNT_N_IN(0) => SFP_MOD0(0), + SD_PRSNT_N_IN(1) => HUB_MOD0(8), + + SD_LOS_IN(0) => SFP_LOS(0), + SD_LOS_IN(1) => HUB_LOS(8), + + SD_TXDIS_OUT(0) => SFP_TX_DIS(0), + SD_TXDIS_OUT(1) => HUB_TXDIS(8), + + --Control Interface + BUS_RX => bussci4_rx, + BUS_TX => bussci4_tx, + + -- Status and control port + STAT_DEBUG => open, --med_stat_debug(63 downto 0), + CTRL_DEBUG => open + ); +end generate; + +--------------------------------------------------------------------------- +-- GbE +--------------------------------------------------------------------------- +gen_noGBE : if INCLUDE_GBE = 0 generate + gsc_reply_read <= '1'; + gsc_init_dataready <= '0'; + busgbeip_tx.unknown <= busgbeip_rx.read or busgbeip_rx.write; + busgbereg_tx.unknown <= busgbereg_rx.read or busgbereg_rx.write; +end generate; + + +-- gen_GBE : if INCLUDE_GBE = 1 generate +-- GBE : entity work.gbe_wrapper +-- generic map( +-- DO_SIMULATION => 0, +-- INCLUDE_DEBUG => 0, +-- USE_INTERNAL_TRBNET_DUMMY => 0, +-- USE_EXTERNAL_TRBNET_DUMMY => 0, +-- RX_PATH_ENABLE => 1, +-- FIXED_SIZE_MODE => 1, +-- INCREMENTAL_MODE => 1, +-- FIXED_SIZE => 100, +-- FIXED_DELAY_MODE => 1, +-- UP_DOWN_MODE => 0, +-- UP_DOWN_LIMIT => 100, +-- FIXED_DELAY => 100, +-- +-- NUMBER_OF_GBE_LINKS => 4, +-- LINKS_ACTIVE => "0001", +-- +-- LINK_HAS_READOUT => "0001", +-- LINK_HAS_SLOWCTRL => "0001", +-- LINK_HAS_DHCP => "0001", +-- LINK_HAS_ARP => "0001", +-- LINK_HAS_PING => "0001" +-- ) +-- +-- port map( +-- CLK_SYS_IN => clk_sys, +-- CLK_125_IN => CLK_SUPPL_PCLK, +-- RESET => reset_i, +-- GSR_N => GSR_N, +-- +-- TRIGGER_IN => '0', +-- +-- SD_PRSNT_N_IN(0) => SFP_MOD0(0), +-- SD_PRSNT_N_IN(3 downto 1)=> "111", +-- SD_LOS_IN(0) => SFP_LOS(0), +-- SD_LOS_IN(3 downto 1) => "111", +-- SD_TXDIS_OUT(0) => SFP_TX_DIS(0), +-- +-- CTS_NUMBER_IN => cts_number, +-- CTS_CODE_IN => cts_code, +-- CTS_INFORMATION_IN => cts_information, +-- CTS_READOUT_TYPE_IN => cts_readout_type, +-- CTS_START_READOUT_IN => cts_start_readout, +-- CTS_DATA_OUT => cts_data, +-- CTS_DATAREADY_OUT => cts_dataready, +-- CTS_READOUT_FINISHED_OUT => cts_readout_finished, +-- CTS_READ_IN => cts_read, +-- CTS_LENGTH_OUT => cts_length, +-- CTS_ERROR_PATTERN_OUT => cts_status_bits, +-- +-- FEE_DATA_IN => fee_data, +-- FEE_DATAREADY_IN => fee_dataready, +-- FEE_READ_OUT => fee_read, +-- FEE_STATUS_BITS_IN => fee_status_bits, +-- FEE_BUSY_IN => fee_busy, +-- +-- MC_UNIQUE_ID_IN => mc_unique_id, +-- MY_TRBNET_ADDRESS_IN => my_address, +-- ISSUE_REBOOT_OUT => reboot_from_gbe, +-- +-- GSC_CLK_IN => clk_sys, +-- GSC_INIT_DATAREADY_OUT => gsc_init_dataready, +-- GSC_INIT_DATA_OUT => gsc_init_data, +-- GSC_INIT_PACKET_NUM_OUT => gsc_init_packet_num, +-- GSC_INIT_READ_IN => gsc_init_read, +-- GSC_REPLY_DATAREADY_IN => gsc_reply_dataready, +-- GSC_REPLY_DATA_IN => gsc_reply_data, +-- GSC_REPLY_PACKET_NUM_IN => gsc_reply_packet_num, +-- GSC_REPLY_READ_OUT => gsc_reply_read, +-- GSC_BUSY_IN => gsc_busy, +-- +-- BUS_IP_RX => busgbeip_rx, +-- BUS_IP_TX => busgbeip_tx, +-- BUS_REG_RX => busgbereg_rx, +-- BUS_REG_TX => busgbereg_tx, +-- +-- MAKE_RESET_OUT => reset_via_gbe, +-- +-- DEBUG_OUT => open +-- ); +-- end generate; + + +-- --------------------------------------------------------------------------- +-- -- Hub +-- --------------------------------------------------------------------------- +-- gen_hub_with_gbe : if INCLUDE_GBE = c_YES generate +-- +-- THE_HUB: entity work.trb_net16_hub_streaming_port_sctrl_record +-- generic map( +-- HUB_USED_CHANNELS => (1,1,0,1), +-- INIT_ADDRESS => INIT_ADDRESS, +-- MII_NUMBER => INTERFACE_NUM, +-- MII_IS_UPLINK => IS_UPLINK, +-- MII_IS_DOWNLINK => IS_DOWNLINK, +-- MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, +-- USE_ONEWIRE => c_YES, +-- HARDWARE_VERSION => HARDWARE_INFO, +-- INCLUDED_FEATURES => INCLUDED_FEATURES, +-- INIT_ENDPOINT_ID => x"0001", +-- CLOCK_FREQUENCY => CLOCK_FREQUENCY, +-- BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR +-- ) +-- port map( +-- CLK => clk_sys, +-- RESET => reset_i, +-- CLK_EN => '1', +-- +-- --Media interfacces +-- MEDIA_MED2INT => med2int(0 to INTERFACE_NUM-1), +-- MEDIA_INT2MED => int2med(0 to INTERFACE_NUM-1), +-- +-- --Event information coming from CTSCTS_READOUT_TYPE_OUT +-- CTS_NUMBER_OUT => cts_number, +-- CTS_CODE_OUT => cts_code, +-- CTS_INFORMATION_OUT => cts_information, +-- CTS_READOUT_TYPE_OUT => cts_readout_type, +-- CTS_START_READOUT_OUT => cts_start_readout, +-- --Information sent to CTS +-- --status data, equipped with DHDR +-- CTS_DATA_IN => cts_data, +-- CTS_DATAREADY_IN => cts_dataready, +-- CTS_READOUT_FINISHED_IN => cts_readout_finished, +-- CTS_READ_OUT => cts_read, +-- CTS_LENGTH_IN => cts_length, +-- CTS_STATUS_BITS_IN => cts_status_bits, +-- -- Data from Frontends +-- FEE_DATA_OUT => fee_data, +-- FEE_DATAREADY_OUT => fee_dataready, +-- FEE_READ_IN => fee_read, +-- FEE_STATUS_BITS_OUT => fee_status_bits, +-- FEE_BUSY_OUT => fee_busy, +-- MY_ADDRESS_IN => my_address, +-- COMMON_STAT_REGS => common_stat_reg, --open, +-- COMMON_CTRL_REGS => common_ctrl_reg, --open, +-- ONEWIRE => TEMPSENS, +-- MY_ADDRESS_OUT => my_address, +-- UNIQUE_ID_OUT => mc_unique_id, +-- EXTERNAL_SEND_RESET => external_reset_i, +-- +-- BUS_RX => ctrlbus_rx, +-- BUS_TX => ctrlbus_tx, +-- TIMER => timer, +-- +-- --Gbe Sctrl Input +-- GSC_INIT_DATAREADY_IN => gsc_init_dataready, +-- GSC_INIT_DATA_IN => gsc_init_data, +-- GSC_INIT_PACKET_NUM_IN => gsc_init_packet_num, +-- GSC_INIT_READ_OUT => gsc_init_read, +-- GSC_REPLY_DATAREADY_OUT => gsc_reply_dataready, +-- GSC_REPLY_DATA_OUT => gsc_reply_data, +-- GSC_REPLY_PACKET_NUM_OUT => gsc_reply_packet_num, +-- GSC_REPLY_READ_IN => gsc_reply_read, +-- GSC_BUSY_OUT => gsc_busy, +-- +-- --status and control ports +-- HUB_STAT_CHANNEL => open, +-- HUB_STAT_GEN => open, +-- MPLEX_CTRL => (others => '0'), +-- MPLEX_STAT => open, +-- STAT_REGS => open, +-- STAT_CTRL_REGS => open, +-- +-- --Fixed status and control ports +-- STAT_DEBUG => open, +-- CTRL_DEBUG => (others => '0') +-- ); +-- external_reset_i <= reset_via_gbe; -- or med2int(INTERFACE_NUM-1).stat_op(15); +-- end generate; +-- + +gen_hub_no_gbe : if INCLUDE_GBE = c_NO generate + + THE_HUB : entity work.trb_net16_cri_hub_base + generic map( + HUB_USED_CHANNELS => (1,1,0,1), + INIT_ADDRESS => INIT_ADDRESS, + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, + --USE_ONEWIRE => c_YES, + HARDWARE_VERSION => HARDWARE_INFO, + INCLUDED_FEATURES => INCLUDED_FEATURES, + INIT_ENDPOINT_ID => x"0001", + CLOCK_FREQUENCY => CLOCK_FREQUENCY, + BROADCAST_SPECIAL_ADDR => BROADCAST_SPECIAL_ADDR, + COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)) + ) + port map ( + CLK => clk_sys, + RESET => reset_i, + CLK_EN => '1', + + --Media interfacces + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out(INTERFACE_NUM*1-1 downto 0), + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out(INTERFACE_NUM*3-1 downto 0), + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in(INTERFACE_NUM*1-1 downto 0), + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in(INTERFACE_NUM*1-1 downto 0), + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in(INTERFACE_NUM*16-1 downto 0), + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in(INTERFACE_NUM*3-1 downto 0), + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out(INTERFACE_NUM*1-1 downto 0), + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op(INTERFACE_NUM*16-1 downto 0), + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op(INTERFACE_NUM*16-1 downto 0), + + DATA_ACTIVE => open, + DATA_OUT => open, + DATA_READY => open, + + DATA_ADDRESS_SENDER => open, + DATA_SEQNMBR => open, + DATA_LENGTH => open, + + ONEWIRE_DATA => ONEWIRE_DATA, + ONEWIRE_ADDR => ONEWIRE_ADDR, + ONEWIRE_WRITE => ONEWIRE_WRITE, + + COMMON_STAT_REGS => (others => '0'),--open,--common_stat_reg, + COMMON_CTRL_REGS => open,--common_ctrl_reg, + MY_ADDRESS_OUT => my_address, + TEMPERATURE_IN => TEMP_OUT, + + --REGIO INTERFACE + REGIO_ADDR_OUT => ctrlbus_rx.addr, + REGIO_READ_ENABLE_OUT => ctrlbus_rx.read, + REGIO_WRITE_ENABLE_OUT => ctrlbus_rx.write, + REGIO_DATA_OUT => ctrlbus_rx.data, + REGIO_DATA_IN => ctrlbus_tx.data, + REGIO_DATAREADY_IN => rdack, + REGIO_NO_MORE_DATA_IN => ctrlbus_tx.nack, + REGIO_WRITE_ACK_IN => wrack, + REGIO_UNKNOWN_ADDR_IN => ctrlbus_tx.unknown, + REGIO_TIMEOUT_OUT => ctrlbus_rx.timeout, + + --ONEWIRE => TEMPSENS, + --ONEWIRE_MONITOR_OUT => open, + --Status ports (for debugging) + MPLEX_CTRL => (others => '0'), + CTRL_DEBUG => (others => '0'), + STAT_DEBUG => open, + + BUS_HUB_DBG_RX => bus_hub_dbg_rx, + BUS_HUB_DBG_TX => bus_hub_dbg_tx + ); + + gen_media_record : for i in 0 to INTERFACE_NUM-1 generate + med_data_in(i*16+15 downto i*16) <= med2int(i).data; + med_packet_num_in(i*3+2 downto i*3) <= med2int(i).packet_num; + med_dataready_in(i) <= med2int(i).dataready; + med_read_in(i) <= med2int(i).tx_read; + med_stat_op(i*16+15 downto i*16) <= med2int(i).stat_op; + + int2med(i).data <= med_data_out(i*16+15 downto i*16); + int2med(i).packet_num <= med_packet_num_out(i*3+2 downto i*3); + int2med(i).dataready <= med_dataready_out(i); + int2med(i).ctrl_op <= med_ctrl_op(i*16+15 downto i*16); + end generate; + + rdack <= ctrlbus_tx.ack or ctrlbus_tx.rack; + wrack <= ctrlbus_tx.ack or ctrlbus_tx.wack; + + + --------------------------------------------------------------------- + --1-wire interface + --------------------------------------------------------------------- + -- gen_1wire : if USE_ONEWIRE = c_YES generate + onewire_interface : trb_net_onewire + generic map( + USE_TEMPERATURE_READOUT => c_YES, + CLK_PERIOD => 10 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + --connection to 1-wire interface + ONEWIRE => TEMPSENS, + MONITOR_OUT => open,-- ONEWIRE_MONITOR_OUT, + --connection to id ram, according to memory map in TrbNetRegIO + DATA_OUT => ONEWIRE_DATA, + ADDR_OUT => ONEWIRE_ADDR, + WRITE_OUT=> ONEWIRE_WRITE, + TEMP_OUT => TEMP_OUT, + ID_OUT => UNIQUE_ID_OUT, + STAT => open + ); +-- end generate; + +end generate; + +--------------------------------------------------------------------------- +-- Bus Handler +--------------------------------------------------------------------------- + THE_BUS_HANDLER : entity work.trb_net16_regio_bus_handler_record + generic map( + PORT_NUMBER => 9, + PORT_ADDRESSES => (0 => x"d000", 1 => x"d300", 2 => x"b000", 3 => x"b200", 4 => x"b400", 5 => x"b600", 6 => x"8100", 7 => x"8300", + 8 => x"e000", others => x"0000"), + PORT_ADDR_MASK => (0 => 12, 1 => 1, 2 => 9, 3 => 9, 4 => 9, 5 => 9, 6 => 8, 7 => 8, + 8 => 12 , others => 0), + PORT_MASK_ENABLE => 1 + ) + port map( + CLK => clk_sys, + RESET => reset_i, + + REGIO_RX => handlerbus_rx, + REGIO_TX => ctrlbus_tx, + + BUS_RX(0) => bustools_rx, --Flash, SPI, UART, ADC, SED + BUS_RX(1) => bustc_rx, --Clock switch + BUS_RX(2) => bussci1_rx, --SCI Serdes + BUS_RX(3) => bussci2_rx, + BUS_RX(4) => bussci3_rx, + BUS_RX(5) => bussci4_rx, + BUS_RX(6) => busgbeip_rx, + BUS_RX(7) => busgbereg_rx, + BUS_RX(8) => bus_hub_dbg_rx, + BUS_TX(0) => bustools_tx, + BUS_TX(1) => bustc_tx, + BUS_TX(2) => bussci1_tx, + BUS_TX(3) => bussci2_tx, + BUS_TX(4) => bussci3_tx, + BUS_TX(5) => bussci4_tx, + BUS_TX(6) => busgbeip_tx, + BUS_TX(7) => busgbereg_tx, + BUS_TX(8) => bus_hub_dbg_tx, + STAT_DEBUG => open + ); + + handlerbus_rx <= ctrlbus_rx when bus_master_active = '0' else bus_master_out; + +--------------------------------------------------------------------------- +-- Control Tools +--------------------------------------------------------------------------- + THE_TOOLS: entity work.trb3sc_tools + port map( + CLK => clk_sys, + RESET => reset_i, + + --Flash & Reload + FLASH_CS => FLASH_CS, + FLASH_CLK => FLASH_CLK, + FLASH_IN => FLASH_OUT, + FLASH_OUT => FLASH_IN, + PROGRAMN => PROGRAMN, + REBOOT_IN => do_reboot_i, + --SPI + SPI_CS_OUT => spi_cs, + SPI_MOSI_OUT=> spi_mosi, + SPI_MISO_IN => spi_miso, + SPI_CLK_OUT => spi_clk, + --Header + HEADER_IO => HDR_IO, + --LCD + LCD_DATA_IN => open, + --ADC + ADC_CS => ADC_CS, + ADC_MOSI => ADC_DIN, + ADC_MISO => ADC_DOUT, + ADC_CLK => ADC_CLK, + --Trigger & Monitor + MONITOR_INPUTS => open, + TRIG_GEN_INPUTS => open, + TRIG_GEN_OUTPUTS => open, + --SED + SED_ERROR_OUT => sed_error_i, + --Slowcontrol + BUS_RX => bustools_rx, + BUS_TX => bustools_tx, + --Control master for default settings + BUS_MASTER_IN => ctrlbus_tx, + BUS_MASTER_OUT => bus_master_out, + BUS_MASTER_ACTIVE => bus_master_active, + DEBUG_OUT => open + ); + +gen_reboot_no_gbe : if INCLUDE_GBE = c_NO generate + do_reboot_i <= common_ctrl_reg(15); +end generate; +gen_reboot_with_gbe : if INCLUDE_GBE = c_YES generate + do_reboot_i <= common_ctrl_reg(15) or reboot_from_gbe; +end generate; + + +--------------------------------------------------------------------------- +-- Switches +--------------------------------------------------------------------------- +--Serdes Select + PCSSW_ENSMB <= '0'; + PCSSW_EQ <= x"0"; + PCSSW_PE <= x"F"; + PCSSW <= "01001110"; --SFP2 on B3, AddOn on D1 + +--------------------------------------------------------------------------- +-- LED +--------------------------------------------------------------------------- + --LED are green, orange, red, yellow, white(2), rj_green(2), rj_red(2), sfp_green(2), sfp_red(2) + LED_GREEN <= debug_clock_reset(0); + LED_ORANGE <= debug_clock_reset(1); + LED_RED <= not sed_error_i; + LED_YELLOW <= debug_clock_reset(2); + + + +gen_hub_leds : for i in 0 to 6 generate + LED_HUB_LINKOK(i+1) <= not med2int(i).stat_op(9); + LED_HUB_TX(i+1) <= not (med2int(i).stat_op(10) or not med2int(i).stat_op(9)); + LED_HUB_RX(i+1) <= not (med2int(i).stat_op(11)); +end generate; + + LED_HUB_LINKOK(8) <= not med2int(7).stat_op(9) when INCLUDE_GBE = 0 else + '1'; + LED_HUB_TX(8) <= not (med2int(7).stat_op(10) or not med2int(7).stat_op(9)) when INCLUDE_GBE = 0 else + '1'; + LED_HUB_RX(8) <= not (med2int(7).stat_op(11)) when INCLUDE_GBE = 0 else + '1'; + LED_SFP_GREEN(0) <= not med2int(8).stat_op(9) when INCLUDE_GBE = 0 else + '1'; + LED_SFP_RED(0) <= not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 0 else + '1'; + + LED_SFP_GREEN(1) <= not med2int(9).stat_op(9) when INCLUDE_GBE = 0 else + not med2int(7).stat_op(9); + LED_SFP_RED(1) <= not (med2int(9).stat_op(10) or med2int(9).stat_op(11) or not med2int(9).stat_op(9)) when INCLUDE_GBE = 0 else + not (med2int(7).stat_op(10) or med2int(7).stat_op(11) or not med2int(7).stat_op(9)); + + LED_WHITE(0) <= not med2int(10).stat_op(9) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else + not med2int(8).stat_op(9) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else + '1'; + LED_WHITE(1) <= not (med2int(10).stat_op(10) or med2int(10).stat_op(11) or not med2int(10).stat_op(9)) when INCLUDE_GBE = 0 and USE_BACKPLANE = 1 else + not (med2int(8).stat_op(10) or med2int(8).stat_op(11) or not med2int(8).stat_op(9)) when INCLUDE_GBE = 1 and USE_BACKPLANE = 1 else + '1'; + + TEST_LINE(0) <= med2int(INTERFACE_NUM-1).stat_op(13); + TEST_LINE(1) <= med2int(INTERFACE_NUM-1).stat_op(15); + TEST_LINE(2) <= clear_i; + TEST_LINE(3) <= reset_i; +-- TEST_LINE(4) <= time_counter(26); +-- TEST_LINE(5) <= BACK_GPIO(1); +-- TEST_LINE(6) <= sfp_txdis_i; + TEST_LINE(7) <= med2int(INTERFACE_NUM-1).stat_op(9); + + +end architecture; + + + -- 2.43.0