From 5333638fc3a8c82bd38e35dfe9822e32bec17ecd Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Wed, 15 Jun 2022 09:59:11 +0200 Subject: [PATCH] redesign of DiRICH5s1 trigger logic with explicit FlipFlop --- dirich/code/input_signal_stretcher.vhd | 53 +++++++++++++++------- dirich5s/code/stretched_OR_trigger.vhd | 63 +++++++++++--------------- dirich5s/dirich5s.prj | 2 + 3 files changed, 65 insertions(+), 53 deletions(-) diff --git a/dirich/code/input_signal_stretcher.vhd b/dirich/code/input_signal_stretcher.vhd index f5f0c27..56632dd 100644 --- a/dirich/code/input_signal_stretcher.vhd +++ b/dirich/code/input_signal_stretcher.vhd @@ -3,6 +3,7 @@ library ieee; use ieee.numeric_std.all; library work; use work.trb_net_std.all; + entity input_signal_stretcher is port( @@ -11,45 +12,65 @@ port( INPUT : in std_logic; OUTPUT : out std_logic; + + INVERT : in std_logic; + ENABLE : in std_logic; STRETCH : in std_logic_vector(3 downto 0) := x"0" ); end entity; architecture behaviour of input_signal_stretcher is - signal or_long : std_logic := '0'; - signal active : std_logic := '1'; - signal cnt : unsigned (3 downto 0) := x"0"; + signal or_long : std_logic := '0'; + signal or_long_r : std_logic := '0'; + signal input_inv : std_logic; + signal cnt : unsigned (4 downto 0) := "00000"; + + component FD1S3DX + generic (gsr : String := "ENABLED"); + port ( + d : in std_logic := 'X'; + ck : in std_logic := 'X'; + cd : in std_logic := 'X'; + q : out std_logic := 'X' + ); + end component; begin + + input_inv <= ((INPUT xor INVERT) and ENABLE); - or_long <= (or_long or INPUT) and active; - OUTPUT <= INPUT when STRETCH = x"0" else + -- Input signal rising edge capture flip-flop + CREFF : FD1S3DX + port map (CK => input_inv, + CD => cnt(4), + D => '1', + Q => or_long); + + --or_long <= (or_long or input_inv) and (not cnt(4)); + + OUTPUT <= input_inv when STRETCH = x"0" else or_long; + + or_long_r <= or_long when rising_edge(CLK); THE_TRIGGER_CONTROL : process begin wait until rising_edge(CLK); if RESET = '1' then - active <= '1'; - cnt <= x"0"; + cnt <= "00000"; else - active <= '1'; - - if or_long = '1' then -- trigger is high - cnt <= cnt + 1; + if or_long_r = '1' and cnt(4) = '0' then -- trigger is high + cnt <= cnt - 1; + else + cnt <= ('0' & unsigned(STRETCH)) - 1; end if; - -- deactivate high signal of trigger after configured delay -- 1 stretch bit = 10ns -- stretch from 10 to 150ns -- Stretch begins with first clock edge, but signal is async high. -- So stretch of 10ns could be between 10.00ns to 19.99ns long, etc. - if std_logic_vector(cnt) >= STRETCH then - active <= '0'; - cnt <= x"0"; - end if; end if; end process; diff --git a/dirich5s/code/stretched_OR_trigger.vhd b/dirich5s/code/stretched_OR_trigger.vhd index 5f2d08e..06b8478 100644 --- a/dirich5s/code/stretched_OR_trigger.vhd +++ b/dirich5s/code/stretched_OR_trigger.vhd @@ -21,47 +21,35 @@ port( end entity; architecture behaviour of stretched_OR_trigger is - signal input_or : std_logic; - signal input_inv : std_logic_vector(INPUT_WIDTH-1 downto 0); - signal invert : std_logic_vector(31 downto 0) := x"00000000"; - signal enable : std_logic_vector(31 downto 0) := x"00000000"; - signal or_long : std_logic := '0'; - signal stretch : std_logic_vector(3 downto 0) := x"0"; - signal or_long_r : std_logic; - signal cnt : unsigned (4 downto 0) := "00000"; + signal input_or_stretched : std_logic; + signal input_inv : std_logic_vector(INPUT_WIDTH-1 downto 0); + signal invert : std_logic_vector(31 downto 0) := x"00000000"; + signal enable : std_logic_vector(31 downto 0) := x"00000000"; + signal stretch : std_logic_vector( 3 downto 0) := x"0"; + signal stretched_input : std_logic_vector(INPUT_WIDTH-1 downto 0) := (others => '0'); begin - input_inv <= ((INPUT xor invert(INPUT_WIDTH-1 downto 0)) and enable(INPUT_WIDTH-1 downto 0)); - input_or <= or_all( input_inv); - - or_long <= (or_long or input_or) and (not cnt(4)); - - OUTPUT <= input_or when stretch = x"0" else - or_long; - - or_long_r <= or_long when rising_edge(CLK); - - THE_TRIGGER_CONTROL : process - begin - wait until rising_edge(CLK); - - if RESET = '1' then - cnt <= "00000"; - else - if or_long_r = '1' and cnt(4) = '0' then -- trigger is high - cnt <= cnt - 1; - else - cnt <= ('0' & unsigned(stretch)) - 1; - end if; - -- deactivate high signal of trigger after configured delay - -- 1 stretch bit = 10ns - -- stretch from 10 to 150ns - -- Stretch begins with first clock edge, but signal is async high. - -- So stretch of 10ns could be between 10.00ns to 19.99ns long, etc. - end if; - end process; + + GEN_STRETCH : for i in 0 to (INPUT_WIDTH-1) generate + THE_TRIGGER_Stretch : entity work.input_signal_stretcher + port map ( + CLK => CLK, + RESET => RESET, + INPUT => INPUT(i), + INVERT => invert(i), + ENABLE => enable(i), + OUTPUT => stretched_input(i), + STRETCH => stretch + ); + end generate GEN_STRETCH; + + input_or_stretched <= or_all( stretched_input ); + + OUTPUT <= input_or_stretched; + proc_reg : process + variable stretch_check : std_logic_vector(3 downto 0) := x"0"; begin wait until rising_edge(CLK); BUS_TX.ack <= '0'; @@ -73,6 +61,7 @@ begin case BUS_RX.addr(1 downto 0) is when "00" => stretch <= BUS_RX.data(3 downto 0); + when "01" => invert <= BUS_RX.data; when "10" => diff --git a/dirich5s/dirich5s.prj b/dirich5s/dirich5s.prj index f0075ca..8de4dd8 100644 --- a/dirich5s/dirich5s.prj +++ b/dirich5s/dirich5s.prj @@ -218,6 +218,8 @@ add_file -vhdl -lib work "../../tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3 ### Triggering add_file -vhdl -lib work "./code/stretched_OR_trigger.vhd" +add_file -vhdl -lib work "../dirich/code/input_signal_stretcher.vhd" + add_file -vhdl -lib work "./dirich5s.vhd" -- 2.43.0