From 533c3f4a4bf2835bf484337ce9b148334c54efe5 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 12 Jul 2022 10:29:22 +0200 Subject: [PATCH] debugging --- gbe_hub/trb3sc_gbe_hub.vhd | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-) diff --git a/gbe_hub/trb3sc_gbe_hub.vhd b/gbe_hub/trb3sc_gbe_hub.vhd index 2feacdd..5abe81a 100644 --- a/gbe_hub/trb3sc_gbe_hub.vhd +++ b/gbe_hub/trb3sc_gbe_hub.vhd @@ -183,6 +183,8 @@ architecture trb3sc_arch of trb3sc_gbe_hub is signal pcs_an_ready : std_logic; signal link_active : std_logic; + signal debug : std_logic_vector(31 downto 0); + begin -- SerDes usage: @@ -367,21 +369,19 @@ begin -- 8 : fifo_eof -- 7..0: data - DBG(3 downto 0) <= dl_rx_frame_avail; - DBG(7 downto 4) <= dl_rx_frame_req; - DBG(11 downto 8) <= dl_rx_frame_ack; - DBG(15 downto 12) <= ul_rx_data(3 downto 0); - DBG(19 downto 16) <= dl_rx_data(0)(3 downto 0); + DBG(3 downto 0) <= port_sel; + DBG(11 downto 4) <= ul_rx_data(7 downto 0); + DBG(19 downto 12) <= dl_rx_data(0)(7 downto 0); DBG(20) <= ul_rx_frame_avail; DBG(21) <= ul_rx_frame_req; DBG(22) <= ul_rx_frame_ack; DBG(23) <= dl_rx_data(0)(9); DBG(27 downto 24) <= dl_tx_fifofull(3 downto 0); - DBG(28) <= ul_rx_data(8); + DBG(28) <= debug(0); --ul_rx_data(8); DBG(29) <= ul_rx_data(9); - DBG(30) <= ul_rx_data(10); + DBG(30) <= debug(1); --ul_rx_data(10); DBG(31) <= ul_rx_fifofull; - DBG(32) <= dl_rx_data(0)(8); + DBG(32) <= debug(4); --dl_rx_data(0)(8); DBG(33) <= clk_sys; --------------------------------------------------------------------------- @@ -444,7 +444,7 @@ begin MAKE_RESET_OUT => reset_via_gbe, -- debug STATUS_OUT => status, - DEBUG_OUT => open + DEBUG_OUT => debug ); ------------------------------------------------------------------------------- -- 2.43.0