From 535fcf5de158e4dae3fa929ccfbbfb76f21f1f03 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 1 Aug 2008 13:53:08 +0000 Subject: [PATCH] addon-interface tested on mdc addon --- .../scm/lattice_scm_fifo_16bit_dualport.lpc | 16 +-- .../scm/lattice_scm_fifo_16bit_dualport.srp | 4 +- .../scm/lattice_scm_fifo_16bit_dualport.sym | Bin 546 -> 546 bytes .../scm/lattice_scm_fifo_16bit_dualport.vhd | 20 +-- lattice/scm/trb_net16_fifo_arch.vhd | 116 +++++++++--------- lattice/scm/trb_net_clock_generator.vhd | 18 ++- trb_net16_med_16_SDR_OS.vhd | 49 ++++---- 7 files changed, 119 insertions(+), 104 deletions(-) diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc b/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc index 3d402df..d63038e 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.lpc @@ -1,9 +1,9 @@ [Device] Family=latticescm -PartType=LFSCM3GA15EP1 -PartName=LFSCM3GA15EP1-5F256C -SpeedGrade=-5 -Package=FPBGA256 +PartType=LFSCM3GA25EP1 +PartName=LFSCM3GA25EP1-6FF1020C +SpeedGrade=-6 +Package=FFBGA1020 OperatingCondition=COM Status=P @@ -16,8 +16,8 @@ CoreRevision=4.4 ModuleName=lattice_scm_fifo_16bit_dualport SourceFormat=Schematic/VHDL ParameterFileVersion=1.0 -Date=07/23/2008 -Time=14:50:38 +Date=07/30/2008 +Time=18:54:57 [Parameters] Verilog=0 @@ -32,7 +32,7 @@ RDepth=1024 RWidth=18 WDepth=1024 WWidth=18 -regout=1 +regout=0 CtrlByRdEn=0 EmpFlg=1 PeMode=Static - Single Threshold @@ -40,7 +40,7 @@ PeAssert=10 PeDeassert=12 FullFlg=1 PfMode=Static - Single Threshold -PfAssert=1008 +PfAssert=508 PfDeassert=506 Reset=Sync RDataCount=0 diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.srp b/lattice/scm/lattice_scm_fifo_16bit_dualport.srp index 646010e..54ab978 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport.srp +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.srp @@ -1,5 +1,5 @@ SCUBA, Version ispLever_v71_PROD_Build (58) -Wed Jul 23 14:50:39 2008 +Wed Jul 30 18:54:57 2008 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. @@ -7,7 +7,7 @@ Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2008 Lattice Semiconductor Corporation, All rights reserved. - Issued command : /local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -regout -no_enable -pe 10 -pf 1008 -sync_reset -e + Issued command : /local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e Circuit name : lattice_scm_fifo_16bit_dualport Module type : ebfifo Module Version : 4.4 diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.sym b/lattice/scm/lattice_scm_fifo_16bit_dualport.sym index 5b6cf8d4e842e9822e04a3fce42d9e64a789d2b7..d029f6b663d26ac3976f60f3dd78f0f94d88e708 100644 GIT binary patch delta 15 WcmZ3)vWSIkP58sMocxV!GE4w2tp#lW delta 15 WcmZ3)vWSIkO?YV9o9vBjGE4w0Sp_`+ diff --git a/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd b/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd index 2781123..ab276da 100644 --- a/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd +++ b/lattice/scm/lattice_scm_fifo_16bit_dualport.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA ispLever_v71_PROD_Build (58) -- Module Version: 4.4 ---/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -regout -no_enable -pe 10 -pf 1008 -sync_reset -e +--/local/lattice/ispLever7.1/isptools/ispfpga/bin/lin/scuba -w -n lattice_scm_fifo_16bit_dualport -lang vhdl -synth synplify -bus_exp 7 -bb -arch or5s00 -type ebfifo -depth 1024 -width 18 -rwidth 18 -no_enable -pe 10 -pf 508 -sync_reset -e --- Wed Jul 23 14:50:39 2008 +-- Wed Jul 30 18:54:57 2008 library IEEE; use IEEE.std_logic_1164.all; @@ -30,9 +30,9 @@ end lattice_scm_fifo_16bit_dualport; architecture Structure of lattice_scm_fifo_16bit_dualport is -- internal signal declarations + signal scuba_vhi: std_logic; signal Empty_int: std_logic; signal Full_int: std_logic; - signal scuba_vhi: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -111,12 +111,12 @@ architecture Structure of lattice_scm_fifo_16bit_dualport is attribute DATA_WIDTH_W : string; attribute FULLPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111111100001"; attribute FULLPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111111110001"; - attribute AFPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111011100001"; - attribute AFPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b011111011110001"; + attribute AFPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b001111110100001"; + attribute AFPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b001111110110001"; attribute AEPOINTER1 of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000010111111"; attribute AEPOINTER of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b000000010101111"; attribute RESETMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "SYNC"; - attribute REGMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "OUTREG"; + attribute REGMODE of lattice_scm_fifo_16bit_dualport_0_0 : label is "NOREG"; attribute CSDECODE_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b11"; attribute CSDECODE_W of lattice_scm_fifo_16bit_dualport_0_0 : label is "0b11"; attribute DATA_WIDTH_R of lattice_scm_fifo_16bit_dualport_0_0 : label is "18"; @@ -134,9 +134,9 @@ begin lattice_scm_fifo_16bit_dualport_0_0: FIFO16KA -- synopsys translate_off generic map (FULLPOINTER1=> "011111111100001", FULLPOINTER=> "011111111110001", - AFPOINTER1=> "011111011100001", AFPOINTER=> "011111011110001", + AFPOINTER1=> "001111110100001", AFPOINTER=> "001111110110001", AEPOINTER1=> "000000010111111", AEPOINTER=> "000000010101111", - RESETMODE=> "SYNC", REGMODE=> "OUTREG", CSDECODE_R=> "11", + RESETMODE=> "SYNC", REGMODE=> "NOREG", CSDECODE_R=> "11", CSDECODE_W=> "11", DATA_WIDTH_R=> 18, DATA_WIDTH_W=> 18) -- synopsys translate_on port map (DI0=>Data(0), DI1=>Data(1), DI2=>Data(2), DI3=>Data(3), @@ -151,8 +151,8 @@ begin DI30=>scuba_vlo, DI31=>scuba_vlo, DI32=>scuba_vlo, DI33=>scuba_vlo, DI34=>scuba_vlo, DI35=>scuba_vlo, FULLI=>Full_int, CSW0=>scuba_vhi, CSW1=>scuba_vhi, - EMPTYI=>Empty_int, CSR0=>RdEn, CSR1=>scuba_vhi, WE=>WrEn, - RE=>scuba_vhi, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, + EMPTYI=>Empty_int, CSR0=>scuba_vhi, CSR1=>scuba_vhi, + WE=>WrEn, RE=>RdEn, CLKW=>WrClock, CLKR=>RdClock, RST=>Reset, RPRST=>RPReset, DO0=>Q(0), DO1=>Q(1), DO2=>Q(2), DO3=>Q(3), DO4=>Q(4), DO5=>Q(5), DO6=>Q(6), DO7=>Q(7), DO8=>Q(8), DO9=>Q(9), DO10=>Q(10), DO11=>Q(11), DO12=>Q(12), diff --git a/lattice/scm/trb_net16_fifo_arch.vhd b/lattice/scm/trb_net16_fifo_arch.vhd index 319e3fa..9b07121 100644 --- a/lattice/scm/trb_net16_fifo_arch.vhd +++ b/lattice/scm/trb_net16_fifo_arch.vhd @@ -5,83 +5,83 @@ USE ieee.std_logic_signed.ALL; USE IEEE.numeric_std.ALL; use work.trb_net_std.all; --- entity trb_net16_fifo is --- generic ( --- USE_VENDOR_CORES : integer range 0 to 1 := c_NO; --- DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets --- ); --- port ( --- CLK : in std_logic; --- RESET : in std_logic; --- CLK_EN : in std_logic; --- DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data --- PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data --- WRITE_ENABLE_IN : in std_logic; --- DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data --- PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data --- READ_ENABLE_IN : in std_logic; --- FULL_OUT : out std_logic; -- Full Flag --- EMPTY_OUT : out std_logic; --- DEPTH_OUT : out std_logic_vector(7 downto 0) --- ); --- end entity; +entity trb_net16_fifo is + generic ( + USE_VENDOR_CORES : integer range 0 to 1 := c_NO; + DEPTH : integer := 6 -- Depth of the FIFO, 2^(n+1) 64Bit packets + ); + port ( + CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + DATA_IN : in std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Input data + PACKET_NUM_IN : in std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(c_DATA_WIDTH - 1 downto 0); -- Output data + PACKET_NUM_OUT : out std_logic_vector(c_NUM_WIDTH - 1 downto 0); -- Input data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); +end entity; architecture arch_trb_net16_fifo of trb_net16_fifo is component lattice_scm_fifo_18x1k is port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; - Full: out std_logic; - AlmostEmpty: out std_logic; + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; + Full: out std_logic; + AlmostEmpty: out std_logic; AlmostFull: out std_logic); end component; component lattice_scm_fifo_18x16 is port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; Full: out std_logic); end component; component lattice_scm_fifo_18x32 is port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; Full: out std_logic); end component; component lattice_scm_fifo_18x64 is port ( - Data: in std_logic_vector(17 downto 0); - WrClock: in std_logic; - RdClock: in std_logic; - WrEn: in std_logic; - RdEn: in std_logic; - Reset: in std_logic; - RPReset: in std_logic; - Q: out std_logic_vector(17 downto 0); - Empty: out std_logic; + Data: in std_logic_vector(17 downto 0); + WrClock: in std_logic; + RdClock: in std_logic; + WrEn: in std_logic; + RdEn: in std_logic; + Reset: in std_logic; + RPReset: in std_logic; + Q: out std_logic_vector(17 downto 0); + Empty: out std_logic; Full: out std_logic); end component; diff --git a/lattice/scm/trb_net_clock_generator.vhd b/lattice/scm/trb_net_clock_generator.vhd index c79d90a..3b366d7 100644 --- a/lattice/scm/trb_net_clock_generator.vhd +++ b/lattice/scm/trb_net_clock_generator.vhd @@ -31,11 +31,15 @@ architecture trb_net_clock_generator_arch of trb_net_clock_generator is port (clk: in std_logic; clkop: out std_logic; clkos: out std_logic; lock: out std_logic); end component; - + component lattice_scm_clock_200 + generic (SMI_OFFSET : in String := "0x410"); + port (clk: in std_logic; clkop: out std_logic; + clkos: out std_logic; lock: out std_logic); + end component; begin - gen_3x : if FREQUENCY_OUT = 200.0 and FREQUENCY_IN = 100.0 generate + gen_3x : if FREQUENCY_OUT = 300.0 and FREQUENCY_IN = 100.0 generate -- parameterized module component instance CLK_GEN : lattice_scm_clock_300 @@ -46,7 +50,17 @@ begin lock =>locked ); end generate; + gen_2x : if FREQUENCY_OUT = 200.0 and FREQUENCY_IN = 100.0 generate +-- parameterized module component instance + CLK_GEN : lattice_scm_clock_200 + port map ( + clk =>CLK_IN, + clkop=>CLK_OUT, + clkos=>open, + lock =>locked + ); + end generate; gen_none : if FREQUENCY_OUT = 300.0 or FREQUENCY_IN /= 100.0 generate CLK_OUT <= CLK_IN; LOCKED <= '0'; diff --git a/trb_net16_med_16_SDR_OS.vhd b/trb_net16_med_16_SDR_OS.vhd index bebf4ca..6f5f150 100644 --- a/trb_net16_med_16_SDR_OS.vhd +++ b/trb_net16_med_16_SDR_OS.vhd @@ -182,7 +182,7 @@ begin process(CLK) begin - if falling_edge(CLK) then + if rising_edge(CLK) then TX_CLK_OUT <= buf_tx_clk; end if; end process; @@ -223,7 +223,7 @@ begin CLOCK_MULT => 2, CLOCK_DIV => 1, CLKIN_DIVIDE_BY_2 => false, - CLKIN_PERIOD => 20.0 + CLKIN_PERIOD => 10.0 ) port map( RESET => RESET, @@ -259,16 +259,18 @@ process(CLK) RX_REG : process(RECV_CLK, recv_clk_real_locked) begin - if recv_clk_real_locked = '0' then - buf_RX_CTRL <= (others => '0'); - buf_RX_CLK <= '0'; - last_RX_CLK <= '0'; - buf_RX_DATA <= reg_RX_DATA; - elsif rising_edge(RECV_CLK) then - buf_RX_CLK <= reg_RX_CLK; - buf_RX_DATA <= reg_RX_DATA; - buf_RX_CTRL <= reg_RX_CTRL; - last_RX_CLK <= buf_RX_CLK; + if rising_edge(RECV_CLK) then + if recv_clk_real_locked = '0' then + buf_RX_CTRL <= (others => '0'); + buf_RX_CLK <= '0'; + last_RX_CLK <= '0'; + buf_RX_DATA <= (others => '0'); + else + buf_RX_CLK <= reg_RX_CLK; + buf_RX_DATA <= reg_RX_DATA; + buf_RX_CTRL <= reg_RX_CTRL; + last_RX_CLK <= buf_RX_CLK; + end if; end if; end process; @@ -277,7 +279,7 @@ process(CLK) rx_reset <= buf_RX_CTRL(2); rx_parity <= buf_RX_CTRL(3); - rx_parity_match <= xor_all(rx_parity & buf_RX_DATA); + rx_parity_match <= not xor_all(rx_parity & buf_RX_DATA); next_rx_fifo_write_enable <= (buf_RX_CLK xor last_RX_CLK) and rx_datavalid; next_rx_fifo_data_in <= rx_first_packet & rx_parity_match & buf_RX_DATA; @@ -347,10 +349,8 @@ process(CLK) process(RECV_CLK, recv_clk_real_locked,med_reset) begin - if recv_clk_real_locked = '0' or med_reset = '1' then - wait_for_startup <= '1'; - elsif rising_edge(RECV_CLK) then - if rx_clock_detect = '0' then + if rising_edge(RECV_CLK) then + if recv_clk_real_locked = '0' or med_reset = '1' or rx_clock_detect = '0' then wait_for_startup <= '1'; elsif rx_reset = '1' and recv_clk_locked = '1' then wait_for_startup <= '0'; @@ -362,7 +362,7 @@ process(CLK) ERROR_OUT_gen : process(CLK) begin if rising_edge(CLK) then - if recv_clk_real_locked = '0' then + if recv_clk_real_locked = '0' or rx_clock_detect = '0' then INT_ERROR_OUT <= ERROR_NC; elsif (buf_INT_DATAREADY_OUT = '1' and rx_fifo_data_out(16) = '0') then --Parity error INT_ERROR_OUT <= ERROR_ENCOD; @@ -377,11 +377,11 @@ process(CLK) rx_clk_detect_counter: process (RECV_CLK, recv_clk_real_locked) begin - if recv_clk_real_locked = '0' then - rx_CLK_counter <= (others => '0'); - rx_clock_detect <= '0'; - elsif rising_edge(RECV_CLK) then - if buf_RX_CLK = '1' and last_RX_CLK = '0' then + if rising_edge(RECV_CLK) then + if recv_clk_real_locked = '0' then + rx_CLK_counter <= (others => '0'); + rx_clock_detect <= '0'; + elsif buf_RX_CLK = '1' and last_RX_CLK = '0' then rx_CLK_counter <= (others => '0'); rx_clock_detect <= '1'; elsif rx_CLK_counter /= 31 then @@ -398,6 +398,7 @@ process(CLK) STAT_OP(14 downto 0) <= (others => '0'); STAT_OP(15) <= '1' when rx_reset = '1' and wait_for_startup_slow = '0' else '0'; + STAT(12) <= rx_parity_match; STAT(11) <= RECV_CLK; STAT(10) <= recv_clk_real_locked; STAT(9) <= rx_reset; @@ -410,7 +411,7 @@ process(CLK) STAT(2) <= next_tx_reset; STAT(1) <= buf_RX_CLK; - STAT(31 downto 12) <= (others => '0'); + STAT(31 downto 13) <= (others => '0'); med_reset <= RESET or CTRL_OP(15); -- 2.43.0