From 5379805f50190a07ffcaf4956036b1d0000a06e6 Mon Sep 17 00:00:00 2001 From: Ludwig Maier Date: Sun, 9 Mar 2014 15:03:53 +0100 Subject: [PATCH] nxyter, new dsign, working --- nxyter/cores/fifo_32_data.ipx | 10 +- nxyter/cores/fifo_32_data.lpc | 10 +- nxyter/cores/fifo_32_data.vhd | 740 ++++++++++++++++++------- nxyter/source/nx_data_receiver.vhd | 291 +++++----- nxyter/source/nx_data_validate.vhd | 27 +- nxyter/source/nx_event_buffer.vhd | 183 ++++-- nxyter/source/nx_trigger_generator.vhd | 23 +- nxyter/source/nx_trigger_validate.vhd | 5 +- nxyter/source/nxyter_components.vhd | 22 +- nxyter/source/nxyter_fee_board.vhd | 15 +- nxyter/source/pulse_to_level.vhd | 19 +- nxyter/source/registers.txt | 4 +- nxyter/source/timer.vhd | 2 +- nxyter/source/timer_static.vhd | 6 +- nxyter/trb3_periph_constraints.lpf | 3 +- nxyter/trb3_periph_nx1.vhd | 4 +- nxyter/trb3_periph_nxyter.lpf | 2 - 17 files changed, 911 insertions(+), 455 deletions(-) diff --git a/nxyter/cores/fifo_32_data.ipx b/nxyter/cores/fifo_32_data.ipx index 8c89b79..cccad84 100644 --- a/nxyter/cores/fifo_32_data.ipx +++ b/nxyter/cores/fifo_32_data.ipx @@ -1,9 +1,9 @@ - + - - - - + + + + diff --git a/nxyter/cores/fifo_32_data.lpc b/nxyter/cores/fifo_32_data.lpc index f0f1d7b..41e09d1 100644 --- a/nxyter/cores/fifo_32_data.lpc +++ b/nxyter/cores/fifo_32_data.lpc @@ -16,8 +16,8 @@ CoreRevision=4.8 ModuleName=fifo_32_data SourceFormat=VHDL ParameterFileVersion=1.0 -Date=11/16/2013 -Time=11:51:58 +Date=03/06/2014 +Time=20:19:42 [Parameters] Verilog=0 @@ -28,7 +28,7 @@ Expression=BusA(0 to 7) Order=Big Endian [MSB:LSB] IO=0 FIFOImp=EBR Based -Depth=1024 +Depth=2048 Width=32 regout=1 CtrlByRdEn=0 @@ -37,9 +37,9 @@ PeMode=Static - Single Threshold PeAssert=1 PeDeassert=12 FullFlg=1 -PfMode=Static - Single Threshold +PfMode=Dynamic - Single Threshold PfAssert=1020 PfDeassert=506 -RDataCount=1 +RDataCount=0 EnECC=0 EnFWFT=0 diff --git a/nxyter/cores/fifo_32_data.vhd b/nxyter/cores/fifo_32_data.vhd index e607cd3..336b239 100644 --- a/nxyter/cores/fifo_32_data.vhd +++ b/nxyter/cores/fifo_32_data.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond_2.1_Production (100) -- Module Version: 4.8 ---/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 1024 -width 32 -depth 1024 -regout -no_enable -pe -1 -pf 1020 -fill -e +--/usr/local/opt/lattice_diamond/diamond/2.1/ispfpga/bin/lin64/scuba -w -lang vhdl -synth synplify -bus_exp 7 -bb -arch ep5c00 -type ebfifo -depth 2048 -width 32 -depth 2048 -regout -no_enable -pe -1 -pf 0 -e --- Sat Nov 16 11:51:58 2013 +-- Thu Mar 6 20:19:42 2014 library IEEE; use IEEE.std_logic_1164.all; @@ -18,8 +18,8 @@ entity fifo_32_data is WrEn: in std_logic; RdEn: in std_logic; Reset: in std_logic; + AmFullThresh: in std_logic_vector(10 downto 0); Q: out std_logic_vector(31 downto 0); - WCNT: out std_logic_vector(10 downto 0); Empty: out std_logic; Full: out std_logic; AlmostFull: out std_logic); @@ -32,14 +32,25 @@ architecture Structure of fifo_32_data is signal invout_1: std_logic; signal rden_i_inv: std_logic; signal invout_0: std_logic; - signal r_nw_inv: std_logic; signal r_nw: std_logic; - signal fcnt_en_inv: std_logic; signal fcnt_en: std_logic; signal empty_i: std_logic; signal empty_d: std_logic; signal full_i: std_logic; signal full_d: std_logic; + signal wptr_0: std_logic; + signal wptr_1: std_logic; + signal wptr_2: std_logic; + signal wptr_3: std_logic; + signal wptr_4: std_logic; + signal wptr_5: std_logic; + signal wptr_6: std_logic; + signal wptr_7: std_logic; + signal wptr_8: std_logic; + signal wptr_9: std_logic; + signal wptr_10: std_logic; + signal wptr_11: std_logic; + signal rptr_11: std_logic; signal ifcount_0: std_logic; signal ifcount_1: std_logic; signal bdcnt_bctr_ci: std_logic; @@ -56,6 +67,7 @@ architecture Structure of fifo_32_data is signal ifcount_9: std_logic; signal co3: std_logic; signal ifcount_10: std_logic; + signal ifcount_11: std_logic; signal co5: std_logic; signal co4: std_logic; signal cmp_ci: std_logic; @@ -68,44 +80,47 @@ architecture Structure of fifo_32_data is signal cmp_le_1: std_logic; signal cmp_le_1_c: std_logic; signal cmp_ci_1: std_logic; + signal fcount_0: std_logic; + signal fcount_1: std_logic; signal co0_2: std_logic; + signal fcount_2: std_logic; + signal fcount_3: std_logic; signal co1_2: std_logic; + signal fcount_4: std_logic; + signal fcount_5: std_logic; signal co2_2: std_logic; + signal fcount_6: std_logic; + signal fcount_7: std_logic; signal co3_2: std_logic; - signal wren_i: std_logic; + signal fcount_8: std_logic; + signal fcount_9: std_logic; signal co4_2: std_logic; signal wren_i_inv: std_logic; + signal fcount_10: std_logic; + signal fcount_11: std_logic; signal cmp_ge_d1: std_logic; signal cmp_ge_d1_c: std_logic; signal iwcount_0: std_logic; signal iwcount_1: std_logic; - signal wcount_0: std_logic; - signal wcount_1: std_logic; signal w_ctr_ci: std_logic; signal iwcount_2: std_logic; signal iwcount_3: std_logic; - signal wcount_2: std_logic; - signal wcount_3: std_logic; signal co0_3: std_logic; signal iwcount_4: std_logic; signal iwcount_5: std_logic; - signal wcount_4: std_logic; - signal wcount_5: std_logic; signal co1_3: std_logic; signal iwcount_6: std_logic; signal iwcount_7: std_logic; - signal wcount_6: std_logic; - signal wcount_7: std_logic; signal co2_3: std_logic; signal iwcount_8: std_logic; signal iwcount_9: std_logic; - signal wcount_8: std_logic; - signal wcount_9: std_logic; signal co3_3: std_logic; signal iwcount_10: std_logic; + signal iwcount_11: std_logic; signal co5_1: std_logic; - signal wcount_10: std_logic; + signal wcount_11: std_logic; signal co4_3: std_logic; + signal scuba_vhi: std_logic; signal ircount_0: std_logic; signal ircount_1: std_logic; signal rcount_0: std_logic; @@ -132,32 +147,75 @@ architecture Structure of fifo_32_data is signal rcount_9: std_logic; signal co3_4: std_logic; signal ircount_10: std_logic; + signal ircount_11: std_logic; signal co5_2: std_logic; signal rcount_10: std_logic; + signal rcount_11: std_logic; signal co4_4: std_logic; - signal cmp_ci_2: std_logic; - signal fcnt_en_inv_inv: std_logic; + signal wcnt_sub_0: std_logic; + signal cnt_con_inv: std_logic; + signal rptr_0: std_logic; signal cnt_con: std_logic; - signal fcount_0: std_logic; - signal fcount_1: std_logic; + signal wcount_0: std_logic; + signal wcnt_sub_1: std_logic; + signal wcnt_sub_2: std_logic; signal co0_5: std_logic; - signal cnt_con_inv: std_logic; - signal fcount_2: std_logic; - signal fcount_3: std_logic; + signal rptr_1: std_logic; + signal rptr_2: std_logic; + signal wcount_1: std_logic; + signal wcount_2: std_logic; + signal wcnt_sub_3: std_logic; + signal wcnt_sub_4: std_logic; signal co1_5: std_logic; - signal fcount_4: std_logic; - signal fcount_5: std_logic; + signal rptr_3: std_logic; + signal rptr_4: std_logic; + signal wcount_3: std_logic; + signal wcount_4: std_logic; + signal wcnt_sub_5: std_logic; + signal wcnt_sub_6: std_logic; signal co2_5: std_logic; - signal fcount_6: std_logic; - signal fcount_7: std_logic; + signal rptr_5: std_logic; + signal rptr_6: std_logic; + signal wcount_5: std_logic; + signal wcount_6: std_logic; + signal wcnt_sub_7: std_logic; + signal wcnt_sub_8: std_logic; signal co3_5: std_logic; - signal scuba_vhi: std_logic; - signal fcount_8: std_logic; - signal fcount_9: std_logic; + signal rptr_7: std_logic; + signal rptr_8: std_logic; + signal wcount_7: std_logic; + signal wcount_8: std_logic; + signal wcnt_sub_9: std_logic; + signal wcnt_sub_10: std_logic; signal co4_5: std_logic; - signal fcount_10: std_logic; - signal af_d: std_logic; - signal af_d_c: std_logic; + signal rptr_9: std_logic; + signal rptr_10: std_logic; + signal wcount_9: std_logic; + signal wcount_10: std_logic; + signal wcnt_sub_11: std_logic; + signal co5_3: std_logic; + signal wcnt_sub_msb: std_logic; + signal wren_i: std_logic; + signal cmp_ci_2: std_logic; + signal wcnt_reg_0: std_logic; + signal wcnt_reg_1: std_logic; + signal co0_6: std_logic; + signal wcnt_reg_2: std_logic; + signal wcnt_reg_3: std_logic; + signal co1_6: std_logic; + signal wcnt_reg_4: std_logic; + signal wcnt_reg_5: std_logic; + signal co2_6: std_logic; + signal wcnt_reg_6: std_logic; + signal wcnt_reg_7: std_logic; + signal co3_6: std_logic; + signal wcnt_reg_8: std_logic; + signal wcnt_reg_9: std_logic; + signal co4_6: std_logic; + signal wcnt_reg_10: std_logic; + signal wcnt_reg_11: std_logic; + signal af_set: std_logic; + signal af_set_c: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -186,6 +244,15 @@ architecture Structure of fifo_32_data is B1: in std_logic; CI: in std_logic; COUT: out std_logic; S0: out std_logic; S1: out std_logic); end component; + component FSUB2B + port (A0: in std_logic; A1: in std_logic; B0: in std_logic; + B1: in std_logic; BI: in std_logic; BOUT: out std_logic; + S0: out std_logic; S1: out std_logic); + end component; + component FD1P3BX + port (D: in std_logic; SP: in std_logic; CK: in std_logic; + PD: in std_logic; Q: out std_logic); + end component; component FD1P3DX port (D: in std_logic; SP: in std_logic; CK: in std_logic; CD: in std_logic; Q: out std_logic); @@ -282,12 +349,57 @@ architecture Structure of fifo_32_data is attribute MEM_INIT_FILE : string; attribute RESETMODE : string; attribute GSR : string; - attribute MEM_LPC_FILE of pdp_ram_0_0_1 : label is "fifo_32_data.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_0_1 : label is ""; - attribute RESETMODE of pdp_ram_0_0_1 : label is "SYNC"; - attribute MEM_LPC_FILE of pdp_ram_0_1_0 : label is "fifo_32_data.lpc"; - attribute MEM_INIT_FILE of pdp_ram_0_1_0 : label is ""; - attribute RESETMODE of pdp_ram_0_1_0 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_0_3 : label is "fifo_32_data.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_0_3 : label is ""; + attribute RESETMODE of pdp_ram_0_0_3 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_1_2 : label is "fifo_32_data.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_1_2 : label is ""; + attribute RESETMODE of pdp_ram_0_1_2 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_2_1 : label is "fifo_32_data.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_2_1 : label is ""; + attribute RESETMODE of pdp_ram_0_2_1 : label is "SYNC"; + attribute MEM_LPC_FILE of pdp_ram_0_3_0 : label is "fifo_32_data.lpc"; + attribute MEM_INIT_FILE of pdp_ram_0_3_0 : label is ""; + attribute RESETMODE of pdp_ram_0_3_0 : label is "SYNC"; + attribute GSR of FF_74 : label is "ENABLED"; + attribute GSR of FF_73 : label is "ENABLED"; + attribute GSR of FF_72 : label is "ENABLED"; + attribute GSR of FF_71 : label is "ENABLED"; + attribute GSR of FF_70 : label is "ENABLED"; + attribute GSR of FF_69 : label is "ENABLED"; + attribute GSR of FF_68 : label is "ENABLED"; + attribute GSR of FF_67 : label is "ENABLED"; + attribute GSR of FF_66 : label is "ENABLED"; + attribute GSR of FF_65 : label is "ENABLED"; + attribute GSR of FF_64 : label is "ENABLED"; + attribute GSR of FF_63 : label is "ENABLED"; + attribute GSR of FF_62 : label is "ENABLED"; + attribute GSR of FF_61 : label is "ENABLED"; + attribute GSR of FF_60 : label is "ENABLED"; + attribute GSR of FF_59 : label is "ENABLED"; + attribute GSR of FF_58 : label is "ENABLED"; + attribute GSR of FF_57 : label is "ENABLED"; + attribute GSR of FF_56 : label is "ENABLED"; + attribute GSR of FF_55 : label is "ENABLED"; + attribute GSR of FF_54 : label is "ENABLED"; + attribute GSR of FF_53 : label is "ENABLED"; + attribute GSR of FF_52 : label is "ENABLED"; + attribute GSR of FF_51 : label is "ENABLED"; + attribute GSR of FF_50 : label is "ENABLED"; + attribute GSR of FF_49 : label is "ENABLED"; + attribute GSR of FF_48 : label is "ENABLED"; + attribute GSR of FF_47 : label is "ENABLED"; + attribute GSR of FF_46 : label is "ENABLED"; + attribute GSR of FF_45 : label is "ENABLED"; + attribute GSR of FF_44 : label is "ENABLED"; + attribute GSR of FF_43 : label is "ENABLED"; + attribute GSR of FF_42 : label is "ENABLED"; + attribute GSR of FF_41 : label is "ENABLED"; + attribute GSR of FF_40 : label is "ENABLED"; + attribute GSR of FF_39 : label is "ENABLED"; + attribute GSR of FF_38 : label is "ENABLED"; + attribute GSR of FF_37 : label is "ENABLED"; + attribute GSR of FF_36 : label is "ENABLED"; attribute GSR of FF_35 : label is "ENABLED"; attribute GSR of FF_34 : label is "ENABLED"; attribute GSR of FF_33 : label is "ENABLED"; @@ -330,28 +442,28 @@ architecture Structure of fifo_32_data is begin -- component instantiation statements - AND2_t4: AND2 + AND2_t5: AND2 port map (A=>WrEn, B=>invout_2, Z=>wren_i); - INV_8: INV + INV_5: INV port map (A=>full_i, Z=>invout_2); - AND2_t3: AND2 + AND2_t4: AND2 port map (A=>RdEn, B=>invout_1, Z=>rden_i); - INV_7: INV + INV_4: INV port map (A=>empty_i, Z=>invout_1); - AND2_t2: AND2 + AND2_t3: AND2 port map (A=>wren_i, B=>rden_i_inv, Z=>cnt_con); - XOR2_t1: XOR2 + XOR2_t2: XOR2 port map (A=>wren_i, B=>rden_i, Z=>fcnt_en); - INV_6: INV + INV_3: INV port map (A=>rden_i, Z=>rden_i_inv); - INV_5: INV + INV_2: INV port map (A=>wren_i, Z=>wren_i_inv); LUT4_1: ROM16X1A @@ -364,81 +476,111 @@ begin port map (AD3=>scuba_vlo, AD2=>cmp_ge_d1, AD1=>rden_i, AD0=>full_i, DO0=>full_d); - AND2_t0: AND2 + AND2_t1: AND2 port map (A=>rden_i, B=>invout_0, Z=>r_nw); - INV_4: INV + INV_1: INV port map (A=>wren_i, Z=>invout_0); - INV_3: INV - port map (A=>fcnt_en, Z=>fcnt_en_inv); - - INV_2: INV - port map (A=>cnt_con, Z=>cnt_con_inv); - - INV_1: INV - port map (A=>r_nw, Z=>r_nw_inv); + XOR2_t0: XOR2 + port map (A=>wcount_11, B=>rptr_11, Z=>wcnt_sub_msb); INV_0: INV - port map (A=>fcnt_en_inv, Z=>fcnt_en_inv_inv); + port map (A=>cnt_con, Z=>cnt_con_inv); - pdp_ram_0_0_1: DP16KC + pdp_ram_0_0_3: DP16KC generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) port map (DIA0=>Data(0), DIA1=>Data(1), DIA2=>Data(2), DIA3=>Data(3), DIA4=>Data(4), DIA5=>Data(5), DIA6=>Data(6), - DIA7=>Data(7), DIA8=>Data(8), DIA9=>Data(9), DIA10=>Data(10), - DIA11=>Data(11), DIA12=>Data(12), DIA13=>Data(13), - DIA14=>Data(14), DIA15=>Data(15), DIA16=>Data(16), - DIA17=>Data(17), ADA0=>scuba_vhi, ADA1=>scuba_vhi, - ADA2=>scuba_vlo, ADA3=>scuba_vlo, ADA4=>wcount_0, - ADA5=>wcount_1, ADA6=>wcount_2, ADA7=>wcount_3, - ADA8=>wcount_4, ADA9=>wcount_5, ADA10=>wcount_6, - ADA11=>wcount_7, ADA12=>wcount_8, ADA13=>wcount_9, - CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, - CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, - RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, - DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, - DIB5=>scuba_vlo, DIB6=>scuba_vlo, DIB7=>scuba_vlo, - DIB8=>scuba_vlo, DIB9=>scuba_vlo, DIB10=>scuba_vlo, - DIB11=>scuba_vlo, DIB12=>scuba_vlo, DIB13=>scuba_vlo, - DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, - DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, - ADB2=>scuba_vlo, ADB3=>scuba_vlo, ADB4=>rcount_0, - ADB5=>rcount_1, ADB6=>rcount_2, ADB7=>rcount_3, - ADB8=>rcount_4, ADB9=>rcount_5, ADB10=>rcount_6, - ADB11=>rcount_7, ADB12=>rcount_8, ADB13=>rcount_9, - CEB=>rden_i, CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + DIA7=>Data(7), DIA8=>Data(8), DIA9=>scuba_vlo, + DIA10=>scuba_vlo, DIA11=>scuba_vlo, DIA12=>scuba_vlo, + DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, + DIA16=>scuba_vlo, DIA17=>scuba_vlo, ADA0=>scuba_vlo, + ADA1=>scuba_vlo, ADA2=>scuba_vlo, ADA3=>wptr_0, ADA4=>wptr_1, + ADA5=>wptr_2, ADA6=>wptr_3, ADA7=>wptr_4, ADA8=>wptr_5, + ADA9=>wptr_6, ADA10=>wptr_7, ADA11=>wptr_8, ADA12=>wptr_9, + ADA13=>wptr_10, CEA=>wren_i, CLKA=>Clock, OCEA=>wren_i, + WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, + CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, + DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, + DIB4=>scuba_vlo, DIB5=>scuba_vlo, DIB6=>scuba_vlo, + DIB7=>scuba_vlo, DIB8=>scuba_vlo, DIB9=>scuba_vlo, + DIB10=>scuba_vlo, DIB11=>scuba_vlo, DIB12=>scuba_vlo, + DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, + DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, + ADB1=>scuba_vlo, ADB2=>scuba_vlo, ADB3=>rptr_0, ADB4=>rptr_1, + ADB5=>rptr_2, ADB6=>rptr_3, ADB7=>rptr_4, ADB8=>rptr_5, + ADB9=>rptr_6, ADB10=>rptr_7, ADB11=>rptr_8, ADB12=>rptr_9, + ADB13=>rptr_10, CEB=>rden_i, CLKB=>Clock, OCEB=>scuba_vhi, + WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, + CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, + DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, + DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, + DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, + DOA16=>open, DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), + DOB3=>Q(3), DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), + DOB8=>Q(8), DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + pdp_ram_0_1_2: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(9), DIA1=>Data(10), DIA2=>Data(11), + DIA3=>Data(12), DIA4=>Data(13), DIA5=>Data(14), + DIA6=>Data(15), DIA7=>Data(16), DIA8=>Data(17), + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, - DOA17=>open, DOB0=>Q(0), DOB1=>Q(1), DOB2=>Q(2), DOB3=>Q(3), - DOB4=>Q(4), DOB5=>Q(5), DOB6=>Q(6), DOB7=>Q(7), DOB8=>Q(8), - DOB9=>Q(9), DOB10=>Q(10), DOB11=>Q(11), DOB12=>Q(12), - DOB13=>Q(13), DOB14=>Q(14), DOB15=>Q(15), DOB16=>Q(16), - DOB17=>Q(17)); + DOA17=>open, DOB0=>Q(9), DOB1=>Q(10), DOB2=>Q(11), + DOB3=>Q(12), DOB4=>Q(13), DOB5=>Q(14), DOB6=>Q(15), + DOB7=>Q(16), DOB8=>Q(17), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); - pdp_ram_0_1_0: DP16KC + pdp_ram_0_2_1: DP16KC generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", - REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 18, - DATA_WIDTH_A=> 18) + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) port map (DIA0=>Data(18), DIA1=>Data(19), DIA2=>Data(20), DIA3=>Data(21), DIA4=>Data(22), DIA5=>Data(23), DIA6=>Data(24), DIA7=>Data(25), DIA8=>Data(26), - DIA9=>Data(27), DIA10=>Data(28), DIA11=>Data(29), - DIA12=>Data(30), DIA13=>Data(31), DIA14=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, - ADA0=>scuba_vhi, ADA1=>scuba_vhi, ADA2=>scuba_vlo, - ADA3=>scuba_vlo, ADA4=>wcount_0, ADA5=>wcount_1, - ADA6=>wcount_2, ADA7=>wcount_3, ADA8=>wcount_4, - ADA9=>wcount_5, ADA10=>wcount_6, ADA11=>wcount_7, - ADA12=>wcount_8, ADA13=>wcount_9, CEA=>wren_i, CLKA=>Clock, - OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, @@ -447,162 +589,344 @@ begin DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, - ADB3=>scuba_vlo, ADB4=>rcount_0, ADB5=>rcount_1, - ADB6=>rcount_2, ADB7=>rcount_3, ADB8=>rcount_4, - ADB9=>rcount_5, ADB10=>rcount_6, ADB11=>rcount_7, - ADB12=>rcount_8, ADB13=>rcount_9, CEB=>rden_i, CLKB=>Clock, - OCEB=>scuba_vhi, WEB=>scuba_vlo, CSB0=>scuba_vlo, - CSB1=>scuba_vlo, CSB2=>scuba_vlo, RSTB=>Reset, DOA0=>open, - DOA1=>open, DOA2=>open, DOA3=>open, DOA4=>open, DOA5=>open, - DOA6=>open, DOA7=>open, DOA8=>open, DOA9=>open, DOA10=>open, - DOA11=>open, DOA12=>open, DOA13=>open, DOA14=>open, - DOA15=>open, DOA16=>open, DOA17=>open, DOB0=>Q(18), - DOB1=>Q(19), DOB2=>Q(20), DOB3=>Q(21), DOB4=>Q(22), - DOB5=>Q(23), DOB6=>Q(24), DOB7=>Q(25), DOB8=>Q(26), - DOB9=>Q(27), DOB10=>Q(28), DOB11=>Q(29), DOB12=>Q(30), - DOB13=>Q(31), DOB14=>open, DOB15=>open, DOB16=>open, - DOB17=>open); + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(18), DOB1=>Q(19), DOB2=>Q(20), + DOB3=>Q(21), DOB4=>Q(22), DOB5=>Q(23), DOB6=>Q(24), + DOB7=>Q(25), DOB8=>Q(26), DOB9=>open, DOB10=>open, + DOB11=>open, DOB12=>open, DOB13=>open, DOB14=>open, + DOB15=>open, DOB16=>open, DOB17=>open); - FF_35: FD1P3DX + pdp_ram_0_3_0: DP16KC + generic map (CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", + WRITEMODE_B=> "NORMAL", WRITEMODE_A=> "NORMAL", GSR=> "DISABLED", + REGMODE_B=> "OUTREG", REGMODE_A=> "OUTREG", DATA_WIDTH_B=> 9, + DATA_WIDTH_A=> 9) + port map (DIA0=>Data(27), DIA1=>Data(28), DIA2=>Data(29), + DIA3=>Data(30), DIA4=>Data(31), DIA5=>scuba_vlo, + DIA6=>scuba_vlo, DIA7=>scuba_vlo, DIA8=>scuba_vlo, + DIA9=>scuba_vlo, DIA10=>scuba_vlo, DIA11=>scuba_vlo, + DIA12=>scuba_vlo, DIA13=>scuba_vlo, DIA14=>scuba_vlo, + DIA15=>scuba_vlo, DIA16=>scuba_vlo, DIA17=>scuba_vlo, + ADA0=>scuba_vlo, ADA1=>scuba_vlo, ADA2=>scuba_vlo, + ADA3=>wptr_0, ADA4=>wptr_1, ADA5=>wptr_2, ADA6=>wptr_3, + ADA7=>wptr_4, ADA8=>wptr_5, ADA9=>wptr_6, ADA10=>wptr_7, + ADA11=>wptr_8, ADA12=>wptr_9, ADA13=>wptr_10, CEA=>wren_i, + CLKA=>Clock, OCEA=>wren_i, WEA=>scuba_vhi, CSA0=>scuba_vlo, + CSA1=>scuba_vlo, CSA2=>scuba_vlo, RSTA=>Reset, + DIB0=>scuba_vlo, DIB1=>scuba_vlo, DIB2=>scuba_vlo, + DIB3=>scuba_vlo, DIB4=>scuba_vlo, DIB5=>scuba_vlo, + DIB6=>scuba_vlo, DIB7=>scuba_vlo, DIB8=>scuba_vlo, + DIB9=>scuba_vlo, DIB10=>scuba_vlo, DIB11=>scuba_vlo, + DIB12=>scuba_vlo, DIB13=>scuba_vlo, DIB14=>scuba_vlo, + DIB15=>scuba_vlo, DIB16=>scuba_vlo, DIB17=>scuba_vlo, + ADB0=>scuba_vlo, ADB1=>scuba_vlo, ADB2=>scuba_vlo, + ADB3=>rptr_0, ADB4=>rptr_1, ADB5=>rptr_2, ADB6=>rptr_3, + ADB7=>rptr_4, ADB8=>rptr_5, ADB9=>rptr_6, ADB10=>rptr_7, + ADB11=>rptr_8, ADB12=>rptr_9, ADB13=>rptr_10, CEB=>rden_i, + CLKB=>Clock, OCEB=>scuba_vhi, WEB=>scuba_vlo, + CSB0=>scuba_vlo, CSB1=>scuba_vlo, CSB2=>scuba_vlo, + RSTB=>Reset, DOA0=>open, DOA1=>open, DOA2=>open, DOA3=>open, + DOA4=>open, DOA5=>open, DOA6=>open, DOA7=>open, DOA8=>open, + DOA9=>open, DOA10=>open, DOA11=>open, DOA12=>open, + DOA13=>open, DOA14=>open, DOA15=>open, DOA16=>open, + DOA17=>open, DOB0=>Q(27), DOB1=>Q(28), DOB2=>Q(29), + DOB3=>Q(30), DOB4=>Q(31), DOB5=>open, DOB6=>open, DOB7=>open, + DOB8=>open, DOB9=>open, DOB10=>open, DOB11=>open, + DOB12=>open, DOB13=>open, DOB14=>open, DOB15=>open, + DOB16=>open, DOB17=>open); + + FF_74: FD1P3DX port map (D=>ifcount_0, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_0); - FF_34: FD1P3DX + FF_73: FD1P3DX port map (D=>ifcount_1, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_1); - FF_33: FD1P3DX + FF_72: FD1P3DX port map (D=>ifcount_2, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_2); - FF_32: FD1P3DX + FF_71: FD1P3DX port map (D=>ifcount_3, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_3); - FF_31: FD1P3DX + FF_70: FD1P3DX port map (D=>ifcount_4, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_4); - FF_30: FD1P3DX + FF_69: FD1P3DX port map (D=>ifcount_5, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_5); - FF_29: FD1P3DX + FF_68: FD1P3DX port map (D=>ifcount_6, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_6); - FF_28: FD1P3DX + FF_67: FD1P3DX port map (D=>ifcount_7, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_7); - FF_27: FD1P3DX + FF_66: FD1P3DX port map (D=>ifcount_8, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_8); - FF_26: FD1P3DX + FF_65: FD1P3DX port map (D=>ifcount_9, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_9); - FF_25: FD1P3DX + FF_64: FD1P3DX port map (D=>ifcount_10, SP=>fcnt_en, CK=>Clock, CD=>Reset, Q=>fcount_10); - FF_24: FD1S3BX + FF_63: FD1P3DX + port map (D=>ifcount_11, SP=>fcnt_en, CK=>Clock, CD=>Reset, + Q=>fcount_11); + + FF_62: FD1S3BX port map (D=>empty_d, CK=>Clock, PD=>Reset, Q=>empty_i); - FF_23: FD1S3DX + FF_61: FD1S3DX port map (D=>full_d, CK=>Clock, CD=>Reset, Q=>full_i); - FF_22: FD1P3DX - port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + FF_60: FD1P3BX + port map (D=>iwcount_0, SP=>wren_i, CK=>Clock, PD=>Reset, Q=>wcount_0); - FF_21: FD1P3DX + FF_59: FD1P3DX port map (D=>iwcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_1); - FF_20: FD1P3DX + FF_58: FD1P3DX port map (D=>iwcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_2); - FF_19: FD1P3DX + FF_57: FD1P3DX port map (D=>iwcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_3); - FF_18: FD1P3DX + FF_56: FD1P3DX port map (D=>iwcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_4); - FF_17: FD1P3DX + FF_55: FD1P3DX port map (D=>iwcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_5); - FF_16: FD1P3DX + FF_54: FD1P3DX port map (D=>iwcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_6); - FF_15: FD1P3DX + FF_53: FD1P3DX port map (D=>iwcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_7); - FF_14: FD1P3DX + FF_52: FD1P3DX port map (D=>iwcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_8); - FF_13: FD1P3DX + FF_51: FD1P3DX port map (D=>iwcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_9); - FF_12: FD1P3DX + FF_50: FD1P3DX port map (D=>iwcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, Q=>wcount_10); - FF_11: FD1P3DX - port map (D=>ircount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + FF_49: FD1P3DX + port map (D=>iwcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wcount_11); + + FF_48: FD1P3BX + port map (D=>ircount_0, SP=>rden_i, CK=>Clock, PD=>Reset, Q=>rcount_0); - FF_10: FD1P3DX + FF_47: FD1P3DX port map (D=>ircount_1, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_1); - FF_9: FD1P3DX + FF_46: FD1P3DX port map (D=>ircount_2, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_2); - FF_8: FD1P3DX + FF_45: FD1P3DX port map (D=>ircount_3, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_3); - FF_7: FD1P3DX + FF_44: FD1P3DX port map (D=>ircount_4, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_4); - FF_6: FD1P3DX + FF_43: FD1P3DX port map (D=>ircount_5, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_5); - FF_5: FD1P3DX + FF_42: FD1P3DX port map (D=>ircount_6, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_6); - FF_4: FD1P3DX + FF_41: FD1P3DX port map (D=>ircount_7, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_7); - FF_3: FD1P3DX + FF_40: FD1P3DX port map (D=>ircount_8, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_8); - FF_2: FD1P3DX + FF_39: FD1P3DX port map (D=>ircount_9, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_9); - FF_1: FD1P3DX + FF_38: FD1P3DX port map (D=>ircount_10, SP=>rden_i, CK=>Clock, CD=>Reset, Q=>rcount_10); + FF_37: FD1P3DX + port map (D=>ircount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rcount_11); + + FF_36: FD1P3DX + port map (D=>wcount_0, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_0); + + FF_35: FD1P3DX + port map (D=>wcount_1, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_1); + + FF_34: FD1P3DX + port map (D=>wcount_2, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_2); + + FF_33: FD1P3DX + port map (D=>wcount_3, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_3); + + FF_32: FD1P3DX + port map (D=>wcount_4, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_4); + + FF_31: FD1P3DX + port map (D=>wcount_5, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_5); + + FF_30: FD1P3DX + port map (D=>wcount_6, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_6); + + FF_29: FD1P3DX + port map (D=>wcount_7, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_7); + + FF_28: FD1P3DX + port map (D=>wcount_8, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_8); + + FF_27: FD1P3DX + port map (D=>wcount_9, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_9); + + FF_26: FD1P3DX + port map (D=>wcount_10, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_10); + + FF_25: FD1P3DX + port map (D=>wcount_11, SP=>wren_i, CK=>Clock, CD=>Reset, + Q=>wptr_11); + + FF_24: FD1P3DX + port map (D=>rcount_0, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_0); + + FF_23: FD1P3DX + port map (D=>rcount_1, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_1); + + FF_22: FD1P3DX + port map (D=>rcount_2, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_2); + + FF_21: FD1P3DX + port map (D=>rcount_3, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_3); + + FF_20: FD1P3DX + port map (D=>rcount_4, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_4); + + FF_19: FD1P3DX + port map (D=>rcount_5, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_5); + + FF_18: FD1P3DX + port map (D=>rcount_6, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_6); + + FF_17: FD1P3DX + port map (D=>rcount_7, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_7); + + FF_16: FD1P3DX + port map (D=>rcount_8, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_8); + + FF_15: FD1P3DX + port map (D=>rcount_9, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_9); + + FF_14: FD1P3DX + port map (D=>rcount_10, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_10); + + FF_13: FD1P3DX + port map (D=>rcount_11, SP=>rden_i, CK=>Clock, CD=>Reset, + Q=>rptr_11); + + FF_12: FD1S3DX + port map (D=>wcnt_sub_0, CK=>Clock, CD=>Reset, Q=>wcnt_reg_0); + + FF_11: FD1S3DX + port map (D=>wcnt_sub_1, CK=>Clock, CD=>Reset, Q=>wcnt_reg_1); + + FF_10: FD1S3DX + port map (D=>wcnt_sub_2, CK=>Clock, CD=>Reset, Q=>wcnt_reg_2); + + FF_9: FD1S3DX + port map (D=>wcnt_sub_3, CK=>Clock, CD=>Reset, Q=>wcnt_reg_3); + + FF_8: FD1S3DX + port map (D=>wcnt_sub_4, CK=>Clock, CD=>Reset, Q=>wcnt_reg_4); + + FF_7: FD1S3DX + port map (D=>wcnt_sub_5, CK=>Clock, CD=>Reset, Q=>wcnt_reg_5); + + FF_6: FD1S3DX + port map (D=>wcnt_sub_6, CK=>Clock, CD=>Reset, Q=>wcnt_reg_6); + + FF_5: FD1S3DX + port map (D=>wcnt_sub_7, CK=>Clock, CD=>Reset, Q=>wcnt_reg_7); + + FF_4: FD1S3DX + port map (D=>wcnt_sub_8, CK=>Clock, CD=>Reset, Q=>wcnt_reg_8); + + FF_3: FD1S3DX + port map (D=>wcnt_sub_9, CK=>Clock, CD=>Reset, Q=>wcnt_reg_9); + + FF_2: FD1S3DX + port map (D=>wcnt_sub_10, CK=>Clock, CD=>Reset, Q=>wcnt_reg_10); + + FF_1: FD1S3DX + port map (D=>wcnt_sub_11, CK=>Clock, CD=>Reset, Q=>wcnt_reg_11); + FF_0: FD1S3DX - port map (D=>af_d, CK=>Clock, CD=>Reset, Q=>AlmostFull); + port map (D=>af_set, CK=>Clock, CD=>Reset, Q=>AlmostFull); bdcnt_bctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>cnt_con, B0=>scuba_vlo, B1=>cnt_con, @@ -629,8 +953,8 @@ begin CO=>co4, NC0=>ifcount_8, NC1=>ifcount_9); bdcnt_bctr_5: CB2 - port map (CI=>co4, PC0=>fcount_10, PC1=>scuba_vlo, CON=>cnt_con, - CO=>co5, NC0=>ifcount_10, NC1=>open); + port map (CI=>co4, PC0=>fcount_10, PC1=>fcount_11, CON=>cnt_con, + CO=>co5, NC0=>ifcount_10, NC1=>ifcount_11); e_cmp_ci_a: FADD2B port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, @@ -658,7 +982,7 @@ begin B1=>scuba_vlo, CI=>co3_1, LE=>co4_1); e_cmp_5: ALEB2 - port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, + port map (A0=>fcount_10, A1=>fcount_11, B0=>scuba_vlo, B1=>scuba_vlo, CI=>co4_1, LE=>cmp_le_1_c); a0: FADD2B @@ -692,8 +1016,8 @@ begin CI=>co3_2, GE=>co4_2); g_cmp_5: AGEB2 - port map (A0=>fcount_10, A1=>scuba_vlo, B0=>wren_i_inv, - B1=>scuba_vlo, CI=>co4_2, GE=>cmp_ge_d1_c); + port map (A0=>fcount_10, A1=>fcount_11, B0=>wren_i, + B1=>wren_i_inv, CI=>co4_2, GE=>cmp_ge_d1_c); a1: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, @@ -726,8 +1050,11 @@ begin NC0=>iwcount_8, NC1=>iwcount_9); w_ctr_5: CU2 - port map (CI=>co4_3, PC0=>wcount_10, PC1=>scuba_vlo, CO=>co5_1, - NC0=>iwcount_10, NC1=>open); + port map (CI=>co4_3, PC0=>wcount_10, PC1=>wcount_11, CO=>co5_1, + NC0=>iwcount_10, NC1=>iwcount_11); + + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); r_ctr_cia: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo, @@ -755,59 +1082,74 @@ begin NC0=>ircount_8, NC1=>ircount_9); r_ctr_5: CU2 - port map (CI=>co4_4, PC0=>rcount_10, PC1=>scuba_vlo, CO=>co5_2, - NC0=>ircount_10, NC1=>open); + port map (CI=>co4_4, PC0=>rcount_10, PC1=>rcount_11, CO=>co5_2, + NC0=>ircount_10, NC1=>ircount_11); - af_cmp_ci_a: FADD2B - port map (A0=>scuba_vhi, A1=>scuba_vhi, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, + wcnt_0: FSUB2B + port map (A0=>cnt_con, A1=>wcount_0, B0=>cnt_con_inv, B1=>rptr_0, + BI=>scuba_vlo, BOUT=>co0_5, S0=>open, S1=>wcnt_sub_0); + + wcnt_1: FSUB2B + port map (A0=>wcount_1, A1=>wcount_2, B0=>rptr_1, B1=>rptr_2, + BI=>co0_5, BOUT=>co1_5, S0=>wcnt_sub_1, S1=>wcnt_sub_2); + + wcnt_2: FSUB2B + port map (A0=>wcount_3, A1=>wcount_4, B0=>rptr_3, B1=>rptr_4, + BI=>co1_5, BOUT=>co2_5, S0=>wcnt_sub_3, S1=>wcnt_sub_4); + + wcnt_3: FSUB2B + port map (A0=>wcount_5, A1=>wcount_6, B0=>rptr_5, B1=>rptr_6, + BI=>co2_5, BOUT=>co3_5, S0=>wcnt_sub_5, S1=>wcnt_sub_6); + + wcnt_4: FSUB2B + port map (A0=>wcount_7, A1=>wcount_8, B0=>rptr_7, B1=>rptr_8, + BI=>co3_5, BOUT=>co4_5, S0=>wcnt_sub_7, S1=>wcnt_sub_8); + + wcnt_5: FSUB2B + port map (A0=>wcount_9, A1=>wcount_10, B0=>rptr_9, B1=>rptr_10, + BI=>co4_5, BOUT=>co5_3, S0=>wcnt_sub_9, S1=>wcnt_sub_10); + + wcnt_6: FSUB2B + port map (A0=>wcnt_sub_msb, A1=>scuba_vlo, B0=>scuba_vlo, + B1=>scuba_vlo, BI=>co5_3, BOUT=>open, S0=>wcnt_sub_11, S1=>open); - af_cmp_0: AGEB2 - port map (A0=>fcount_0, A1=>fcount_1, B0=>fcnt_en_inv_inv, - B1=>cnt_con, CI=>cmp_ci_2, GE=>co0_5); + af_set_cmp_ci_a: FADD2B + port map (A0=>scuba_vlo, A1=>wren_i, B0=>scuba_vlo, B1=>wren_i, + CI=>scuba_vlo, COUT=>cmp_ci_2, S0=>open, S1=>open); - af_cmp_1: AGEB2 - port map (A0=>fcount_2, A1=>fcount_3, B0=>cnt_con_inv, - B1=>scuba_vhi, CI=>co0_5, GE=>co1_5); + af_set_cmp_0: AGEB2 + port map (A0=>wcnt_reg_0, A1=>wcnt_reg_1, B0=>AmFullThresh(0), + B1=>AmFullThresh(1), CI=>cmp_ci_2, GE=>co0_6); - af_cmp_2: AGEB2 - port map (A0=>fcount_4, A1=>fcount_5, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>co1_5, GE=>co2_5); + af_set_cmp_1: AGEB2 + port map (A0=>wcnt_reg_2, A1=>wcnt_reg_3, B0=>AmFullThresh(2), + B1=>AmFullThresh(3), CI=>co0_6, GE=>co1_6); - af_cmp_3: AGEB2 - port map (A0=>fcount_6, A1=>fcount_7, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>co2_5, GE=>co3_5); + af_set_cmp_2: AGEB2 + port map (A0=>wcnt_reg_4, A1=>wcnt_reg_5, B0=>AmFullThresh(4), + B1=>AmFullThresh(5), CI=>co1_6, GE=>co2_6); - scuba_vhi_inst: VHI - port map (Z=>scuba_vhi); + af_set_cmp_3: AGEB2 + port map (A0=>wcnt_reg_6, A1=>wcnt_reg_7, B0=>AmFullThresh(6), + B1=>AmFullThresh(7), CI=>co2_6, GE=>co3_6); - af_cmp_4: AGEB2 - port map (A0=>fcount_8, A1=>fcount_9, B0=>scuba_vhi, - B1=>scuba_vhi, CI=>co3_5, GE=>co4_5); + af_set_cmp_4: AGEB2 + port map (A0=>wcnt_reg_8, A1=>wcnt_reg_9, B0=>AmFullThresh(8), + B1=>AmFullThresh(9), CI=>co3_6, GE=>co4_6); - af_cmp_5: AGEB2 - port map (A0=>fcount_10, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>co4_5, GE=>af_d_c); + af_set_cmp_5: AGEB2 + port map (A0=>wcnt_reg_10, A1=>wcnt_reg_11, B0=>AmFullThresh(10), + B1=>scuba_vlo, CI=>co4_6, GE=>af_set_c); scuba_vlo_inst: VLO port map (Z=>scuba_vlo); a2: FADD2B port map (A0=>scuba_vlo, A1=>scuba_vlo, B0=>scuba_vlo, - B1=>scuba_vlo, CI=>af_d_c, COUT=>open, S0=>af_d, S1=>open); - - WCNT(0) <= fcount_0; - WCNT(1) <= fcount_1; - WCNT(2) <= fcount_2; - WCNT(3) <= fcount_3; - WCNT(4) <= fcount_4; - WCNT(5) <= fcount_5; - WCNT(6) <= fcount_6; - WCNT(7) <= fcount_7; - WCNT(8) <= fcount_8; - WCNT(9) <= fcount_9; - WCNT(10) <= fcount_10; + B1=>scuba_vlo, CI=>af_set_c, COUT=>open, S0=>af_set, + S1=>open); + Empty <= empty_i; Full <= full_i; end Structure; @@ -822,6 +1164,8 @@ configuration Structure_CON of fifo_32_data is for all:CU2 use entity ecp3.CU2(V); end for; for all:CB2 use entity ecp3.CB2(V); end for; for all:FADD2B use entity ecp3.FADD2B(V); end for; + for all:FSUB2B use entity ecp3.FSUB2B(V); end for; + for all:FD1P3BX use entity ecp3.FD1P3BX(V); end for; for all:FD1P3DX use entity ecp3.FD1P3DX(V); end for; for all:FD1S3BX use entity ecp3.FD1S3BX(V); end for; for all:FD1S3DX use entity ecp3.FD1S3DX(V); end for; diff --git a/nxyter/source/nx_data_receiver.vhd b/nxyter/source/nx_data_receiver.vhd index 8685653..df9a729 100644 --- a/nxyter/source/nx_data_receiver.vhd +++ b/nxyter/source/nx_data_receiver.vhd @@ -69,7 +69,6 @@ architecture Behavioral of nx_data_receiver is signal nx_fifo_full : std_logic; signal nx_fifo_delay : unsigned(3 downto 0); signal nx_fifo_reset : std_logic; - signal nx_fifo_reset_l : std_logic; -- NX_TIMESTAMP_IN Process signal frame_byte_ctr : unsigned(1 downto 0); @@ -115,34 +114,35 @@ architecture Behavioral of nx_data_receiver is signal adc_reset_sync_s : std_logic; signal adc_reset_sync : std_logic; signal adc_reset_ctr : unsigned(11 downto 0); - signal output_handler_reset : std_logic; -- Reset Handler signal startup_reset : std_logic; signal rs_wait_timer_start : std_logic; signal rs_wait_timer_done : std_logic; + + signal rs_timeout_timer_start : std_logic; + signal rs_timeout_timer_done : std_logic; + signal rs_timeout_timer_reset : std_logic; type R_STATES is (R_IDLE, + R_SET_ALL_RESETS, R_WAIT_1, - R_WAIT_2, R_WAIT_NX_FRAME_RATE_OK, - R_PLL_RESET, - R_PLL_WAIT_UNLOCK, R_PLL_WAIT_LOCK, - R_WAIT_RESET_ADC, R_WAIT_ADC_OK, - --R_WAIT_ADC_SETTLED, - R_WAIT_RESET_DATA_HANDLER + R_WAIT_DATA_HANDLER_OK ); signal R_STATE : R_STATES; - signal sampling_clk_reset_p : std_logic; + signal frame_rates_reset : std_logic; signal sampling_clk_reset : std_logic; + signal adc_reset : std_logic; signal adc_reset_p : std_logic; - signal ADC_RESET_AD9228 : std_logic; + signal output_handler_reset : std_logic; + signal reset_handler_counter : unsigned(15 downto 0); signal reset_handler_busy : std_logic; - signal frame_rates_reset : std_logic; + signal reset_timeout_flag : std_logic; ----------------------------------------------------------------------------- -- CLK_IN Domain @@ -179,6 +179,7 @@ architecture Behavioral of nx_data_receiver is ----------------------------------------------------------------------------- -- ADC Handler + signal ADC_RESET_AD9228 : std_logic; signal adc_data : std_logic_vector(11 downto 0); signal test_adc_data : std_logic_vector(11 downto 0); signal adc_data_valid : std_logic; @@ -219,6 +220,8 @@ architecture Behavioral of nx_data_receiver is signal adc_frame_rate : unsigned(27 downto 0); signal frame_rate_ctr : unsigned(27 downto 0); signal frame_rate : unsigned(27 downto 0); + signal parity_rate_ctr : unsigned(27 downto 0); + signal parity_rate : unsigned(27 downto 0); signal rate_timer_ctr : unsigned(27 downto 0); -- Error @@ -233,6 +236,7 @@ architecture Behavioral of nx_data_receiver is signal nx_frame_rate_error : std_logic; signal adc_frame_rate_error : std_logic; signal frame_rate_error : std_logic; + signal parity_rate_error : std_logic; signal reset_for_offline : std_logic; -- Slave Bus @@ -311,7 +315,7 @@ begin DEBUG_OUT(2) <= adc_clk_skip; DEBUG_OUT(3) <= adc_clk_ok; DEBUG_OUT(4) <= adc_reset_sync; - DEBUG_OUT(5) <= adc_reset_p; + DEBUG_OUT(5) <= adc_reset; DEBUG_OUT(6) <= ADC_RESET_AD9228; DEBUG_OUT(7) <= pll_adc_not_lock; DEBUG_OUT(8) <= reset_for_offline; @@ -327,18 +331,19 @@ begin when "11" => -- Test Channel DEBUG_OUT(0) <= CLK_IN; - DEBUG_OUT(4 downto 1) <= debug_state; - DEBUG_OUT(5) <= reset_handler_busy; - DEBUG_OUT(6) <= nx_frame_rate_offline; - DEBUG_OUT(7) <= nx_frame_rate_error; - DEBUG_OUT(8) <= pll_adc_not_lock; - DEBUG_OUT(9) <= error_adc0; - DEBUG_OUT(10) <= adc_frame_rate_error; - DEBUG_OUT(11) <= sampling_clk_reset_p; - DEBUG_OUT(12) <= adc_reset_p; - DEBUG_OUT(13) <= nx_fifo_reset; + DEBUG_OUT(3 downto 1) <= debug_state(2 downto 0); + DEBUG_OUT(4) <= reset_handler_busy; + DEBUG_OUT(5) <= nx_frame_rate_offline; + DEBUG_OUT(6) <= nx_frame_rate_error; + DEBUG_OUT(7) <= pll_adc_not_lock; + DEBUG_OUT(8) <= error_adc0; + DEBUG_OUT(9) <= adc_frame_rate_error; + DEBUG_OUT(10) <= nx_fifo_reset; + DEBUG_OUT(11) <= sampling_clk_reset; + DEBUG_OUT(12) <= adc_reset; + DEBUG_OUT(13) <= output_handler_reset; DEBUG_OUT(14) <= frame_rate_error; - DEBUG_OUT(15) <= '0'; + DEBUG_OUT(15) <= reset_timeout_flag; end case; end process PROC_DEBUG_MULT; @@ -439,7 +444,7 @@ begin end if; end process PROC_PLL_LOCK_COUNTER; - ADC_RESET_AD9228 <= RESET_IN or adc_reset_p; + ADC_RESET_AD9228 <= RESET_IN or adc_reset; adc_ad9228_1: adc_ad9228 port map ( CLK_IN => CLK_IN, @@ -487,8 +492,8 @@ begin timer_static_RESET_TIMER: timer_static generic map ( - CTR_WIDTH => 28, - CTR_END => 50000000 -- 50ms + CTR_WIDTH => 20, + CTR_END => 500000 -- 1ms ) port map ( CLK_IN => CLK_IN, @@ -497,6 +502,17 @@ begin TIMER_DONE_OUT => rs_wait_timer_done ); + timer_static_RESET_TIMEOUT: timer_static + generic map ( + CTR_WIDTH => 26, + CTR_END => 10000000 -- 1s + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => rs_timeout_timer_reset, + TIMER_START_IN => rs_timeout_timer_start, + TIMER_DONE_OUT => rs_timeout_timer_done + ); pulse_dtrans_1: pulse_dtrans generic map ( @@ -515,28 +531,45 @@ begin begin if (rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then - sampling_clk_reset_p <= '0'; - adc_reset_p <= '0'; + frame_rates_reset <= '0'; nx_fifo_reset <= '0'; + sampling_clk_reset <= '0'; + adc_reset_p <= '0'; + adc_reset <= '0'; output_handler_reset <= '0'; + rs_wait_timer_start <= '0'; + rs_timeout_timer_start <= '0'; + rs_timeout_timer_reset <= '1'; reset_handler_counter <= (others => '0'); - startup_reset <= '1'; reset_handler_busy <= '0'; + reset_timeout_flag <= '0'; + startup_reset <= '1'; R_STATE <= R_IDLE; else - sampling_clk_reset_p <= '0'; - adc_reset_p <= '0'; + frame_rates_reset <= '0'; nx_fifo_reset <= '0'; + sampling_clk_reset <= '0'; + adc_reset_p <= '0'; + adc_reset <= '0'; output_handler_reset <= '0'; + rs_wait_timer_start <= '0'; + rs_timeout_timer_start <= '0'; + rs_timeout_timer_reset <= '0'; reset_handler_busy <= '1'; - debug_state <= x"0"; + + debug_state <= x"0"; if (reset_handler_counter_clear = '1') then - reset_handler_counter <= (others => '0'); + reset_handler_counter <= (others => '0'); end if; - + + if (rs_timeout_timer_done = '1') then + -- Reset Timeout + reset_timeout_flag <= '1'; + end if; + case R_STATE is when R_IDLE => if (reset_for_offline = '1' or @@ -547,109 +580,94 @@ begin ) then if (reset_handler_counter_clear = '0') then reset_handler_counter <= reset_handler_counter + 1; - end if; - rs_wait_timer_start <= '1'; -- 50ms to settle down - R_STATE <= R_WAIT_1; + end if; + R_STATE <= R_SET_ALL_RESETS; else - reset_handler_busy <= '0'; - R_STATE <= R_IDLE; + reset_handler_busy <= '0'; + R_STATE <= R_IDLE; end if; + when R_SET_ALL_RESETS => + frame_rates_reset <= '1'; + nx_fifo_reset <= '1'; + sampling_clk_reset <= '1'; + adc_reset_p <= '1'; + adc_reset <= '1'; + output_handler_reset <= '1'; + + rs_wait_timer_start <= '1'; -- wait 1mue to settle + R_STATE <= R_WAIT_1; + debug_state <= x"1"; + when R_WAIT_1 => if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_1; + nx_fifo_reset <= '1'; + sampling_clk_reset <= '1'; + adc_reset <= '1'; + output_handler_reset <= '1'; + R_STATE <= R_WAIT_1; else - nx_fifo_reset <= '1'; - rs_wait_timer_start <= '1'; -- 50ms to settle down - R_STATE <= R_WAIT_2; + -- Release NX Fifo Reset + Start Timeout HAndler + sampling_clk_reset <= '1'; + adc_reset <= '1'; + output_handler_reset <= '1'; + reset_timeout_flag <= '0'; + rs_timeout_timer_start <= '1'; + R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; - debug_state <= x"1"; + debug_state <= x"2"; - when R_WAIT_2 => - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_2; - else - R_STATE <= R_WAIT_NX_FRAME_RATE_OK; - end if; - debug_state <= x"2"; - when R_WAIT_NX_FRAME_RATE_OK => if (nx_frame_rate_offline = '0' and nx_frame_rate_error = '0') then - R_STATE <= R_PLL_RESET; - else - R_STATE <= R_WAIT_NX_FRAME_RATE_OK; - end if; - debug_state <= x"3"; - - when R_PLL_RESET => - sampling_clk_reset_p <= '1'; - R_STATE <= R_PLL_WAIT_UNLOCK; - - debug_state <= x"4"; - - when R_PLL_WAIT_UNLOCK => - if (pll_adc_not_lock = '0') then - R_STATE <= R_PLL_WAIT_UNLOCK; + -- Release PLL Reset + adc_reset <= '1'; + output_handler_reset <= '1'; + R_STATE <= R_PLL_WAIT_LOCK; else - R_STATE <= R_PLL_WAIT_LOCK; + sampling_clk_reset <= '1'; + adc_reset <= '1'; + output_handler_reset <= '1'; + R_STATE <= R_WAIT_NX_FRAME_RATE_OK; end if; - debug_state <= x"5"; + debug_state <= x"3"; when R_PLL_WAIT_LOCK => if (pll_adc_not_lock = '1') then - R_STATE <= R_PLL_WAIT_LOCK; - else - rs_wait_timer_start <= '1'; -- 50ms - R_STATE <= R_WAIT_RESET_ADC; - end if; - debug_state <= x"6"; - - when R_WAIT_RESET_ADC => - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_RESET_ADC; + adc_reset <= '1'; + output_handler_reset <= '1'; + R_STATE <= R_PLL_WAIT_LOCK; else - adc_reset_p <= '1'; - R_STATE <= R_WAIT_ADC_OK; + -- Release ADC Reset + output_handler_reset <= '1'; + R_STATE <= R_WAIT_ADC_OK; end if; - debug_state <= x"7"; - - when R_WAIT_ADC_OK => + debug_state <= x"4"; + + when R_WAIT_ADC_OK => if (error_adc0 = '0' and adc_frame_rate_error = '0') then - output_handler_reset <= '1'; - rs_wait_timer_start <= '1'; -- 50ms - R_STATE <= R_WAIT_RESET_DATA_HANDLER; + -- Release Output Handler Reset + R_STATE <= R_WAIT_DATA_HANDLER_OK; else - R_STATE <= R_WAIT_ADC_OK; + R_STATE <= R_WAIT_ADC_OK; end if; - debug_state <= x"8"; + debug_state <= x"5"; - when R_WAIT_RESET_DATA_HANDLER => - if (rs_wait_timer_done = '0') then - R_STATE <= R_WAIT_RESET_DATA_HANDLER; + when R_WAIT_DATA_HANDLER_OK => + if (frame_rate_error = '0') then + startup_reset <= '0'; + R_STATE <= R_IDLE; else - startup_reset <= '0'; - R_STATE <= R_IDLE; + R_STATE <= R_WAIT_DATA_HANDLER_OK; end if; - debug_state <= x"9"; + debug_state <= x"6"; end case; end if; end if; end process PROC_RESET_HANDLER; - pulse_to_level_SAMPLING_CLK_RESET: pulse_to_level - generic map ( - NUM_CYCLES => 10 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - PULSE_IN => sampling_clk_reset_p, - LEVEL_OUT => sampling_clk_reset - ); - ----------------------------------------------------------------------------- -- NX_TIMESTAMP_CLK_IN Domain ----------------------------------------------------------------------------- @@ -773,8 +791,8 @@ begin RdClock => CLK_IN, WrEn => nx_fifo_write_enable, RdEn => nx_fifo_read_enable, - Reset => nx_fifo_reset_l, - RPReset => nx_fifo_reset_l, + Reset => nx_fifo_reset, + RPReset => nx_fifo_reset, Q => nx_fifo_data, Empty => nx_fifo_empty, Full => nx_fifo_full @@ -782,17 +800,6 @@ begin nx_fifo_write_enable <= nx_new_frame and not nx_fifo_full; - pulse_to_level_NX_FIFO_RESET: pulse_to_level - generic map ( - NUM_CYCLES => 5 - ) - port map ( - CLK_IN => CLK_IN, - RESET_IN => RESET_IN, - PULSE_IN => nx_fifo_reset, - LEVEL_OUT => nx_fifo_reset_l - ); - PROC_NX_CLK_ACT: process(NX_TIMESTAMP_CLK_IN) begin if (rising_edge(NX_TIMESTAMP_CLK_IN)) then @@ -1102,6 +1109,8 @@ begin adc_frame_rate <= (others => '0'); frame_rate_ctr <= (others => '0'); frame_rate <= (others => '0'); + parity_rate_ctr <= (others => '0'); + parity_rate <= (others => '0'); rate_timer_ctr <= (others => '0'); else if (rate_timer_ctr < x"5f5e100") then @@ -1118,11 +1127,16 @@ begin if (new_data_o = '1') then frame_rate_ctr <= frame_rate_ctr + 1; end if; + + if (parity_error_ctr_inc = '1') then + parity_rate_ctr <= parity_rate_ctr + 1; + end if; else rate_timer_ctr <= (others => '0'); nx_frame_rate <= nx_frame_rate_ctr; adc_frame_rate <= adc_frame_rate_ctr; frame_rate <= frame_rate_ctr; + parity_rate <= parity_rate_ctr; nx_frame_rate_ctr(27 downto 1) <= (others => '0'); nx_frame_rate_ctr(0) <= nx_fifo_data_valid; @@ -1132,6 +1146,9 @@ begin frame_rate_ctr(27 downto 1) <= (others => '0'); frame_rate_ctr(0) <= new_data_o; + + parity_rate_ctr(27 downto 1) <= (others => '0'); + parity_rate_ctr(0) <= parity_error_ctr_inc; end if; end if; end if; @@ -1147,6 +1164,7 @@ begin nx_frame_rate_error <= '0'; adc_frame_rate_error <= '0'; frame_rate_error <= '0'; + parity_rate_error <= '0'; reset_for_offline <= '0'; else if (nx_frame_rate < 2) then @@ -1176,6 +1194,12 @@ begin else frame_rate_error <= '0'; end if; + + if (parity_rate > 0) then + parity_rate_error <= '1'; + else + parity_rate_error <= '0'; + end if; -- Reset Request to Reset Handler nx_frame_rate_offline_last <= nx_frame_rate_offline; @@ -1290,9 +1314,9 @@ begin when x"000a" => slv_data_out_o(31 downto 0) <= (others => '0'); slv_ack_o <= '1'; - + when x"000b" => - slv_data_out_o(0) <= adc_clk_ok; + slv_data_out_o(0) <= reset_handler_busy; slv_data_out_o(31 downto 1) <= (others => '0'); slv_ack_o <= '1'; @@ -1342,6 +1366,11 @@ begin slv_data_out_o(31 downto 8) <= (others => '0'); slv_ack_o <= '1'; + when x"0015" => + slv_data_out_o(27 downto 0) <= parity_rate; + slv_data_out_o(31 downto 28) <= (others => '0'); + slv_ack_o <= '1'; + when x"001e" => slv_data_out_o(1 downto 0) <= debug_adc; slv_data_out_o(31 downto 2) <= (others => '0'); @@ -1437,7 +1466,8 @@ begin adc_clk_ok = '0' or parity_error_ctr_inc = '1' or reg_nx_frame_synced = '0' or - adc_frame_rate_error = '1' + adc_frame_rate_error = '1' or + parity_rate_error = '1' ) then error_o <= '1'; else @@ -1445,15 +1475,14 @@ begin end if; error_status_bits(0) <= nx_frame_rate_offline; - error_status_bits(1) <= nx_frame_rate_error; - error_status_bits(2) <= not reg_nx_frame_synced; - error_status_bits(3) <= parity_error_ctr_inc; - - error_status_bits(4) <= error_adc0; - error_status_bits(5) <= pll_adc_not_lock; - error_status_bits(6) <= not adc_clk_ok; - error_status_bits(7) <= adc_frame_rate_error; - error_status_bits(8) <= frame_rate_error; + error_status_bits(1) <= frame_rate_error; + error_status_bits(2) <= nx_frame_rate_error; + error_status_bits(3) <= adc_frame_rate_error; + error_status_bits(4) <= parity_rate_error; + error_status_bits(5) <= not reg_nx_frame_synced; + error_status_bits(6) <= error_adc0; + error_status_bits(7) <= pll_adc_not_lock; + error_status_bits(8) <= not adc_clk_ok; error_status_bits(9) <= '0'; error_status_bits(10) <= '0'; error_status_bits(11) <= '0'; diff --git a/nxyter/source/nx_data_validate.vhd b/nxyter/source/nx_data_validate.vhd index 3f5d06d..c4a9254 100644 --- a/nxyter/source/nx_data_validate.vhd +++ b/nxyter/source/nx_data_validate.vhd @@ -22,7 +22,8 @@ entity nx_data_validate is TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); ADC_DATA_OUT : out std_logic_vector(11 downto 0); DATA_VALID_OUT : out std_logic; - + SELF_TRIGGER_OUT : out std_logic; + NX_TOKEN_RETURN_OUT : out std_logic; NX_NOMORE_DATA_OUT : out std_logic; @@ -75,6 +76,9 @@ architecture Behavioral of nx_data_validate is signal pileup_rate_inc : std_logic; signal overflow_rate_inc : std_logic; + -- Self Trigger + signal self_trigger_o : std_logic; + -- Rate Calculation signal nx_trigger_ctr_t : unsigned(27 downto 0); signal nx_frame_ctr_t : unsigned(27 downto 0); @@ -113,7 +117,8 @@ begin DEBUG_OUT(2) <= nx_nomore_data_o; DEBUG_OUT(3) <= data_valid_o; DEBUG_OUT(4) <= new_timestamp; - DEBUG_OUT(8 downto 5) <= (others => '0'); + DEBUG_OUT(5) <= self_trigger_o; + DEBUG_OUT(8 downto 6) <= (others => '0'); DEBUG_OUT(15 downto 9) <= channel_o; --DEBUG_OUT(6 downto 4) <= timestamp_status_o; --DEBUG_OUT(7) <= nx_token_return_o; @@ -373,6 +378,20 @@ begin end if; end if; end process PROC_ADC_AVERAGE; + + ----------------------------------------------------------------------------- + -- Self Trigger Out + ----------------------------------------------------------------------------- + pulse_to_level_SELF_TRIGGER: pulse_to_level + generic map ( + NUM_CYCLES => 2 + ) + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + PULSE_IN => data_valid_o, + LEVEL_OUT => self_trigger_o + ); ----------------------------------------------------------------------------- -- TRBNet Slave Bus @@ -499,10 +518,12 @@ begin DATA_VALID_OUT <= data_valid_o; NX_TOKEN_RETURN_OUT <= nx_token_return_o; NX_NOMORE_DATA_OUT <= nx_nomore_data_o; - + SELF_TRIGGER_OUT <= self_trigger_o; + -- Slave SLV_DATA_OUT <= slv_data_out_o; SLV_NO_MORE_DATA_OUT <= slv_no_more_data_o; SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; SLV_ACK_OUT <= slv_ack_o; + end Behavioral; diff --git a/nxyter/source/nx_event_buffer.vhd b/nxyter/source/nx_event_buffer.vhd index 0bd2321..14af877 100644 --- a/nxyter/source/nx_event_buffer.vhd +++ b/nxyter/source/nx_event_buffer.vhd @@ -41,7 +41,9 @@ entity nx_event_buffer is SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; - + + ERROR_OUT : out std_logic; + DEBUG_OUT : out std_logic_vector(15 downto 0) ); @@ -61,31 +63,31 @@ architecture Behavioral of nx_event_buffer is signal STATE : STATES; -- FIFO - signal fifo_reset : std_logic; - signal fifo_read_enable : std_logic; + signal fifo_reset : std_logic; + signal fifo_read_enable : std_logic; -- FIFO Input Handler - signal fifo_next_word : std_logic_vector(31 downto 0); - signal fifo_full : std_logic; - signal fifo_write_enable : std_logic; + signal fifo_next_word : std_logic_vector(31 downto 0); + signal fifo_full : std_logic; + signal fifo_write_enable : std_logic; + signal fifo_almost_full_thr : std_logic_vector(10 downto 0); - -- NOMORE_DATA RS FlipFlop + -- NOMORE_DATA RS FlipFlop signal flush_end_enable_set : std_logic; signal flush_end_enable : std_logic; -- FIFO Read Handler - signal fifo_o : std_logic_vector(31 downto 0); - signal fifo_empty : std_logic; - signal fifo_write_ctr : std_logic_vector(10 downto 0); - signal fifo_read_start : std_logic; - signal fifo_almost_full : std_logic; - - signal fifo_read_enable_s : std_logic; - signal fifo_read_busy : std_logic; - signal fifo_no_data : std_logic; - signal fifo_read_done : std_logic; - signal evt_buffer_full_o : std_logic; - signal fifo_data : std_logic_vector(31 downto 0); + signal fifo_o : std_logic_vector(31 downto 0); + signal fifo_empty : std_logic; + signal fifo_read_start : std_logic; + signal fifo_almost_full : std_logic; + + signal fifo_read_enable_s : std_logic; + signal fifo_read_busy : std_logic; + signal fifo_no_data : std_logic; + signal fifo_read_done : std_logic; + signal evt_buffer_full_o : std_logic; + signal fifo_data : std_logic_vector(31 downto 0); type R_STATES is (R_IDLE, R_NOP1, @@ -102,7 +104,8 @@ architecture Behavioral of nx_event_buffer is signal fifo_read_enable_f : std_logic; signal fifo_read_enable_f2 : std_logic; signal fifo_flush_ctr : unsigned(10 downto 0); - + signal fifo_flush_ctr_last : unsigned(10 downto 0); + signal evt_data_flushed_x : std_logic; signal fifo_flush_ctr_x : unsigned(10 downto 0); signal flush_end_enable_reset_x : std_logic; @@ -114,13 +117,20 @@ architecture Behavioral of nx_event_buffer is signal F_STATE, F_NEXT_STATE : F_STATES; + -- Error Status + signal fifo_almost_full_p : std_logic; + signal error_status_o : std_logic; + signal fifo_full_rate_ctr : unsigned(19 downto 0); + signal fifo_full_rate : unsigned(19 downto 0); + signal rate_timer_ctr : unsigned(27 downto 0); + -- Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; signal slv_unknown_addr_o : std_logic; signal slv_ack_o : std_logic; - signal register_fifo_status : std_logic_vector(31 downto 0); + signal register_fifo_status : std_logic_vector(7 downto 0); signal data_wait : std_logic; @@ -194,18 +204,18 @@ begin -- Send data to FIFO fifo_32_data_1: fifo_32_data port map ( - Data => fifo_next_word, - Clock => CLK_IN, - WrEn => fifo_write_enable, - RdEn => fifo_read_enable, - Reset => fifo_reset, - Q => fifo_o, - WCNT => fifo_write_ctr, - Empty => fifo_empty, - Full => fifo_full, - AlmostFull => fifo_almost_full + Data => fifo_next_word, + Clock => CLK_IN, + WrEn => fifo_write_enable, + RdEn => fifo_read_enable, + Reset => fifo_reset, + AmFullThresh => fifo_almost_full_thr, + Q => fifo_o, + Empty => fifo_empty, + Full => fifo_full, + AlmostFull => fifo_almost_full ); - + fifo_reset <= RESET_IN or RESET_DATA_BUFFER_IN; fifo_read_enable <= fifo_read_enable_f or fifo_read_enable_s; @@ -218,7 +228,9 @@ begin fifo_write_enable <= '0'; fifo_next_word <= x"deadbeef"; - if (DATA_CLK_IN = '1' and fifo_full = '0') then + if (DATA_CLK_IN = '1' and + fifo_full = '0' and + fifo_almost_full = '0') then fifo_next_word <= DATA_IN; fifo_write_enable <= '1'; end if; @@ -245,19 +257,22 @@ begin PROC_FLUSH_BUFFER_TRANSFER: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then + fifo_read_enable_f2 <= fifo_read_enable_f; if( RESET_IN = '1' ) then evt_data_clk <= '0'; evt_data_flushed <= '0'; fifo_flush_ctr <= (others => '0'); - fifo_read_enable_f2 <= '0'; + fifo_flush_ctr_last <= (others => '0'); F_STATE <= F_IDLE; else evt_data_flushed <= evt_data_flushed_x; fifo_flush_ctr <= fifo_flush_ctr_x; F_STATE <= F_NEXT_STATE; - - fifo_read_enable_f2 <= fifo_read_enable_f; evt_data_clk <= fifo_read_enable_f2; + + if (F_STATE = F_END) then + fifo_flush_ctr_last <= fifo_flush_ctr_x; + end if; end if; end if; end process PROC_FLUSH_BUFFER_TRANSFER; @@ -371,6 +386,50 @@ begin end if; end process PROC_FIFO_READ_WORD; + + ----------------------------------------------------------------------------- + -- Rate Counters + Rate Error Check + ----------------------------------------------------------------------------- + level_to_pulse_FIFO_FULL: level_to_pulse + port map ( + CLK_IN => CLK_IN, + RESET_IN => RESET_IN, + LEVEL_IN => fifo_almost_full, + PULSE_OUT => fifo_almost_full_p + ); + + + PROC_RATE_COUNTER: process(CLK_IN) + begin + if (rising_edge(CLK_IN) ) then + if (RESET_IN = '1') then + fifo_full_rate_ctr <= (others => '0'); + fifo_full_rate <= (others => '0'); + rate_timer_ctr <= (others => '0'); + error_status_o <= '0'; + else + if (rate_timer_ctr < x"5f5e100") then + rate_timer_ctr <= rate_timer_ctr + 1; + + if (fifo_almost_full_p = '1') then + fifo_full_rate_ctr <= fifo_full_rate_ctr + 1; + end if; + else + rate_timer_ctr <= (others => '0'); + fifo_full_rate <= fifo_full_rate_ctr; + + fifo_full_rate_ctr(19 downto 1) <= (others => '0'); + fifo_full_rate_ctr(0) <= fifo_almost_full_p; + + if (fifo_full_rate > 0) then + error_status_o <= '1'; + else + error_status_o <= '0'; + end if; + end if; + end if; + end if; + end process PROC_RATE_COUNTER; ----------------------------------------------------------------------------- -- Slave Bus Slow Control @@ -382,7 +441,6 @@ begin register_fifo_status(4) <= fifo_read_enable; register_fifo_status(5) <= fifo_empty; register_fifo_status(7 downto 6) <= (others => '0'); - register_fifo_status(31 downto 8) <= (others => '0'); PROC_SLAVE_BUS: process(CLK_IN) begin @@ -395,6 +453,7 @@ begin fifo_read_start <= '0'; data_wait <= '0'; + fifo_almost_full_thr <= "00101011110"; -- default: 350 = 1.4k else slv_data_out_o <= (others => '0'); slv_ack_o <= '0'; @@ -421,32 +480,50 @@ begin elsif (SLV_READ_IN = '1') then case SLV_ADDR_IN is when x"0000" => - fifo_read_start <= '1'; - data_wait <= '1'; + fifo_read_start <= '1'; + data_wait <= '1'; when x"0001" => - slv_data_out_o(10 downto 0) <= fifo_write_ctr; - slv_data_out_o(31 downto 11) <= (others => '0'); - slv_ack_o <= '1'; + slv_data_out_o(10 downto 0) <= fifo_almost_full_thr; + slv_data_out_o(31 downto 11) <= (others => '0'); + slv_ack_o <= '1'; when x"0002" => - slv_data_out_o(10 downto 0) <= std_logic_vector(fifo_flush_ctr); - slv_data_out_o(31 downto 11) <= (others => '0'); - slv_ack_o <= '1'; - + slv_data_out_o(10 downto 0) <= + std_logic_vector(fifo_flush_ctr_last); + slv_data_out_o(31 downto 11) <= (others => '0'); + slv_ack_o <= '1'; + when x"0003" => - slv_data_out_o <= register_fifo_status; - slv_ack_o <= '1'; + slv_data_out_o(19 downto 0) <= fifo_full_rate; + slv_data_out_o(31 downto 20) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0004" => + slv_data_out_o(0) <= error_status_o; + slv_data_out_o(31 downto 1) <= (others => '0'); + slv_ack_o <= '1'; + + when x"0005" => + slv_data_out_o(7 downto 0) <= register_fifo_status; + slv_data_out_o(31 downto 8) <= (others => '0'); + slv_ack_o <= '1'; when others => - slv_unknown_addr_o <= '1'; + slv_unknown_addr_o <= '1'; end case; - + elsif (SLV_WRITE_IN = '1') then case SLV_ADDR_IN is + when x"0001" => + if (unsigned(slv_data_out_o(10 downto 0)) < 2040) then + fifo_almost_full_thr <= SLV_DATA_IN(10 downto 0); + end if; + slv_ack_o <= '1'; + when others => - slv_unknown_addr_o <= '1'; - slv_ack_o <= '0'; + slv_unknown_addr_o <= '1'; + slv_ack_o <= '0'; end case; else @@ -472,4 +549,6 @@ begin SLV_UNKNOWN_ADDR_OUT <= slv_unknown_addr_o; SLV_ACK_OUT <= slv_ack_o; + ERROR_OUT <= error_status_o; + end Behavioral; diff --git a/nxyter/source/nx_trigger_generator.vhd b/nxyter/source/nx_trigger_generator.vhd index 99c8800..a71a326 100644 --- a/nxyter/source/nx_trigger_generator.vhd +++ b/nxyter/source/nx_trigger_generator.vhd @@ -55,9 +55,6 @@ architecture Behavioral of nx_trigger_generator is signal testpulse_rate_t : unsigned(27 downto 0); signal rate_timer : unsigned(27 downto 0); - -- Reg Sync - signal testpulse_length : unsigned(11 downto 0); - -- TRBNet Slave Bus signal slv_data_out_o : std_logic_vector(31 downto 0); signal slv_no_more_data_o : std_logic; @@ -127,7 +124,7 @@ begin TIMER_END_IN => wait_timer_init, TIMER_DONE_OUT => wait_timer_done ); - wait_timer_init <= testpulse_length - 1; + wait_timer_init <= reg_testpulse_length - 1; ----------------------------------------------------------------------------- -- Generate Trigger @@ -158,7 +155,7 @@ begin extern_trigger <= '1'; testpulse_o <= '1'; testpulse_p <= '1'; - if (testpulse_length > 0) then + if (reg_testpulse_length > 0) then wait_timer_start <= '1'; STATE <= S_WAIT_TESTPULSE_END; else @@ -221,22 +218,6 @@ begin end if; end process PROC_CAL_RATES; - ----------------------------------------------------------------------------- - -- Register Transfer - ----------------------------------------------------------------------------- - - bus_async_trans_TESTPULSE_LENGTH : bus_async_trans - generic map ( - BUS_WIDTH => 12, - NUM_FF => 2 - ) - port map ( - CLK_IN => NX_MAIN_CLK_IN, - RESET_IN => RESET_NX_MAIN_CLK_IN, - SIGNAL_A_IN => std_logic_vector(reg_testpulse_length), - unsigned(SIGNAL_OUT) => testpulse_length - ); - ----------------------------------------------------------------------------- -- TRBNet Slave Bus ----------------------------------------------------------------------------- diff --git a/nxyter/source/nx_trigger_validate.vhd b/nxyter/source/nx_trigger_validate.vhd index 6f1597d..d9f8d5a 100644 --- a/nxyter/source/nx_trigger_validate.vhd +++ b/nxyter/source/nx_trigger_validate.vhd @@ -42,7 +42,7 @@ entity nx_trigger_validate is HISTOGRAM_ADC_OUT : out std_logic_vector(11 downto 0); HISTOGRAM_PILEUP_OUT : out std_logic; HISTOGRAM_OVERFLOW_OUT : out std_logic; - + -- Slave bus SLV_READ_IN : in std_logic; SLV_WRITE_IN : in std_logic; @@ -355,7 +355,8 @@ begin end if; --TS Window Disabled, always store data - if (readout_mode(2) = '1') then + if (readout_mode(2) = '1' or + self_trigger_mode = '1') then store_data := '1'; end if; diff --git a/nxyter/source/nxyter_components.vhd b/nxyter/source/nxyter_components.vhd index 3ba0784..4ca27cf 100644 --- a/nxyter/source/nxyter_components.vhd +++ b/nxyter/source/nxyter_components.vhd @@ -419,16 +419,16 @@ end component; component fifo_32_data port ( - Data : in std_logic_vector(31 downto 0); - Clock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(31 downto 0); - WCNT : out std_logic_vector(10 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic + Data : in std_logic_vector(31 downto 0); + Clock : in std_logic; + WrEn : in std_logic; + RdEn : in std_logic; + Reset : in std_logic; + AmFullThresh : in std_logic_vector(10 downto 0); + Q : out std_logic_vector(31 downto 0); + Empty : out std_logic; + Full : out std_logic; + AlmostFull : out std_logic ); end component; @@ -501,6 +501,7 @@ component nx_data_validate TIMESTAMP_STATUS_OUT : out std_logic_vector(2 downto 0); ADC_DATA_OUT : out std_logic_vector(11 downto 0); DATA_VALID_OUT : out std_logic; + SELF_TRIGGER_OUT : out std_logic; NX_TOKEN_RETURN_OUT : out std_logic; NX_NOMORE_DATA_OUT : out std_logic; SLV_READ_IN : in std_logic; @@ -584,6 +585,7 @@ component nx_event_buffer SLV_ACK_OUT : out std_logic; SLV_NO_MORE_DATA_OUT : out std_logic; SLV_UNKNOWN_ADDR_OUT : out std_logic; + ERROR_OUT : out std_logic; DEBUG_OUT : out std_logic_vector(15 downto 0) ); end component; diff --git a/nxyter/source/nxyter_fee_board.vhd b/nxyter/source/nxyter_fee_board.vhd index 1e10028..bbfb86e 100644 --- a/nxyter/source/nxyter_fee_board.vhd +++ b/nxyter/source/nxyter_fee_board.vhd @@ -139,7 +139,7 @@ architecture Behavioral of nXyter_FEE_board is -- Data Receiver signal adc_data_valid : std_logic; signal adc_new_data : std_logic; - + signal self_trigger : std_logic; signal new_timestamp : std_logic_vector(31 downto 0); signal new_adc_data : std_logic_vector(11 downto 0); signal new_data : std_logic; @@ -219,6 +219,7 @@ architecture Behavioral of nXyter_FEE_board is -- Error signal error_all : std_logic_vector(7 downto 0); signal error_data_receiver : std_logic; + signal error_event_buffer : std_logic; -- Debug Handler constant DEBUG_NUM_PORTS : integer := 14; @@ -237,7 +238,8 @@ begin -- Errors ------------------------------------------------------------------------------- error_all(0) <= error_data_receiver; - error_all(7 downto 1) <= (others => '0'); + error_all(1) <= error_event_buffer; + error_all(7 downto 2) <= (others => '0'); ------------------------------------------------------------------------------- -- Port Maps @@ -634,6 +636,7 @@ begin TIMESTAMP_STATUS_OUT => timestamp_status, ADC_DATA_OUT => adc_data, DATA_VALID_OUT => data_valid, + SELF_TRIGGER_OUT => self_trigger, NX_TOKEN_RETURN_OUT => nx_token_return, NX_NOMORE_DATA_OUT => nx_nomore_data, @@ -697,7 +700,7 @@ begin SLV_ACK_OUT => slv_ack(8), SLV_NO_MORE_DATA_OUT => slv_no_more_data(8), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(8), - + DEBUG_OUT => debug_line(10) ); @@ -737,7 +740,8 @@ begin SLV_NO_MORE_DATA_OUT => slv_no_more_data(3), SLV_UNKNOWN_ADDR_OUT => slv_unknown_addr(3), - DEBUG_OUT => debug_line(11) + ERROR_OUT => error_event_buffer, + DEBUG_OUT => debug_line(11) ); nx_status_event_1: nx_status_event @@ -803,7 +807,8 @@ begin -- Others ------------------------------------------------------------------------------- NX_TIMESTAMP_TRIGGER_OUT <= nx_timestamp_trigger_o; - + TRIGGER_OUT <= self_trigger; + ------------------------------------------------------------------------------- -- DEBUG Line Select ------------------------------------------------------------------------------- diff --git a/nxyter/source/pulse_to_level.vhd b/nxyter/source/pulse_to_level.vhd index c7362aa..eb8f147 100644 --- a/nxyter/source/pulse_to_level.vhd +++ b/nxyter/source/pulse_to_level.vhd @@ -38,7 +38,7 @@ begin timer_static_1: timer_static generic map ( CTR_WIDTH => 5, - CTR_END => (NUM_CYCLES - 1) + CTR_END => NUM_CYCLES ) port map ( CLK_IN => CLK_IN, @@ -47,7 +47,7 @@ begin TIMER_DONE_OUT => timer_done ); - PROC_CONVERT_TRANSFER: process(CLK_IN) + PROC_LEVEL_OUT_TRANSFER: process(CLK_IN) begin if( rising_edge(CLK_IN) ) then if( RESET_IN = '1' ) then @@ -58,15 +58,12 @@ begin STATE <= NEXT_STATE; end if; end if; - end process PROC_CONVERT_TRANSFER; + end process PROC_LEVEL_OUT_TRANSFER; - PROC_CONVERT: process(STATE, - PULSE_IN, - timer_done - ) - constant TIMER_VALUE : - unsigned(4 downto 0) := to_unsigned(NUM_CYCLES - 1, 5); - + PROC_LEVEL_OUT: process(STATE, + PULSE_IN, + timer_done + ) begin case STATE is @@ -92,7 +89,7 @@ begin end if; end case; - end process PROC_CONVERT; + end process PROC_LEVEL_OUT; -- Output Signals LEVEL_OUT <= level_o; diff --git a/nxyter/source/registers.txt b/nxyter/source/registers.txt index 3233def..377dfc3 100644 --- a/nxyter/source/registers.txt +++ b/nxyter/source/registers.txt @@ -153,8 +153,8 @@ -- Event Data Buffer 0x8600 : r read FIFO buffer -0x8601 : r FIFO write counter -0x8602 : r FIFO flush counter +0x8601 : rw Fifo Depth in words (10...4000, default 350) +0x8602 : r FIFO flush counter last 0x8603 : r read FIFO status --- DEBUG ------------------------------------------------------------ diff --git a/nxyter/source/timer.vhd b/nxyter/source/timer.vhd index e2d6bd2..fb2d827 100644 --- a/nxyter/source/timer.vhd +++ b/nxyter/source/timer.vhd @@ -57,7 +57,7 @@ begin case STATE is when S_IDLE => timer_done_o <= '0'; - if (TIMER_START_IN = '1') then + if (TIMER_START_IN = '1' and TIMER_END_IN > 0) then timer_ctr_x <= TIMER_END_IN - 1; NEXT_STATE <= S_COUNT; else diff --git a/nxyter/source/timer_static.vhd b/nxyter/source/timer_static.vhd index 78121f9..f899cf7 100644 --- a/nxyter/source/timer_static.vhd +++ b/nxyter/source/timer_static.vhd @@ -4,9 +4,9 @@ use ieee.numeric_std.all; entity timer_static is generic ( - CTR_WIDTH : integer range 2 to 32 := 12; - CTR_END : integer := 10; - STEP_SIZE : integer range 1 to 100 := 1 + CTR_WIDTH : integer range 2 to 32 := 12; + CTR_END : integer range 2 to 4000 := 10; + STEP_SIZE : integer range 1 to 100 := 1 ); port( CLK_IN : in std_logic; diff --git a/nxyter/trb3_periph_constraints.lpf b/nxyter/trb3_periph_constraints.lpf index 0ed2219..6d5bdba 100644 --- a/nxyter/trb3_periph_constraints.lpf +++ b/nxyter/trb3_periph_constraints.lpf @@ -61,7 +61,7 @@ LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLI ################################################################# MULTICYCLE FROM CELL "THE_RESET_HANDLER/final_reset*" 30 ns; -MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset_p*" 30 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/adc_reset*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_data_receiver_*/signal_async_trans_RESET_IN/*" 30 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_fpga_timestamp_*/signal_async_trans_RESET_IN/*" 30 ns; @@ -79,6 +79,7 @@ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_offset_ MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/ts_window_width_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/readout_time_max_*" 100 ns; MULTICYCLE FROM CELL "nXyter_FEE_board_*/nx_trigger_validate_*/fpga_timestamp_offset_*" 100 ns; +MULTICYCLE FROM CELL "nXyter_FEE_board_*.nx_event_buffer_*.fifo_almost_full_thr" 100 ns; BLOCK NET "nXyter_FEE_board_*/nx_data_receiver_*/adc_ad9228_*/fifo_adc_48to48_dc_*/r_gcount*"; diff --git a/nxyter/trb3_periph_nx1.vhd b/nxyter/trb3_periph_nx1.vhd index c2449e7..d834f28 100644 --- a/nxyter/trb3_periph_nx1.vhd +++ b/nxyter/trb3_periph_nx1.vhd @@ -68,8 +68,6 @@ entity trb3_periph is NX1B_ADC_NX_IN : in std_logic; NX1B_ADC_D_IN : in std_logic; - ADDON_TRIGGER_OUT : out std_logic; - --------------------------------------------------------------------------- -- END AddonBoard nXyter --------------------------------------------------------------------------- @@ -702,7 +700,7 @@ begin --DEBUG_LINE_OUT => open ); - ADDON_TRIGGER_OUT <= fee1_trigger; + FPGA5_COMM(10) <= fee1_trigger; ----------------------------------------------------------------------------- -- nXyter Main and ADC Clocks diff --git a/nxyter/trb3_periph_nxyter.lpf b/nxyter/trb3_periph_nxyter.lpf index dbb0dbd..01d67a5 100644 --- a/nxyter/trb3_periph_nxyter.lpf +++ b/nxyter/trb3_periph_nxyter.lpf @@ -169,7 +169,6 @@ IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4; #LOCATE COMP "NX2_TESTPULSE_OUT" SITE "AA24"; #DQLR1_6 #185 #LOCATE COMP "NX2_DATA_CLK_IN" SITE "M23"; #DQSUR1_T #118 ##LOCATE COMP "NX2_DATA_CLK_IN" SITE "N23"; #DQUR2_2 #134 -#LOCATE COMP "ADDON_TRIGGER_OUT" SITE "N23"; #DQUR2_2 #134 # #LOCATE COMP "NX2_I2C_SCL_INOUT" SITE "R25"; #DQLR2_0 #170 #LOCATE COMP "NX2_I2C_SDA_INOUT" SITE "R26"; #DQLR2_1 #172 @@ -219,7 +218,6 @@ IOBUF PORT "NX1_SPI_CSB_OUT" IO_TYPE=LVCMOS25 PULLMODE=UP DRIVE=4; #IOBUF PORT "NX2_ADC_FCLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; #IOBUF PORT "NX2_ADC_SAMPLE_CLK_OUT" IO_TYPE=LVDS25; # -#IOBUF PORT "ADDON_TRIGGER_OUT" IO_TYPE=LVDS25; #IOBUF PORT "NX2_DATA_CLK_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; #IOBUF PORT "NX2_TESTPULSE_OUT" IO_TYPE=LVDS25; #IOBUF PORT "NX2_MAIN_CLK_OUT" IO_TYPE=LVDS25; -- 2.43.0