From 539d96245e628e4c480e681e812bad43251291d5 Mon Sep 17 00:00:00 2001 From: palka Date: Fri, 18 Jan 2008 10:20:43 +0000 Subject: [PATCH] new protocol between vulom and cts --- trb_cts/vulom_interface.vhd | 167 +++++++++++++++++++++++++++++++++--- 1 file changed, 154 insertions(+), 13 deletions(-) diff --git a/trb_cts/vulom_interface.vhd b/trb_cts/vulom_interface.vhd index 0b131ba..631da14 100644 --- a/trb_cts/vulom_interface.vhd +++ b/trb_cts/vulom_interface.vhd @@ -15,6 +15,8 @@ entity vulom_interface is RESET : in std_logic; DATA_IN : in std_logic_vector(1 downto 0); BUSY : out std_logic; + ACK_TO_VULOM : out std_logic; + ERR_TO_VULOM : out std_logic; API_DATA : out std_logic_vector(47 downto 0); API_RUN_OUT : in std_logic; API_SHORT_TRANSFER : out std_logic; @@ -55,6 +57,8 @@ architecture vulom_interface of vulom_interface is type VULOM_TO_API is (IDLE, SEND_TRIGGER_a,SEND_TRIGGER_b,SEND_TRIGGER_c, WAIT_FOR_END_BUSY,TRIGGER_MISSMATCH); signal VULOM_TO_API_current,VULOM_TO_API_next : VULOM_TO_API; + type CHECK_TRANSMITION is (IDLE, CHECK_1, CHECK_2, CHECK_3 , WAIT_FOR_END, CHECK_SUM, SEND_ERROR, SEND_ACK_1, SEND_ACK_2 ); + signal CHECK_current, CHECK_next : CHECK_TRANSMITION; signal trigger_code : std_logic_vector(3 downto 0); signal trigger_tag : std_logic_vector(15 downto 0); signal api_ready_pulse : std_logic; @@ -72,6 +76,12 @@ architecture vulom_interface of vulom_interface is signal data_clock_counter : std_logic_vector(7 downto 0):=x"00"; signal not_transfer_busy : std_logic; signal not_transfer_busy_pulse : std_logic; + signal err : std_logic; + signal ack : std_logic; + signal seq_ok : std_logic; + signal err_counter : std_logic_vector(3 downto 0); + signal ack_counter : std_logic_vector(3 downto 0); + signal check_sum_ok : std_logic; begin trigger_code <= "00" & v_data(0); trigger_tag <= v_data(8) & v_data(7) & v_data(6) & v_data(5) & v_data(4) & v_data(3) & v_data(2) & v_data(1); @@ -81,18 +91,148 @@ begin API_TARGET_ADDRESS <= x"FFFF"; API_SHORT_TRANSFER <= '1'; not_api_run_out <= not API_RUN_OUT; - SAVE_VULOM_DATA: process (DATA_CLK) - variable vulom_data_array_counter : integer:=1; + check_sum_ok <= '1'; --for crc + + CHECK_BEG_SEQUENCE : process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' then + CHECK_current <= IDLE; + else + CHECK_current <= CHECK_next; + end if; + end if; + end process CHECK_BEG_SEQUENCE; + CHECK_BEG_SEQUENCE_FSM: process (CLK, DATA_CLK, DATA_IN, check_sum_ok,fast_trigg ,trigger_pulse,trigger_counter,trigger_tag, api_ready_pulse) + begin + case (CHECK_current) is + when IDLE => + seq_ok <= '0'; + ack <= '0'; + err <= '0'; + if rising_edge(DATA_CLK) then + if DATA_IN(0)='1' and DATA_IN(1)='0' then + CHECK_next <= CHECK_1; + else + CHECK_next <= IDLE; + end if; + end if; + when CHECK_1 => + seq_ok <= '0'; + ack <= '0'; + err <= '0'; + if rising_edge(DATA_CLK) then + if DATA_IN(0)='0' and DATA_IN(1)='1' then + CHECK_next <= CHECK_2; + else + CHECK_next <= IDLE; + end if; + end if; + when CHECK_2 => + seq_ok <= '0'; + ack <= '0'; + err <= '0'; + if rising_edge(DATA_CLK) then + if DATA_IN(0)='1' and DATA_IN(1)='0' then + CHECK_next <= CHECK_3; + else + CHECK_next <= IDLE; + end if; + end if; + when CHECK_3 => + seq_ok <= '0'; + ack <= '0'; + err <= '0'; + if rising_edge(DATA_CLK) then + if DATA_IN(0)='0' and DATA_IN(1)='1' then + CHECK_next <= WAIT_FOR_END; + else + CHECK_next <= IDLE; + end if; + end if; + when WAIT_FOR_END => + seq_ok <= '1'; + ack <= '0'; + if data_clock_counter = 161 then + CHECK_next <= CHECK_SUM; + end if; + when CHECK_SUM => + seq_ok <= '0'; + ack <= '0'; + err <= '0'; + if check_sum_ok = '0' then + CHECK_next <= SEND_ERROR; + else + CHECK_next <= SEND_ACK_1; + end if; + when SEND_ACK_1 => + seq_ok <= '0'; + ack <= '0'; + err <= '0'; + if not_transfer_busy_pulse = '1' then + CHECK_next <= SEND_ACK_2; + else + CHECK_next <= SEND_ACK_1; + end if; + when SEND_ACK_2 => + seq_ok <= '0'; + ack <= '1'; + err <= '0'; + if ack_counter = 15 then + CHECK_next <= IDLE; + else + CHECK_next <= SEND_ACK_2; + end if; + when SEND_ERROR => + seq_ok <= '0'; + ack <= '0'; + err <= '1'; + if err_counter = x"f" then + CHECK_next <= IDLE; + else + CHECK_next <= SEND_ERROR; + end if; + when others => + CHECK_next <= IDLE; + end case; + end process CHECK_BEG_SEQUENCE_FSM; + ACK_TO_VULOM <= ack; + ERR_TO_VULOM <= err; + ERR_COUNTER_CLK: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or CHECK_current = IDLE then + err_counter <= x"0"; + elsif CHECK_current = SEND_ERROR then + err_counter <= err_counter + 1; + else + err_counter <= err_counter; + end if; + end if; + end process ERR_COUNTER_CLK; + ACK_COUNTER_CLK: process (CLK, RESET) + begin + if rising_edge(CLK) then + if RESET = '1' or CHECK_current = IDLE then + ack_counter <= x"0"; + elsif CHECK_current = SEND_ACK_2 then + ack_counter <= ack_counter + 1; + else + ack_counter <= ack_counter; + end if; + end if; + end process ACK_COUNTER_CLK; + SAVE_VULOM_DATA: process (DATA_CLK, seq_ok) + variable vulom_data_array_counter : integer:=0; begin if rising_edge (DATA_CLK) then - if vulom_data_array_counter = 161 then - vulom_data_array_counter := 1; + vulom_data_array_counter := 0; data_clock_counter <= (others => '0'); - else - vulom_data_array_counter := vulom_data_array_counter + 1; - v_data(vulom_data_array_counter-1) <= DATA_IN(1 downto 0); - data_clock_counter <= data_clock_counter + 1; + elsif seq_ok = '1' then + vulom_data_array_counter := vulom_data_array_counter + 1; + v_data(vulom_data_array_counter-1) <= DATA_IN(1 downto 0); + data_clock_counter <= data_clock_counter + 1; end if; end if; end process SAVE_VULOM_DATA; @@ -129,13 +269,13 @@ begin en_clk => '1', signal_in => not_api_run_out, pulse => api_ready_pulse); + data_trigg <= '1' when CHECK_current = SEND_ACK_1 else '0'; --160 FAST_TRIGG_PULSER : edge_to_pulse port map ( clock => CLK, en_clk => '1', signal_in => data_trigg, pulse => data_trigg_pulse); - data_trigg <= '1' when data_clock_counter = 160 else '0'; --160 SYNCH_START: process (CLK, RESET) begin if rising_edge(CLK) then @@ -201,7 +341,7 @@ begin --api -- if API_SEQNR_OUT /= trigger_tag then --cts only -if trigger_counter /= trigger_tag then + if trigger_counter /= trigger_tag then VULOM_TO_API_next <= TRIGGER_MISSMATCH; else VULOM_TO_API_next <= WAIT_FOR_END_BUSY; @@ -211,9 +351,9 @@ if trigger_counter /= trigger_tag then busy_i <= '1'; API_SEND <= '0'; --api -if api_ready_pulse = '1' then +-- if api_ready_pulse = '1' then --just cts --- if not_transfer_busy_pulse = '1' then + if not_transfer_busy_pulse = '1' then VULOM_TO_API_next <= IDLE; else VULOM_TO_API_next <= WAIT_FOR_END_BUSY; @@ -235,7 +375,8 @@ if api_ready_pulse = '1' then end case; end process VULOM_TO_API_FSM; - BUSY <=(busy_i or LVL1_TRANSFER_BUSY); +-- BUSY <=(busy_i or LVL1_TRANSFER_BUSY); + BUSY <= ack; VULOM_INT_REG(3 downto 0) <= vulom_interface_debug; VULOM_INT_REG(7 downto 4) <= trigger_code; VULOM_INT_REG(15 downto 8) <= trigger_tag(7 downto 0); -- 2.43.0