From 53fb5707e0f51502a26f17e7884846a98a4306a0 Mon Sep 17 00:00:00 2001 From: hadeshyp Date: Fri, 15 Mar 2013 16:06:11 +0000 Subject: [PATCH] added config for CTS, JM --- cts/compile_central_frankfurt.pl | 7 +- cts/config.vhd | 103 ++++++++++++++ cts/cts.fdc | 46 ++++++ cts/project2/cts.ldf | 11 +- cts/source/cts_pkg.vhd | 27 ++++ cts/trb3_central.p2t | 4 +- cts/trb3_central.prj | 12 +- cts/trb3_central.vhd | 234 +++++++++++++++++-------------- cts/trb3_central_constraints.lpf | 103 +++++++++++--- 9 files changed, 413 insertions(+), 134 deletions(-) create mode 100644 cts/config.vhd create mode 100644 cts/cts.fdc diff --git a/cts/compile_central_frankfurt.pl b/cts/compile_central_frankfurt.pl index 2b63979..e44a691 100755 --- a/cts/compile_central_frankfurt.pl +++ b/cts/compile_central_frankfurt.pl @@ -12,6 +12,7 @@ my $TOPNAME = "trb3_central"; #Name of top-level entity my $lattice_path = '/d/jspc29/lattice/diamond/2.01'; #my $lattice_path = '/d/jspc29/lattice/diamond/2.0'; #my $lattice_path = '/d/jspc29/lattice/diamond/1.4.2.105'; +#my $synplify_path = '/d/jspc29/lattice/synplify/G-2012.09-SP1/'; my $synplify_path = '/d/jspc29/lattice/synplify/F-2012.03-SP1/'; my $lm_license_file_for_synplify = "27000\@lxcad01.gsi.de"; my $lm_license_file_for_par = "1702\@hadeb05.gsi.de"; @@ -43,7 +44,9 @@ my $SPEEDGRADE="8"; system("cp ../base/$TOPNAME.lpf workdir/$TOPNAME.lpf"); system("cat ../tdc_releases/tdc_v1.1.1/tdc_constraints.lpf >> workdir/$TOPNAME.lpf"); system("cat ".$TOPNAME."_constraints.lpf >> workdir/$TOPNAME.lpf"); +system("sed -i 's#THE_TDC/#gen_TDC_THE_TDC/#g' workdir/$TOPNAME.lpf"); +if($ENV{'LPF_ONLY'} == 1) {exit;} #set -e #set -o errexit @@ -117,11 +120,13 @@ execute($c); $c=qq|multipar -pr "$TOPNAME.prf" -o "mpar_$TOPNAME.rpt" -log "mpar_$TOPNAME.log" -p "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd"|; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.ncd" "$TOPNAME.prf"|; +#$c=qq|$lattice_path/ispfpga/bin/lin/par -f "../$TOPNAME.p2t" "$tpmap.ncd" "$TOPNAME.dir" "$TOPNAME.prf"|; execute($c); # IOR IO Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/iotiming -s "$TOPNAME.ncd" "$TOPNAME.prf"|; -execute($c); +#execute($c); # TWR Timing Report $c=qq|$lattice_path/ispfpga/bin/lin/trce -c -v 15 -o "$TOPNAME.twr.setup" "$TOPNAME.ncd" "$TOPNAME.prf"|; diff --git a/cts/config.vhd b/cts/config.vhd new file mode 100644 index 0000000..9bb800a --- /dev/null +++ b/cts/config.vhd @@ -0,0 +1,103 @@ +library ieee; +USE IEEE.std_logic_1164.ALL; +use ieee.numeric_std.all; +use work.trb_net_std.all; + +package config is + + +------------------------------------------------------------------------------ +--Begin of configuration +------------------------------------------------------------------------------ + +--include TDC for all four trigger input lines + constant INCLUDE_TDC : integer range c_NO to c_YES := c_NO; + +--use all four SFP (1-4) as downlink to other boards. + constant USE_4_SFP : integer range c_NO to c_YES := c_NO; + + +--Run wih 125 MHz instead of 100 MHz + constant USE_125_MHZ : integer range c_NO to c_YES := c_YES; + +------------------------------------------------------------------------------ +--End of configuration +------------------------------------------------------------------------------ + + + + + + + +------------------------------------------------------------------------------ +--Hub configuration +------------------------------------------------------------------------------ + type hub_mii_t is array(0 to 1) of integer; + type hub_ct is array(0 to 16) of integer; + type hub_cfg_t is array(0 to 1) of hub_ct; + + --this is used to select the proper configuration in the main code + constant CFG_MODE : integer; + + + --first entry is normal CTS with one optical output, second one is with four optical outputs + --slow-control is accepted on SFP1 only, triggers are sent to all used SFP + constant INTERNAL_NUM_ARR : hub_mii_t := (5,5); + constant INTERFACE_NUM_ARR : hub_mii_t := (5,8); + constant IS_UPLINK_ARR : hub_cfg_t := ((0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0)); + constant IS_DOWNLINK_ARR : hub_cfg_t := ((1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), + (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0)); + constant IS_UPLINK_ONLY_ARR : hub_cfg_t := ((0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), + (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0)); + + + constant INTERNAL_NUM : integer; + constant INTERFACE_NUM : integer; + constant IS_UPLINK : hub_ct; + constant IS_DOWNLINK : hub_ct; + constant IS_UPLINK_ONLY : hub_ct; + + + -- MII_NUMBER => 5, --(8) + -- INT_NUMBER => 5, + -- INT_CHANNELS => (0,1,0,1,3), + + -- No trigger / sctrl sent to optical link, slow control receiving possible + -- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); + + -- Trigger / sctrl sent to optical link, slow control receiving possible + -- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0); + -- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0); + -- & disable port 4 in c0 and c1 -- no triggers from/to optical link + + -- Trigger / sctrl sent to 4 optical links + -- MII_IS_UPLINK => (0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0,0); + -- MII_IS_DOWNLINK => (1,1,1,1,1,1,1,1,1,1,0,0,0,0,0,0,0); + -- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0); + -- & disable port 4 in c0 and c1 -- no triggers from/to optical link + +------------------------------------------------------------------------------ +--CTS configuration +------------------------------------------------------------------------------ + constant cts_rdo_additional_ports : integer; + +end; + +package body config is +--compute correct configuration mode + constant CFG_MODE : integer := USE_4_SFP; + constant cts_rdo_additional_ports : integer := 1 + INCLUDE_TDC; + + constant INTERNAL_NUM : integer := INTERNAL_NUM_ARR(CFG_MODE); + constant INTERFACE_NUM : integer := INTERFACE_NUM_ARR(CFG_MODE); + constant IS_UPLINK : hub_ct := IS_UPLINK_ARR(CFG_MODE); + constant IS_DOWNLINK : hub_ct := IS_DOWNLINK_ARR(CFG_MODE); + constant IS_UPLINK_ONLY : hub_ct := IS_UPLINK_ONLY_ARR(CFG_MODE); + + +end package body; \ No newline at end of file diff --git a/cts/cts.fdc b/cts/cts.fdc new file mode 100644 index 0000000..3a276a1 --- /dev/null +++ b/cts/cts.fdc @@ -0,0 +1,46 @@ + +###==== BEGIN Header + +# Synopsys, Inc. constraint file +# /local/trb/cvs/trb3/cts/cts.fdc +# Written on Mon Feb 25 14:14:25 2013 +# by Synplify Pro, G-2012.09-SP1 FDC Constraint Editor + +# Custom constraint commands may be added outside of the SCOPE tab sections bounded with BEGIN/END. +# These sections are generated from SCOPE spreadsheet tabs. + +###==== END Header + +###==== BEGIN Collections - (Populated from tab in SCOPE, do not edit) +###==== END Collections + +###==== BEGIN Clocks - (Populated from tab in SCOPE, do not edit) + +###==== END Clocks + +###==== BEGIN "Generated Clocks" - (Populated from tab in SCOPE, do not edit) +###==== END "Generated Clocks" + +###==== BEGIN Inputs/Outputs - (Populated from tab in SCOPE, do not edit) +###==== END Inputs/Outputs + +###==== BEGIN "Delay Paths" - (Populated from tab in SCOPE, do not edit) +###==== END "Delay Paths" + +###==== BEGIN Attributes - (Populated from tab in SCOPE, do not edit) +###==== END Attributes + +###==== BEGIN "I/O Standards" - (Populated from tab in SCOPE, do not edit) +###==== END "I/O Standards" + +###==== BEGIN "Compile Points" - (Populated from tab in SCOPE, do not edit) +define_compile_point {v:work.trb_net16_med_ecp3_sfp_work_trb3_central_trb3_central_arch_11layer0} -type {locked,partition} +define_compile_point {v:work.trb_net16_med_ecp3_sfp_4_onboard_work_trb3_central_trb3_central_arch_16layer0} -type {locked,partition} +define_compile_point {v:work.trb_net16_hub_streaming_port_sctrl_cts_work_trb3_central_trb3_central_arch_36layer0} -type {locked,partition} +define_compile_point {v:work.trb_net16_gbe_buf_0_0} -type {locked,partition} +define_compile_point {v:work.TDC_5_0_2} -type {locked,partition} +define_compile_point {v:work.CTS_work_trb3_central_trb3_central_arch_6layer0} -type {locked,partition} +define_compile_point {v:work.trb_net16_regIO_work_trb3_central_trb3_central_arch_29layer0} -type {locked,partition} +###==== END "Compile Points" + + diff --git a/cts/project2/cts.ldf b/cts/project2/cts.ldf index 7c447c2..0528c19 100755 --- a/cts/project2/cts.ldf +++ b/cts/project2/cts.ldf @@ -448,7 +448,7 @@ - + @@ -498,6 +498,15 @@ + + + + + + + + + diff --git a/cts/source/cts_pkg.vhd b/cts/source/cts_pkg.vhd index dcaffa9..094652f 100755 --- a/cts/source/cts_pkg.vhd +++ b/cts/source/cts_pkg.vhd @@ -99,6 +99,33 @@ package cts_pkg is ); end component; + component mbs_vulom_recv is + port( + CLK : in std_logic; -- e.g. 100 MHz + RESET_IN : in std_logic; -- could be used after busy_release to make sure entity is in correct state + + --Module inputs + MBS_IN : in std_logic; -- raw input + CLK_200 : in std_logic; -- internal sampling clock + + --trigger outputs + TRG_ASYNC_OUT : out std_logic; -- asynchronous rising edge, length varying, here: approx. 110 ns + TRG_SYNC_OUT : out std_logic; -- sync. to CLK + + --data output for read-out + TRIGGER_IN : in std_logic; + DATA_OUT : out std_logic_vector(31 downto 0); + WRITE_OUT : out std_logic; + STATUSBIT_OUT: out std_logic_vector(31 downto 0); + FINISHED_OUT : out std_logic; + + --Registers / Debug + CONTROL_REG_IN : in std_logic_vector(31 downto 0); + STATUS_REG_OUT : out std_logic_vector(31 downto 0); + DEBUG : out std_logic_vector(31 downto 0) + ); + end component; + component CTS_TRIGGER is generic ( TRIGGER_INPUT_COUNT : integer range 1 to 8 := 4; diff --git a/cts/trb3_central.p2t b/cts/trb3_central.p2t index 7b937b7..41d2ae3 100644 --- a/cts/trb3_central.p2t +++ b/cts/trb3_central.p2t @@ -1,10 +1,10 @@ -w -i 15 -l 5 --n 1 +-n 5 -y -s 12 --t 14 +-t 20 -c 1 -e 2 #-g guidefile.ncd diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index 0784f9b..69ee759 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -26,6 +26,10 @@ set_option -fixgatedclocks 3 set_option -fixgeneratedclocks 3 set_option -compiler_compatible true +set_option -max_parallel_jobs 3 +#set_option -automatic_compile_point 1 +#set_option -continue_on_error 1 +set_option -resolve_multiple_driver 1 # simulation options set_option -write_verilog 0 @@ -50,8 +54,9 @@ impl -active "workdir" #add_file options -add_file -vhdl -lib work "version.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_std.vhd" +add_file -vhdl -lib work "version.vhd" +add_file -vhdl -lib work "config.vhd" add_file -vhdl -lib work "../../trbnet/trb_net_components.vhd" add_file -vhdl -lib work "../../trbnet/trb_net16_hub_func.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/lattice_ecp2m_fifo.vhd" @@ -215,12 +220,14 @@ add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net16_fifo_arch.vhd" add_file -vhdl -lib work "../../trbnet/lattice/ecp3/trb_net_fifo_16bit_bram_dualport.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_onboard_full.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/serdes_full_ctc.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_ctc.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/ecp3_sfp/sfp_0_200_int.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_lsm_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp.vhd" add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4_onboard.vhd" +add_file -vhdl -lib work "../../trbnet/media_interfaces/trb_net16_med_ecp3_sfp_4.vhd" add_file -vhdl -lib work "../base/cores/pll_in200_out100.vhd" add_file -vhdl -lib work "../../trbnet/optical_link/f_divider.vhd" @@ -253,6 +260,5 @@ add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/TDC.vhd" add_file -vhdl -lib "work" "../tdc_releases/tdc_v1.1.1/up_counter.vhd" add_file -vhdl -lib work "./trb3_central.vhd" - - +#add_file -fpga_constraint "./cts.fdc" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index a5ec572..396d7a6 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -1,7 +1,7 @@ library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; -USE IEEE.std_logic_UNSIGNED.ALL; +use ieee.std_logic_unsigned.all; library work; use work.trb_net_std.all; @@ -12,7 +12,12 @@ library work; use work.trb_net_gbe_components.all; use work.cts_pkg.all; - + +--Configuration is done in this file: + use work.config.all; +-- The description of hub ports is also there! + + --Ports: -- LVL1/IPU SCtrl -- 0 FPGA 1 FPGA 1 @@ -20,23 +25,10 @@ library work; -- 2 FPGA 3 FPGA 3 -- 3 FPGA 4 FPGA 4 -- 4 opt. link opt. link --- 5 CTS read-out internal 0 1 - X X O --downlink only --- 6 CTS TRG Sctrl GbE 2 3 4 X X X --uplink only +-- 5-7 SFP 2-4 +-- 5(8) CTS read-out internal 0 1 - X X O --downlink only +-- 6(9) CTS TRG Sctrl GbE 2 3 4 X X X --uplink only --- MII_NUMBER => 5, --- INT_NUMBER => 5, --- INT_CHANNELS => (0,1,0,1,3), - --- No trigger / sctrl sent to optical link, slow control receiving possible --- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); --- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0); --- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); - --- Trigger / sctrl sent to optical link, slow control receiving possible --- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0); --- MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0); --- MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0); --- & disable port 4 in c0 and c1 -- no triggers from/to optical link --Slow Control -- 0 - 7 Readout endpoint common status @@ -52,7 +44,6 @@ library work; entity trb3_central is - port( --Clocks CLK_EXT : in std_logic_vector(4 downto 3); --from RJ45 @@ -73,10 +64,10 @@ entity trb3_central is CLK_SERDES_INT_RIGHT : in std_logic; --Clock Manager 1/0, off, 125 MHz possible --SFP - SFP_RX_P : in std_logic_vector(6 downto 1); - SFP_RX_N : in std_logic_vector(6 downto 1); - SFP_TX_P : out std_logic_vector(6 downto 1); - SFP_TX_N : out std_logic_vector(6 downto 1); + SFP_RX_P : in std_logic_vector(9 downto 1); + SFP_RX_N : in std_logic_vector(9 downto 1); + SFP_TX_P : out std_logic_vector(9 downto 1); + SFP_TX_N : out std_logic_vector(9 downto 1); SFP_TX_FAULT : in std_logic_vector(8 downto 1); --TX broken SFP_RATE_SEL : out std_logic_vector(8 downto 1); --not supported by our SFP SFP_LOS : in std_logic_vector(8 downto 1); --Loss of signal @@ -188,22 +179,24 @@ architecture trb3_central_arch of trb3_central is attribute syn_keep of GSR_N : signal is true; attribute syn_preserve of GSR_N : signal is true; + + --FPGA Test signal time_counter, time_counter2 : unsigned(31 downto 0); --Media Interface - signal med_stat_op : std_logic_vector (5*16-1 downto 0); - signal med_ctrl_op : std_logic_vector (5*16-1 downto 0); - signal med_stat_debug : std_logic_vector (5*64-1 downto 0); - signal med_ctrl_debug : std_logic_vector (5*64-1 downto 0); - signal med_data_out : std_logic_vector (5*16-1 downto 0); - signal med_packet_num_out : std_logic_vector (5*3-1 downto 0); - signal med_dataready_out : std_logic_vector (5*1-1 downto 0); - signal med_read_out : std_logic_vector (5*1-1 downto 0); - signal med_data_in : std_logic_vector (5*16-1 downto 0); - signal med_packet_num_in : std_logic_vector (5*3-1 downto 0); - signal med_dataready_in : std_logic_vector (5*1-1 downto 0); - signal med_read_in : std_logic_vector (5*1-1 downto 0); + signal med_stat_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_ctrl_op : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_stat_debug : std_logic_vector (INTERFACE_NUM*64-1 downto 0); + signal med_ctrl_debug : std_logic_vector (INTERFACE_NUM*64-1 downto 0); + signal med_data_out : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_packet_num_out : std_logic_vector (INTERFACE_NUM*3-1 downto 0); + signal med_dataready_out : std_logic_vector (INTERFACE_NUM*1-1 downto 0); + signal med_read_out : std_logic_vector (INTERFACE_NUM*1-1 downto 0); + signal med_data_in : std_logic_vector (INTERFACE_NUM*16-1 downto 0); + signal med_packet_num_in : std_logic_vector (INTERFACE_NUM*3-1 downto 0); + signal med_dataready_in : std_logic_vector (INTERFACE_NUM*1-1 downto 0); + signal med_read_in : std_logic_vector (INTERFACE_NUM*1-1 downto 0); --Hub signal common_stat_regs : std_logic_vector (std_COMSTATREG*32-1 downto 0); @@ -312,10 +305,10 @@ architecture trb3_central_arch of trb3_central is signal cts_ext_control : std_logic_vector(31 downto 0); signal cts_ext_debug : std_logic_vector(31 downto 0); - signal cts_rdo_additional_data : std_logic_vector(63 downto 0); - signal cts_rdo_additional_write : std_logic_vector(1 downto 0) := "00"; - signal cts_rdo_additional_finished : std_logic_vector(1 downto 0) := "00"; - signal cts_rdo_trg_status_bits_additional : std_logic_vector(63 downto 0) := (others => '0'); + signal cts_rdo_additional_data : std_logic_vector(31+INCLUDE_TDC*32 downto 0); + signal cts_rdo_additional_write : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0'); + signal cts_rdo_additional_finished : std_logic_vector(0+INCLUDE_TDC downto 0) := (others => '0'); + signal cts_rdo_trg_status_bits_additional : std_logic_vector(31+INCLUDE_TDC*32 downto 0) := (others => '0'); signal cts_rdo_trg_type : std_logic_vector(3 downto 0); signal cts_rdo_trg_code : std_logic_vector(7 downto 0); signal cts_rdo_trg_information : std_logic_vector(23 downto 0); @@ -410,37 +403,11 @@ architecture trb3_central_arch of trb3_central is signal tdc_ctrl_data_out : std_logic_vector(31 downto 0); signal tdc_ctrl_reg : std_logic_vector(4*32-1 downto 0); signal tdc_debug : std_logic_vector(15 downto 0); - - component mbs_vulom_recv is - port( - CLK : in std_logic; -- e.g. 100 MHz - RESET_IN : in std_logic; -- could be used after busy_release to make sure entity is in correct state - - --Module inputs - MBS_IN : in std_logic; -- raw input - CLK_200 : in std_logic; -- internal sampling clock - - --trigger outputs - TRG_ASYNC_OUT : out std_logic; -- asynchronous rising edge, length varying, here: approx. 110 ns - TRG_SYNC_OUT : out std_logic; -- sync. to CLK - - --data output for read-out - TRIGGER_IN : in std_logic; - DATA_OUT : out std_logic_vector(31 downto 0); - WRITE_OUT : out std_logic; - STATUSBIT_OUT: out std_logic_vector(31 downto 0); - FINISHED_OUT : out std_logic; - - --Registers / Debug - CONTROL_REG_IN : in std_logic_vector(31 downto 0); - STATUS_REG_OUT : out std_logic_vector(31 downto 0); - DEBUG : out std_logic_vector(31 downto 0) - ); - end component; + begin -- MBS Module - THE_MBS: mbs_vulom_recv + THE_MBS: entity work.mbs_vulom_recv port map ( CLK => clk_100_i, RESET_IN => reset_i, @@ -593,8 +560,10 @@ THE_MAIN_PLL : pll_in200_out100 --------------------------------------------------------------------------- --- The TrbNet media interface (Uplink) +-- The TrbNet media interface (SFP) --------------------------------------------------------------------------- + +gen_single_sfp : if USE_4_SFP = c_NO generate THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp generic map( SERDES_NUM => 0, --number of serdes in quad @@ -620,10 +589,10 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp MED_READ_IN => med_read_out(4), REFCLK2CORE_OUT => open, --SFP Connection - SD_RXD_P_IN => SFP_RX_P(1), - SD_RXD_N_IN => SFP_RX_N(1), - SD_TXD_P_OUT => SFP_TX_P(1), - SD_TXD_N_OUT => SFP_TX_N(1), + SD_RXD_P_IN => SFP_RX_P(5), + SD_RXD_N_IN => SFP_RX_N(5), + SD_TXD_P_OUT => SFP_TX_P(5), + SD_TXD_N_OUT => SFP_TX_N(5), SD_REFCLK_P_IN => open, SD_REFCLK_N_IN => open, SD_PRSNT_N_IN => SFP_MOD0(1), @@ -635,9 +604,59 @@ THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp STAT_DEBUG => med_stat_debug(4*64+63 downto 4*64), CTRL_DEBUG => (others => '0') ); - - SFP_TXDIS(7 downto 2) <= (others => '1'); +end generate; + +gen_four_sfp : if USE_4_SFP = c_YES generate + THE_MEDIA_UPLINK : trb_net16_med_ecp3_sfp_4 + generic map( + REVERSE_ORDER => c_NO, --order of ports + FREQUENCY => 200 --run on 200 MHz clock + ) + port map( + CLK => clk_200_i, + SYSCLK => clk_100_i, + RESET => reset_i, + CLEAR => clear_i, + CLK_EN => '1', + --Internal Connection + MED_DATA_IN => med_data_out(127 downto 64), + MED_PACKET_NUM_IN => med_packet_num_out(23 downto 12), + MED_DATAREADY_IN => med_dataready_out(7 downto 4), + MED_READ_OUT => med_read_in(7 downto 4), + MED_DATA_OUT => med_data_in(127 downto 64), + MED_PACKET_NUM_OUT => med_packet_num_in(23 downto 12), + MED_DATAREADY_OUT => med_dataready_in(7 downto 4), + MED_READ_IN => med_read_out(7 downto 4), + + REFCLK2CORE_OUT => open, + --SFP Connection + SD_RXD_P_IN => SFP_RX_P(8 downto 5), + SD_RXD_N_IN => SFP_RX_N(8 downto 5), + SD_TXD_P_OUT => SFP_TX_P(8 downto 5), + SD_TXD_N_OUT => SFP_TX_N(8 downto 5), + SD_REFCLK_P_IN => open, + SD_REFCLK_N_IN => open, + SD_PRSNT_N_IN => SFP_MOD0(4 downto 1), + SD_LOS_IN => SFP_LOS(4 downto 1), + SD_TXDIS_OUT => SFP_TXDIS(4 downto 1), + +-- SCI_DATA_IN => sci1_data_in, +-- SCI_DATA_OUT => sci1_data_out, +-- SCI_ADDR => sci1_addr, +-- SCI_READ => sci1_read, +-- SCI_WRITE => sci1_write, +-- SCI_ACK => sci1_ack, + -- Status and control port + + STAT_OP => med_stat_op(7*16+15 downto 4*16), + CTRL_OP => med_ctrl_op(7*16+15 downto 4*16), + + STAT_DEBUG => open, + CTRL_DEBUG => (others => '0') + ); +SFP_TXDIS(7 downto 5) <= (others => '1'); +end generate; --------------------------------------------------------------------------- -- The TrbNet media interface (to other FPGA) @@ -660,10 +679,10 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard MED_READ_IN => med_read_out(3 downto 0), REFCLK2CORE_OUT => open, --SFP Connection - SD_RXD_P_IN => SFP_RX_P(5 downto 2), - SD_RXD_N_IN => SFP_RX_N(5 downto 2), - SD_TXD_P_OUT => SFP_TX_P(5 downto 2), - SD_TXD_N_OUT => SFP_TX_N(5 downto 2), + SD_RXD_P_IN => SFP_RX_P(4 downto 1), + SD_RXD_N_IN => SFP_RX_N(4 downto 1), + SD_TXD_P_OUT => SFP_TX_P(4 downto 1), + SD_TXD_N_OUT => SFP_TX_N(4 downto 1), SD_REFCLK_P_IN => open, SD_REFCLK_N_IN => open, SD_PRSNT_N_IN(0) => FPGA1_COMM(2), @@ -695,14 +714,10 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard THE_HUB: trb_net16_hub_streaming_port_sctrl_cts generic map( INIT_ADDRESS => x"F3C0", - MII_NUMBER => 5, --- MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), --- MII_IS_DOWNLINK => (1,1,1,1,0,1,0,0,0,0,0,0,0,0,0,0,0), --- MII_IS_UPLINK_ONLY => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), - MII_IS_UPLINK => (0,0,0,0,1,0,1,0,0,0,0,0,0,0,0,0,0), - MII_IS_DOWNLINK => (1,1,1,1,1,1,0,0,0,0,0,0,0,0,0,0,0), - MII_IS_UPLINK_ONLY => (0,0,0,0,0,0,1,0,0,0,0,0,0,0,0,0,0), - COMPILE_TIME => std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,32)), + MII_NUMBER => INTERFACE_NUM, + MII_IS_UPLINK => IS_UPLINK, + MII_IS_DOWNLINK => IS_DOWNLINK, + MII_IS_UPLINK_ONLY => IS_UPLINK_ONLY, COMPILE_VERSION => x"0001", HARDWARE_VERSION => x"9000CEE0", INIT_ENDPOINT_ID => x"0005", @@ -710,7 +725,7 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard CLOCK_FREQUENCY => 100, USE_ONEWIRE => c_YES, BROADCAST_SPECIAL_ADDR => x"35", - RDO_ADDITIONAL_PORT => 2, + RDO_ADDITIONAL_PORT => cts_rdo_additional_ports, RDO_DATA_BUFFER_DEPTH => 9, RDO_DATA_BUFFER_FULL_THRESH => 2**9-128, RDO_HEADER_BUFFER_DEPTH => 9, @@ -722,16 +737,16 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard CLK_EN => '1', -- Media interfacces --------------------------------------------------------------- - MED_DATAREADY_OUT(5*1-1 downto 0) => med_dataready_out, - MED_DATA_OUT(5*16-1 downto 0) => med_data_out, - MED_PACKET_NUM_OUT(5*3-1 downto 0) => med_packet_num_out, - MED_READ_IN(5*1-1 downto 0) => med_read_in, - MED_DATAREADY_IN(5*1-1 downto 0) => med_dataready_in, - MED_DATA_IN(5*16-1 downto 0) => med_data_in, - MED_PACKET_NUM_IN(5*3-1 downto 0) => med_packet_num_in, - MED_READ_OUT(5*1-1 downto 0) => med_read_out, - MED_STAT_OP(5*16-1 downto 0) => med_stat_op, - MED_CTRL_OP(5*16-1 downto 0) => med_ctrl_op, + MED_DATAREADY_OUT(INTERFACE_NUM*1-1 downto 0) => med_dataready_out, + MED_DATA_OUT(INTERFACE_NUM*16-1 downto 0) => med_data_out, + MED_PACKET_NUM_OUT(INTERFACE_NUM*3-1 downto 0) => med_packet_num_out, + MED_READ_IN(INTERFACE_NUM*1-1 downto 0) => med_read_in, + MED_DATAREADY_IN(INTERFACE_NUM*1-1 downto 0) => med_dataready_in, + MED_DATA_IN(INTERFACE_NUM*16-1 downto 0) => med_data_in, + MED_PACKET_NUM_IN(INTERFACE_NUM*3-1 downto 0) => med_packet_num_in, + MED_READ_OUT(INTERFACE_NUM*1-1 downto 0) => med_read_out, + MED_STAT_OP(INTERFACE_NUM*16-1 downto 0) => med_stat_op, + MED_CTRL_OP(INTERFACE_NUM*16-1 downto 0) => med_ctrl_op, -- Gbe Read-out Path --------------------------------------------------------------- --Event information coming from CTS for GbE @@ -907,10 +922,10 @@ THE_MEDIA_ONBOARD : trb_net16_med_ecp3_sfp_4_onboard FEE_STATUS_BITS_IN => gbe_fee_status_bits, FEE_BUSY_IN => gbe_fee_busy, --SFP Connection - SFP_RXD_P_IN => SFP_RX_P(6), --these ports are don't care - SFP_RXD_N_IN => SFP_RX_N(6), - SFP_TXD_P_OUT => SFP_TX_P(6), - SFP_TXD_N_OUT => SFP_TX_N(6), + SFP_RXD_P_IN => SFP_RX_P(9), --these ports are don't care + SFP_RXD_N_IN => SFP_RX_N(9), + SFP_TXD_P_OUT => SFP_TX_P(9), + SFP_TXD_N_OUT => SFP_TX_N(9), SFP_REFCLK_P_IN => open, --SFP_REFCLKP(2), SFP_REFCLK_N_IN => open, --SFP_REFCLKN(2), SFP_PRSNT_N_IN => SFP_MOD0(8), -- SFP Present ('0' = SFP in place, '1' = no SFP mounted) @@ -1182,6 +1197,7 @@ THE_FPGA_REBOOT : fpga_reboot ------------------------------------------------------------------------------- -- TDC ------------------------------------------------------------------------------- +gen_TDC : if INCLUDE_TDC = c_YES generate THE_TDC : TDC generic map ( CHANNEL_NUMBER => 5, -- Number of TDC channels @@ -1255,9 +1271,19 @@ THE_FPGA_REBOOT : fpga_reboot LHB_UNKNOWN_ADDR_OUT => open, -- lhb_invalid, -- bus invalid addr -- LOGIC_ANALYSER_OUT => tdc_debug, - CONTROL_REG_IN => tdc_ctrl_reg); - - + CONTROL_REG_IN => tdc_ctrl_reg + ); +end generate; + +gen_no_TDC : if INCLUDE_TDC = c_NO generate + + srb_invalid <= '1'; + esb_invalid <= '1'; + fwb_invalid <= '1'; + hitreg_invalid <= '1'; +end generate; + + --------------------------------------------------------------------------- -- Clock and Trigger Configuration --------------------------------------------------------------------------- diff --git a/cts/trb3_central_constraints.lpf b/cts/trb3_central_constraints.lpf index 56f8b3e..9f0e7c5 100644 --- a/cts/trb3_central_constraints.lpf +++ b/cts/trb3_central_constraints.lpf @@ -25,7 +25,9 @@ GSR_NET NET "GSR_N"; # Locate Serdes and media interfaces ################################################################# LOCATE COMP "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/clk_int_SERDES_GBE/PCSD_INST" SITE "PCSB"; -LOCATE COMP "THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_single_sfp_THE_MEDIA_UPLINK/gen_serdes_0_200_ctc_THE_SERDES/PCSD_INST" SITE "PCSA" ; +LOCATE COMP "gen_four_sfp_THE_MEDIA_UPLINK/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSA" ; + LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_200_THE_SERDES/PCSD_INST" SITE "PCSC" ; LOCATE COMP "THE_MEDIA_ONBOARD/gen_serdes_125_THE_SERDES/PCSD_INST" SITE "PCSC" ; @@ -33,14 +35,16 @@ MULTICYCLE TO CELL "THE_RESET_HANDLER/final_reset_*" 30 ns; MULTICYCLE TO CELL "THE_HUB/THE_HUB/local_network_reset*" 30 ns; -REGION "MEDIA_UPLINK" "R98C95" 17 27; -LOCATE UGROUP "THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +REGION "MEDIA_UPLINK" "R92C90" 22 76; +LOCATE UGROUP "gen_four_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +LOCATE UGROUP "gen_single_sfp_THE_MEDIA_UPLINK/media_interface_group" REGION "MEDIA_UPLINK" ; +LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_UPLINK" ; -REGION "MEDIA_ONBOARD" "R90C122" 20 40; -LOCATE UGROUP "THE_MEDIA_ONBOARD/media_interface_group" REGION "MEDIA_ONBOARD" ; +#REGION "MEDIA_ONBOARD" "R90C122" 20 40; MULTICYCLE TO CELL "THE_MEDIA_DOWNLINK/SCI_DATA_OUT*" 50 ns; -MULTICYCLE TO CELL "THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "gen_single_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; +MULTICYCLE TO CELL "gen_four_sfp_THE_MEDIA_UPLINK/SCI_DATA_OUT*" 50 ns; #SPI Interface REGION "REGION_SPI" "R13C150D" 12 16 DEVSIZE; @@ -55,7 +59,7 @@ MULTICYCLE TO CELL "THE_MBS/trg_sync" 20 ns; MULTICYCLE TO CELL "THE_MBS/error_reg" 20 ns; #TrbNet Hub -REGION "REGION_IOBUF" "R54C90D" 60 86 DEVSIZE; +REGION "REGION_IOBUF" "R40C90D" 55 75 DEVSIZE; LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_0_MPLEX/MUX_group" REGION "REGION_IOBUF" ; LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_1_MPLEX/MUX_group" REGION "REGION_IOBUF" ; LOCATE UGROUP "THE_HUB/THE_HUB/gen_muxes_2_MPLEX/MUX_group" REGION "REGION_IOBUF" ; @@ -111,8 +115,61 @@ LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_0_gen_iobuf_IOBUF/genINITOB LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_1_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; LOCATE UGROUP "THE_HUB/THE_HUB/gen_bufs_4_gen_iobufs_3_gen_iobuf_IOBUF/genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; - - +# THE_HUB.THE_HUB.gen_bufs.0.gen_iobufs.1.gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.0_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.1_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.2_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.3_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_muxes.4_MPLEX/MUX_group" REGION "REGION_IOBUF" ; +# +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_hub_logic.1_gen_logic_gen_select_logic2_HUBLOGIC/HUBIPULOGIC_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_hub_logic.0_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_hub_logic.3_gen_logic_gen_select_logic1_HUBLOGIC/HUBLOGIC_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF1_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF1_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.0_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.1_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.3_gen_iobuf.IOBUF.GEN_IBUF.THE_IBUF/IBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.0_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.1_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.2_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.0_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.1_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.3_gen_iobufs.3_gen_iobuf.IOBUF.genREPLYOBUF2_gen_REPLYOBUF3_REPLYOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.0_gen_iobuf.IOBUF.genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.1_gen_iobuf.IOBUF.genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; +# LOCATE UGROUP "THE_HUB.THE_HUB.gen_bufs.4_gen_iobufs.3_gen_iobuf.IOBUF.genINITOBUF2_gen_INITOBUF3_INITOBUF/OBUF_group" REGION "REGION_IOBUF"; #GbE Part @@ -146,12 +203,12 @@ UGROUP "gbe_rx_tx" BLKNAME GBE/FRAME_CONSTRUCTOR BLKNAME GBE/MB_IP_CONFIG BLKNAME GBE/THE_IP_CONFIGURATOR - #BLKNAME GBE/PACKET_CONSTRUCTOR - #BLKNAME GBE/THE_IPU_INTERFACE +# BLKNAME GBE/PACKET_CONSTRUCTOR +# BLKNAME GBE/THE_IPU_INTERFACE BLKNAME GBE/setup_imp_gen_SETUP; -REGION "GBE_REGION" "R50C12D" 25 35 DEVSIZE; +REGION "GBE_REGION" "R44C45D" 36 42 DEVSIZE; REGION "MED0" "R81C10D" 34 40 DEVSIZE; LOCATE UGROUP "gbe_rx_tx" REGION "GBE_REGION" ; FREQUENCY NET "GBE/imp_gen_serdes_intclk_gen_PCS_SERDES/un1_PCS_SERDES_1" 125.000000 MHz ; @@ -260,16 +317,16 @@ PRIORITIZE NET "GBE/pcs_rxd_q_6" 100; PRIORITIZE NET "GBE/pcs_rxd_q_7" 100; PRIORITIZE NET "GBE/pcs_rxd_q_0" 100; PRIORITIZE NET "GBE/serdes_rx_clk_c" 80; - -BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ; -BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ; - -MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ; -MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ; -MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ; -MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ; -MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ; -MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ; -MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ; +# +# BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac*" ; +# BLOCK PATH FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_cpu_if*" TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_rx_mac*" ; +# +# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/sync_rxd_m*" 2.000000 X ; +# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/ipg_shrink_m*" 2.000000 X ; +# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_gmii/nib_alig*" 2.000000 X ; +# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ; +# MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/rd_ptr*" 2.000000 X ; +# MULTICYCLE TO CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ; +# MULTICYCLE FROM CELL "*U1_ts_mac_core*U1_LSC_ts_mac_core/U1_tx_mac/U1_tx_rfifo/wr_ptr*" 2.000000 X ; #BLOCK INTERCLOCKDOMAIN PATHS ; \ No newline at end of file -- 2.43.0