From 542373e0ffd86a630485f297b4ada3239ab5e18e Mon Sep 17 00:00:00 2001
From: Hadaq in Frankfurt <hadaq@frankfurt>
Date: Thu, 11 Apr 2013 18:58:24 +0200
Subject: [PATCH] added remark about USB cable

---
 trb3/Trb3GeneralRemarks.tex | 10 ++++++++++
 trb3/VhdlProjectSetup.tex   |  7 +++++--
 trb3/main.tex               |  3 +--
 3 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/trb3/Trb3GeneralRemarks.tex b/trb3/Trb3GeneralRemarks.tex
index fc525ed..7e7beae 100644
--- a/trb3/Trb3GeneralRemarks.tex
+++ b/trb3/Trb3GeneralRemarks.tex
@@ -147,6 +147,16 @@ The pin-out of the JTAG connector (1x8 pin-header near the power supply).
 \end{description*}
 Pin 1 is next to the 2x6 pin-header. Note that TDO and TDI are switched compared to the layout on all other boards. If you experience strange behavior of the programming procedure and think you might have destroyed the cable: It's most likely a software issue - reboot your PC!
 
+Note that the programming cable can only be used as root by default in most Linux flavours. You can either change permissions on the device in /dev/ by hand or put this (as one line!)
+\\\verb!SUBSYSTEMS=="usb", ATTRS{idVendor}=="1134", SYMLINK+="lattice_cable",!
+\\\verb!GROUP="users", MODE="0666"'! 
+\\into 
+\\\files{/etc/udev/rules.d/91-usb-hardware.rules} 
+\\and run
+\\\verb!udevadm control --reload-rules; udevadm trigger!
+\\\verb!/etc/init.d/boot.udev restart!
+\\Commands and files might be different on your machine.
+
 
 \subsection{Data Unpacker}
 \label{Data_Unpacking}
diff --git a/trb3/VhdlProjectSetup.tex b/trb3/VhdlProjectSetup.tex
index 185f58f..7694ca0 100644
--- a/trb3/VhdlProjectSetup.tex
+++ b/trb3/VhdlProjectSetup.tex
@@ -14,13 +14,16 @@ A not complete list of steps how to create a new TRB3 VHDL project.
 \item Copy necessary files from another project. Choose one using the same FPGA you want to create your project and if possible one that uses the same pinout.
 \begin{description*}
 \item[\files{compile*.pl}] The main script that runs synthesis, map, par...
-\item[\files{}]
+\item[\files{*.prj}] The project settings and list of source files
+\item[\files{*constraints.lpf}] The file with constraints specific for a design
+\item[\files{*.p2t}] Settings for the place and route tool
+\item[\files{*.vhd}] The top-level vhd file as basis for the new design
 \end{description*}
 \item Edit \files{compile*.pl}
 \begin{itemize*}
 \item Set the \cmdname{\$projectname}
 \item Check that all configuration options (the marked block in the beginning of the file) match your local environment.
-\item Check the 2 to 4 lines generating the constraint file if it accesses the correct files.
+\item Check the 2 to 4 lines generating the constraint file if it accesses the correct files. One file from the base directory gives the pin-out, a local file gives the project-dependent constraints. For TDCs, another file is included.
 \end{itemize*}
 \item Edit \files{\$projectname.prj}
 \begin{itemize*}
diff --git a/trb3/main.tex b/trb3/main.tex
index 61309d0..8225363 100644
--- a/trb3/main.tex
+++ b/trb3/main.tex
@@ -215,8 +215,7 @@
 
 \cleardoublepage
 \input{trb3qs_part}
-  \section{New Hardware Project}
-  \input{HardwareProject}
+
 
 \cleardoublepage
 \part{Synchronous TrbNet}
-- 
2.43.0