From 544845124a65989d244a0b9b5538c29e31aa8822 Mon Sep 17 00:00:00 2001 From: Michael Boehmer Date: Tue, 19 Apr 2022 12:27:20 +0200 Subject: [PATCH] fixes --- special/statistics.vhd | 89 ++++++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 43 deletions(-) diff --git a/special/statistics.vhd b/special/statistics.vhd index 252f7fb..cc533f4 100644 --- a/special/statistics.vhd +++ b/special/statistics.vhd @@ -5,18 +5,18 @@ use ieee.numeric_std.all; entity statistics is port( AUXCLK : in std_logic; - RESET : in std_logic; + RESET : in std_logic; DELAY_VALUE_IN : in std_logic_vector(9 downto 0); DELAY_VALID_IN : in std_logic; FSM_START_IN : in std_logic; - FSM_CLR_DONE_IN : in std_logic; + FSM_CLR_DONE_IN : in std_logic; FSM_ACTIVE_OUT : out std_logic; FSM_CE_OUT : out std_logic; - FSM_RST_OUT : out std_logic; + FSM_RST_OUT : out std_logic; FSM_DONE_OUT : out std_logic; RD_CLK : in std_logic; - RD_ADDRESS_IN : in std_logic_vector(9 downto 0); - RD_DATA_OUT : out std_logic_vector(17 downto 0) + RD_ADDRESS_IN : in std_logic_vector(9 downto 0); + RD_DATA_OUT : out std_logic_vector(17 downto 0) ); end; @@ -31,48 +31,48 @@ architecture behavioural of statistics is -- Signals signal fsm_act_x : std_logic; signal fsm_act_q : std_logic; - signal fsm_ce_x : std_logic; - signal fsm_ce_q : std_logic; + signal fsm_ce_x : std_logic; + signal fsm_ce_q : std_logic; signal fsm_rst_x : std_logic; signal fsm_rst_q : std_logic; - signal fsm_we_x : std_logic; - signal fsm_we_q : std_logic; - signal fsm_done_x : std_logic; - signal fsm_done_q : std_logic; + signal fsm_we_x : std_logic; + signal fsm_we_q : std_logic; + signal fsm_done_x : std_logic; + signal fsm_done_q : std_logic; signal sum_ctr : unsigned(18 downto 0); signal sum_ctr_rst_x : std_logic; signal sum_ctr_rst : std_logic; - signal sum_ctr_ce_x : std_logic; - signal sum_ctr_ce : std_logic; - signal sum_ctr_done : std_logic; + signal sum_ctr_ce_x : std_logic; + signal sum_ctr_ce : std_logic; + signal sum_ctr_done : std_logic; signal old_entry : std_logic_vector(17 downto 0); signal new_entry_x : unsigned(17 downto 0); signal new_entry : std_logic_vector(17 downto 0); signal clr_entry : std_logic; - signal mean_sum_x : unsigned(31 downto 0); - signal mean_sum_q : unsigned(31 downto 0); + signal mean_sum_x : unsigned(31 downto 0); + signal mean_sum_q : unsigned(31 downto 0); - component stat_mem is + component statmem is port( - DATAINA : in std_logic_vector(17 downto 0); - DATAINB : in std_logic_vector(17 downto 0); + DATAINA : in std_logic_vector(17 downto 0); + DATAINB : in std_logic_vector(17 downto 0); ADDRESSA : in std_logic_vector(9 downto 0); ADDRESSB : in std_logic_vector(9 downto 0); CLOCKA : in std_logic; CLOCKB : in std_logic; CLOCKENA : in std_logic; CLOCKENB : in std_logic; - WRA : in std_logic; - WRB : in std_logic; + WRA : in std_logic; + WRB : in std_logic; RESETA : in std_logic; RESETB : in std_logic; QA : out std_logic_vector(17 downto 0); QB : out std_logic_vector(17 downto 0) ); - end component stat_mem; + end component statmem; attribute HGROUP: string; --attribute BBOX: string; @@ -121,8 +121,8 @@ begin sum_ctr_ce_x <= '0'; sum_ctr_rst_x <= '0'; case STATE is - when IDLE => bsm <= x"0"; - if( FSM_START_IN = '1') then + when IDLE => bsm <= x"0"; + if( FSM_START_IN = '1' ) then NEXT_STATE <= RSTCTR; fsm_act_x <= '1'; fsm_rst_x <= '1'; @@ -130,16 +130,16 @@ begin else NEXT_STATE <= IDLE; end if; - when RSTCTR => bsm <= x"1"; + when RSTCTR => bsm <= x"1"; NEXT_STATE <= DLY0; fsm_act_x <= '1'; fsm_we_x <= '1'; - when DLY0 => bsm <= x"2"; + when DLY0 => bsm <= x"2"; NEXT_STATE <= WCLR; fsm_act_x <= '1'; fsm_ce_x <= '1'; fsm_we_x <= '1'; - when WCLR => bsm <= x"3"; + when WCLR => bsm <= x"3"; if( FSM_CLR_DONE_IN = '1' ) then NEXT_STATE <= PCTR; fsm_act_x <= '1'; @@ -151,10 +151,10 @@ begin fsm_ce_x <= '1'; fsm_we_x <= '1'; end if; - when PCTR => bsm <= x"4"; + when PCTR => bsm <= x"4"; NEXT_STATE <= DLY1; fsm_act_x <= '1'; - when DLY1 => bsm <= x"5"; + when DLY1 => bsm <= x"5"; if( DELAY_VALID_IN = '1' ) then NEXT_STATE <= WFD; else @@ -168,11 +168,11 @@ begin else NEXT_STATE <= WFD; end if; - when WFD1 => bsm <= x"7"; + when WFD1 => bsm <= x"7"; NEXT_STATE <= WFD2; - when WFD2 => bsm <= x"8"; + when WFD2 => bsm <= x"8"; NEXT_STATE <= WFD3; - when WFD3 => bsm <= x"9"; + when WFD3 => bsm <= x"9"; if ( sum_ctr_done = '1' ) then NEXT_STATE <= SDONE; fsm_done_x <= '1'; @@ -181,26 +181,30 @@ begin fsm_we_x <= '1'; end if; when SDONE => bsm <= x"a"; - NEXT_STATE <= SDONE; -- BUG - fsm_done_x <= '1'; - when others => bsm <= x"f"; + if( FSM_START_IN = '1' ) then + NEXT_STATE <= SDONE; + fsm_done_x <= '1'; + else + NEXT_STATE <= IDLE; + end if; + when others => bsm <= x"f"; NEXT_STATE <= IDLE; end case; end process THE_STATE_TRANSITIONS; -- Memory for statistics data - THE_STAT_MEM: stat_mem + THE_STAT_MEM: statmem port map( - DATAINA => new_entry, - DATAINB => (others => '0'), + DATAINA => new_entry, + DATAINB => (others => '0'), ADDRESSA => DELAY_VALUE_IN, ADDRESSB => RD_ADDRESS_IN, CLOCKA => AUXCLK, CLOCKB => RD_CLK, CLOCKENA => '1', CLOCKENB => '1', - WRA => fsm_we_q, - WRB => '0', + WRA => fsm_we_q, + WRB => '0', RESETA => RESET, RESETB => RESET, QA => old_entry, @@ -238,9 +242,8 @@ begin end if; end process THE_SUM_CTR_PROC; --- sum_ctr_done <= std_logic(sum_ctr(18)); --- sum_ctr_done <= std_logic(sum_ctr(13)); - sum_ctr_done <= std_logic(sum_ctr(16)); + sum_ctr_done <= std_logic(sum_ctr(18)); +-- sum_ctr_done <= std_logic(sum_ctr(16)); -- mean value mean_sum_x <= mean_sum_q + unsigned(DELAY_VALUE_IN); -- 2.43.0