From 5496ee119d66861d7acb10bd9789c978b475eb52 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Fri, 23 May 2014 17:15:29 +0200 Subject: [PATCH] First changes to cleaned up ADC addon design --- adc_addon/adc_addon.vhd | 958 +++++++++++----------------- adc_addon/adc_addon_constraints.lpf | 206 ------ adc_addon/compile_adc_addon_gsi.pl | 2 +- pinout/adc_addon.lpf | 188 +----- 4 files changed, 363 insertions(+), 991 deletions(-) diff --git a/adc_addon/adc_addon.vhd b/adc_addon/adc_addon.vhd index cf3721d..ae199ec 100644 --- a/adc_addon/adc_addon.vhd +++ b/adc_addon/adc_addon.vhd @@ -13,34 +13,38 @@ use machxo2.all; entity adc_addon is - generic( - TEMP_CORRECTION: integer := c_YES - ); - port( - CON : out std_logic_vector(16 downto 1); - INP : in std_logic_vector(16 downto 1); - PWM : out std_logic_vector(16 downto 1); - DISCHARGE : out std_logic_vector( 8 downto 1); - - DELAY_C_IN : in std_logic_vector( 8 downto 1); - DELAY_R_IN : in std_logic_vector( 6 downto 1); - DELAY_L_IN : in std_logic_vector( 5 downto 1); - DELAY_B_IN : in std_logic_vector( 5 downto 1); - DELAY_C_OUT : out std_logic_vector( 8 downto 1); - DELAY_R_OUT : out std_logic_vector( 6 downto 1); - DELAY_L_OUT : out std_logic_vector( 5 downto 1); - DELAY_B_OUT : out std_logic_vector( 5 downto 1); - - SPARE_LVDS : out std_logic; - LED : out std_logic_vector( 8 downto 1); - - SPI_CLK : in std_logic; - SPI_CS : in std_logic; - SPI_IN : in std_logic; - SPI_OUT : out std_logic; - TEMP_LINE : inout std_logic; - TEST_LINE : out std_logic_vector(13 downto 0) - ); + port( + + LED_WHITE : out std_logic; + LED_RED : out std_logic; + LED_GREEN : out std_logic; + LED_YELLOW : out std_logic; + LED_ORANGE : out std_logic; + + -- to TRB3 FPGA + SPI_TRB_CLK : in std_logic_vector(1 downto 0); + SPI_TRB_CS : in std_logic_vector(1 downto 0); + SPI_TRB_IN : in std_logic_vector(1 downto 0); + SPI_TRB_OUT : out std_logic_vector(1 downto 0); + + -- to CABLE_CONN1 (lower channel numbers) + SPI_CONN_L_CLK : out std_logic; + SPI_CONN_L_CS : out std_logic; + SPI_CONN_L_OUT : out std_logic; + SPI_CONN_L_IN : in std_logic; + + -- to CABLE_CONN2 (higher channel numbers) + SPI_CONN_H_CLK : out std_logic; + SPI_CONN_H_CS : out std_logic; + SPI_CONN_H_OUT : out std_logic; + SPI_CONN_H_IN : in std_logic; + + -- chip select for ADC SPI communication + ADC_CSB_reg : out std_logic_vector(12 downto 1); + + -- general purpose to JPG1 + GP_LINE : out std_logic_vector(9 downto 0) + ); end entity; @@ -50,617 +54,365 @@ end entity; architecture adc_addon_arch of adc_addon is -component OSCH + component OSCH -- synthesis translate_off - generic (NOM_FREQ: string := "133.00"); + generic (NOM_FREQ: string := "133.00"); -- synthesis translate_on - port ( - STDBY :IN std_logic; - OSC :OUT std_logic; - SEDSTDBY :OUT std_logic - ); -end component; - -component oddr16 is - port ( - clk: in std_logic; - clkout: out std_logic; - reset: in std_logic; - sclk: out std_logic; - dataout: in std_logic_vector(31 downto 0); - dout: out std_logic_vector(15 downto 0)); -end component; - -component spi_slave - port( - CLK : in std_logic; - SPI_CLK : in std_logic; - SPI_CS : in std_logic; - SPI_IN : in std_logic; - SPI_OUT : out std_logic; - - DATA_OUT : out std_logic_vector(15 downto 0); - REG00_IN : in std_logic_vector(15 downto 0); - REG10_IN : in std_logic_vector(15 downto 0); - REG20_IN : in std_logic_vector(15 downto 0); - REG40_IN : in std_logic_vector(15 downto 0); - - OPERATION_OUT : out std_logic_vector(3 downto 0); - CHANNEL_OUT : out std_logic_vector(7 downto 0); - WRITE_OUT : out std_logic_vector(15 downto 0); - - DEBUG_OUT : out std_logic_vector(15 downto 0) - ); -end component; - - -component pwm_generator - port( - CLK : in std_logic; - DATA_IN : in std_logic_vector(15 downto 0); - DATA_OUT : out std_logic_vector(15 downto 0); - COMP_IN : in signed(15 downto 0); - WRITE_IN : in std_logic; - ADDR_IN : in std_logic_vector(3 downto 0); - PWM : out std_logic_vector(31 downto 0) - ); -end component; - -component flashram - port ( - DataInA: in std_logic_vector(7 downto 0); - DataInB: in std_logic_vector(7 downto 0); - AddressA: in std_logic_vector(3 downto 0); - AddressB: in std_logic_vector(3 downto 0); - ClockA: in std_logic; - ClockB: in std_logic; - ClockEnA: in std_logic; - ClockEnB: in std_logic; - WrA: in std_logic; - WrB: in std_logic; - ResetA: in std_logic; - ResetB: in std_logic; - QA: out std_logic_vector(7 downto 0); - QB: out std_logic_vector(7 downto 0) - ); -end component; - -component pll - port ( - CLKI: in std_logic; - CLKOP: out std_logic; - CLKOS: out std_logic; - LOCK: out std_logic); -end component; - - -component UFM_WB - port( - clk_i : in std_logic; - rst_n : in std_logic; - cmd : in std_logic_vector(2 downto 0); - ufm_page : in std_logic_vector(12 downto 0); - GO : in std_logic; - BUSY : out std_logic; - ERR : out std_logic; - mem_clk : out std_logic; - mem_we : out std_logic; - mem_ce : out std_logic; - mem_addr : out std_logic_vector(3 downto 0); - mem_wr_data : out std_logic_vector(7 downto 0); - mem_rd_data : in std_logic_vector(7 downto 0) - ); -end component; - -component PUR port(PUR : in std_logic); end component; -component GSR port(GSR : in std_logic); end component; - - - -attribute NOM_FREQ : string; -attribute NOM_FREQ of clk_source : label is "133.00"; -signal clk_i : std_logic; - -signal reset_i : std_logic := '1'; -signal reset_cnt : unsigned(3 downto 0) := x"0"; -signal id_data_i : std_logic_vector(15 downto 0); -signal id_addr_i : std_logic_vector(2 downto 0); -signal id_write_i: std_logic; -signal ram_write_i : std_logic; -signal ram_data_i: std_logic_vector(7 downto 0); -signal ram_data_o: std_logic_vector(7 downto 0); -signal ram_addr_i: std_logic_vector(3 downto 0); -signal temperature_i : std_logic_vector(11 downto 0); - -type idram_t is array(0 to 7) of std_logic_vector(15 downto 0); -signal idram : idram_t; -type ram_t is array(0 to 15) of std_logic_vector(15 downto 0); -signal ram : ram_t; - -signal pwm_i : std_logic_vector(32 downto 1); -signal INP_i : std_logic_vector(15 downto 0); -signal fast_input : std_logic_vector(8 downto 1); -signal slow_input : std_logic_vector(8 downto 1); -signal spi_reg00_i : std_logic_vector(15 downto 0); -signal spi_reg10_i : std_logic_vector(15 downto 0); -signal spi_reg20_i : std_logic_vector(15 downto 0); -signal spi_reg40_i : std_logic_vector(15 downto 0); -signal spi_data_i : std_logic_vector(15 downto 0); -signal spi_operation_i : std_logic_vector(3 downto 0); -signal spi_channel_i : std_logic_vector(7 downto 0); -signal spi_write_i : std_logic_vector(15 downto 0); -signal buf_SPI_OUT : std_logic; -signal spi_debug_i : std_logic_vector(15 downto 0); -signal last_spi_channel: std_logic_vector(7 downto 0); - -signal pll_lock : std_logic; -signal clk_26 : std_logic; -signal clk_osc : std_logic; - -signal flashram_addr_i : std_logic_vector(3 downto 0); -signal flashram_cen_i : std_logic; -signal flashram_reset : std_logic; -signal flashram_write_i: std_logic; -signal flashram_data_i : std_logic_vector(7 downto 0); -signal flashram_data_o : std_logic_vector(7 downto 0); - -signal flash_command : std_logic_vector(2 downto 0); -signal flash_page : std_logic_vector(12 downto 0); -signal flash_go : std_logic; -signal flash_busy : std_logic; -signal flash_err : std_logic; - -signal inp_select : integer range 0 to 31 := 0; -signal inp_invert : std_logic_vector(15 downto 0); -signal input_enable : std_logic_vector(15 downto 0); -signal inp_status : std_logic_vector(15 downto 0); -signal led_status : std_logic_vector(8 downto 0) := "100000000"; -signal discharge_disable : std_logic_vector(8 downto 1); -signal discharge_highz : std_logic_vector(8 downto 1); -signal discharge_override : std_logic_vector(8 downto 1); -signal delay_invert : std_logic_vector(8 downto 1); - - -signal timer : unsigned(18 downto 0) := (others => '0'); -signal last_inp : std_logic_vector(15 downto 0) := (others => '0'); -signal leds : std_logic_vector(15 downto 0) := (others => '0'); -signal last_leds: std_logic_vector(15 downto 0) := (others => '0'); -signal onewire_monitor : std_logic; -signal onewire_reset : std_logic; -signal inp_or : std_logic; -signal inp_long_or : std_logic; -signal inp_long_reg : std_logic; -signal last_inp_long_reg : std_logic; - -signal inp_stretch : std_logic_vector(15 downto 0); -signal inp_stretched : std_logic_vector(15 downto 0); -signal inp_hold : std_logic_vector(15 downto 0); -signal inp_gated : std_logic_vector(15 downto 0); -signal inp_hold_reg: std_logic_vector(15 downto 0); -signal last_inp_hold_reg: std_logic_vector(15 downto 0); -signal flash_go_tmp : std_logic_vector(5 downto 0); -signal flash_reset_n : std_logic; - -signal pwm_data_i : std_logic_vector(15 downto 0); -signal pwm_data_o : std_logic_vector(15 downto 0); -signal pwm_write_i : std_logic; -signal pwm_addr_i : std_logic_vector(3 downto 0); -type fsm_state is (IDLE, PWM_WRITE_GET_1, PWM_WRITE_GET_2, PWM_WRITE, PWM_WAIT); -signal fsm_copydat : fsm_state; - -signal pwm_fsm_data_i : std_logic_vector(15 downto 0); -signal pwm_fsm_addr : std_logic_vector(3 downto 0); -signal pwm_fsm_write : std_logic; -signal fsm_job : std_logic_vector(1 downto 0); -signal ram_fsm_data_i : std_logic_vector(7 downto 0); -signal ram_fsm_addr_i : std_logic_vector(3 downto 0); -signal ram_fsm_write_i: std_logic; - -signal enable_cfg_flash : std_logic; -signal comp_setting : std_logic_vector(15 downto 0); -signal compensate_i : signed(15 downto 0); -signal temp_calc_i : signed(27 downto 0); -signal temperature_i_s : std_logic_vector(11 downto 0); -signal comp_setting_s : std_logic_vector(15 downto 0); - -signal ffarr_data : std_logic_vector(15 downto 0); -signal ffarr_read : std_logic; - - + port ( + STDBY :IN std_logic; + OSC :OUT std_logic; + SEDSTDBY :OUT std_logic + ); + end component; + + component oddr16 is + port ( + clk: in std_logic; + clkout: out std_logic; + reset: in std_logic; + sclk: out std_logic; + dataout: in std_logic_vector(31 downto 0); + dout: out std_logic_vector(15 downto 0)); + end component; + + component spi_slave + port( + CLK : in std_logic; + SPI_CLK : in std_logic; + SPI_CS : in std_logic; + SPI_IN : in std_logic; + SPI_OUT : out std_logic; + + DATA_OUT : out std_logic_vector(15 downto 0); + REG00_IN : in std_logic_vector(15 downto 0); + REG10_IN : in std_logic_vector(15 downto 0); + REG20_IN : in std_logic_vector(15 downto 0); + REG40_IN : in std_logic_vector(15 downto 0); + + OPERATION_OUT : out std_logic_vector(3 downto 0); + CHANNEL_OUT : out std_logic_vector(7 downto 0); + WRITE_OUT : out std_logic_vector(15 downto 0); + + DEBUG_OUT : out std_logic_vector(15 downto 0) + ); + end component; + + + component flashram + port ( + DataInA: in std_logic_vector(7 downto 0); + DataInB: in std_logic_vector(7 downto 0); + AddressA: in std_logic_vector(3 downto 0); + AddressB: in std_logic_vector(3 downto 0); + ClockA: in std_logic; + ClockB: in std_logic; + ClockEnA: in std_logic; + ClockEnB: in std_logic; + WrA: in std_logic; + WrB: in std_logic; + ResetA: in std_logic; + ResetB: in std_logic; + QA: out std_logic_vector(7 downto 0); + QB: out std_logic_vector(7 downto 0) + ); + end component; + + component pll + port ( + CLKI: in std_logic; + CLKOP: out std_logic; + CLKOS: out std_logic; + LOCK: out std_logic); + end component; + + + component UFM_WB + port( + clk_i : in std_logic; + rst_n : in std_logic; + cmd : in std_logic_vector(2 downto 0); + ufm_page : in std_logic_vector(12 downto 0); + GO : in std_logic; + BUSY : out std_logic; + ERR : out std_logic; + mem_clk : out std_logic; + mem_we : out std_logic; + mem_ce : out std_logic; + mem_addr : out std_logic_vector(3 downto 0); + mem_wr_data : out std_logic_vector(7 downto 0); + mem_rd_data : in std_logic_vector(7 downto 0) + ); + end component; + + component PUR port(PUR : in std_logic); end component; + component GSR port(GSR : in std_logic); end component; + + + + attribute NOM_FREQ : string; + attribute NOM_FREQ of clk_source : label is "133.00"; + signal clk_i : std_logic; + + signal reset_i : std_logic := '1'; + signal reset_cnt : unsigned(3 downto 0) := x"0"; + signal id_data_i : std_logic_vector(15 downto 0); + signal id_addr_i : std_logic_vector(2 downto 0); + signal id_write_i: std_logic; + signal ram_write_i : std_logic; + signal ram_data_i: std_logic_vector(7 downto 0); + signal ram_data_o: std_logic_vector(7 downto 0); + signal ram_addr_i: std_logic_vector(3 downto 0); + signal temperature_i : std_logic_vector(11 downto 0); + + type ram_t is array(0 to 15) of std_logic_vector(15 downto 0); + signal ram : ram_t; + + + + signal spi_reg20_i : std_logic_vector(15 downto 0); + signal spi_reg40_i : std_logic_vector(15 downto 0); + signal spi_data_i : std_logic_vector(15 downto 0); + signal spi_operation_i : std_logic_vector(3 downto 0); + signal spi_channel_i : std_logic_vector(7 downto 0); + signal spi_write_i : std_logic_vector(15 downto 0); + signal spi_cs, spi_out : std_logic; + + signal spi_debug_i : std_logic_vector(15 downto 0); + signal last_spi_channel: std_logic_vector(7 downto 0); + + signal pll_lock : std_logic; + signal clk_26 : std_logic; + signal clk_osc : std_logic; + + signal flashram_addr_i : std_logic_vector(3 downto 0); + signal flashram_cen_i : std_logic; + signal flashram_reset : std_logic; + signal flashram_write_i: std_logic; + signal flashram_data_i : std_logic_vector(7 downto 0); + signal flashram_data_o : std_logic_vector(7 downto 0); + + signal flash_command : std_logic_vector(2 downto 0); + signal flash_page : std_logic_vector(12 downto 0); + signal flash_go : std_logic; + signal flash_busy : std_logic; + signal flash_err : std_logic; + + + + signal leds : std_logic_vector(4 downto 0) := (others => '0'); + + signal flash_go_tmp : std_logic_vector(5 downto 0); + signal flash_reset_n : std_logic; + + + signal fsm_job : std_logic_vector(1 downto 0); + signal ram_fsm_data_i : std_logic_vector(7 downto 0); + signal ram_fsm_addr_i : std_logic_vector(3 downto 0); + signal ram_fsm_write_i: std_logic; + + signal enable_cfg_flash : std_logic; + + + signal adc_csb : std_logic_vector(12 downto 1) := x"000"; + begin -THE_PLL : pll - port map( - CLKI => clk_osc, - CLKOP => clk_26, --33 - CLKOS => clk_i, --133 - LOCK => pll_lock --no lock available! - ); + THE_PLL : pll + port map( + CLKI => clk_osc, + CLKOP => clk_26, --33 + CLKOS => clk_i, --133 + LOCK => pll_lock --no lock available! + ); --------------------------------------------------------------------------- -- Clock --------------------------------------------------------------------------- -clk_source: OSCH + clk_source: OSCH -- synthesis translate_off - generic map ( NOM_FREQ => "133.00" ) + generic map ( NOM_FREQ => "133.00" ) -- synthesis translate_on - port map ( - STDBY => '0', - OSC => clk_osc, - SEDSTDBY => open - ); - ---------------------------------------------------------------------------- --- Input re-ordering ---------------------------------------------------------------------------- + port map ( + STDBY => '0', + OSC => clk_osc, + SEDSTDBY => open + ); - INP_i <= INP; - PWM <= pwm_i(16 downto 1); - --------------------------------------------------------------------------- -- SPI Interface ---------------------------------------------------------------------------- -THE_SPI_SLAVE : spi_slave - port map( - CLK => clk_i, - SPI_CLK => SPI_CLK, - SPI_CS => SPI_CS, - SPI_IN => SPI_IN, - SPI_OUT => buf_SPI_OUT, - DATA_OUT => spi_data_i, - REG00_IN => spi_reg00_i, - REG10_IN => spi_reg10_i, - REG20_IN => spi_reg20_i, - REG40_IN => spi_reg40_i, - OPERATION_OUT => spi_operation_i, - CHANNEL_OUT => spi_channel_i, - WRITE_OUT => spi_write_i, - DEBUG_OUT => spi_debug_i - ); - -SPI_OUT <= buf_SPI_OUT; - -spi_reg00_i <= pwm_data_o; -spi_reg10_i <= idram(to_integer(unsigned(spi_channel_i(2 downto 0)))); -spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o; +--------------------------------------------------------------------------- + THE_SPI_SLAVE : spi_slave + port map( + CLK => clk_i, + SPI_CLK => SPI_TRB_CLK(0), + SPI_CS => spi_cs, + SPI_IN => SPI_TRB_IN(0), + SPI_OUT => spi_out, + DATA_OUT => spi_data_i, + REG00_IN => (others => '0'), + REG10_IN => (others => '0'), + REG20_IN => spi_reg20_i, + REG40_IN => spi_reg40_i, + OPERATION_OUT => spi_operation_i, + CHANNEL_OUT => spi_channel_i, + WRITE_OUT => spi_write_i, + DEBUG_OUT => spi_debug_i + ); + + spi_cs_mux : process(SPI_TRB_CS) is + begin -- process + case SPI_TRB_CS is + when b"00" => + spi_cs <= '0'; + SPI_CONN_L_CS <= '1'; + SPI_CONN_H_CS <= '1'; + SPI_TRB_OUT(0) <= spi_out; + when b"01" => + spi_cs <= '1'; + SPI_CONN_L_CS <= '0'; + SPI_CONN_H_CS <= '1'; + SPI_TRB_OUT(0) <= SPI_CONN_L_IN; + when b"10" => + spi_cs <= '1'; + SPI_CONN_L_CS <= '1'; + SPI_CONN_H_CS <= '0'; + SPI_TRB_OUT(0) <= SPI_CONN_H_IN; + when others => + spi_cs <= '1'; + SPI_CONN_L_CS <= '1'; + SPI_CONN_H_CS <= '1'; + SPI_TRB_OUT(0) <= '0'; + end case; + end process; + + -- no multiplexing needed for these signals, I think... + SPI_CONN_L_CLK <= SPI_TRB_CLK(0); + SPI_CONN_H_CLK <= SPI_TRB_CLK(0); + SPI_CONN_L_OUT <= SPI_TRB_IN(0); + SPI_CONN_H_OUT <= SPI_TRB_IN(0); + + + + spi_reg40_i <= flash_busy & flash_err & "000000" & ram_data_o; --------------------------------------------------------------------------- -- RAM Interface ---------------------------------------------------------------------------- +--------------------------------------------------------------------------- --CFG-Flash: 0 - 5758 --UFM-Flash: 7167 - 7936 -PROC_CTRL_FLASH : process begin - wait until rising_edge(clk_i); - if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then - flash_command <= spi_data_i(15 downto 13); - if(enable_cfg_flash = '1') then - flash_page <= spi_data_i(12 downto 0); - else - flash_page <= "111" & spi_data_i(9 downto 0); - end if; - flash_go_tmp(0)<= '1'; - else - flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0'; - end if; - if flash_reset_n = '0' then - flash_go_tmp <= (others => '0'); - end if; -end process; - -PROC_CTRL_FLASH_ENABLE : process begin - wait until rising_edge(clk_i); - if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"C") then - enable_cfg_flash <= spi_data_i(0); - end if; -end process; - -flash_go <= or_all(flash_go_tmp); - - -THE_FLASH_RAM : flashram - port map( - DataInA => ram_data_i, - DataInB => flashram_data_i, - AddressA => ram_addr_i, - AddressB => flashram_addr_i, - ClockA => clk_i, - ClockB => clk_26, - ClockEnA => '1', - ClockEnB => flashram_cen_i, - WrA => ram_write_i, - WrB => flashram_write_i, - ResetA => '0', - ResetB => flashram_reset, - QA => ram_data_o, - QB => flashram_data_o - ); + PROC_CTRL_FLASH : process + begin + wait until rising_edge(clk_i); + if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"0") then + flash_command <= spi_data_i(15 downto 13); + if(enable_cfg_flash = '1') then + flash_page <= spi_data_i(12 downto 0); + else + flash_page <= "111" & spi_data_i(9 downto 0); + end if; + flash_go_tmp(0)<= '1'; + else + flash_go_tmp(5 downto 0) <= flash_go_tmp(4 downto 0) & '0'; + end if; + if flash_reset_n = '0' then + flash_go_tmp <= (others => '0'); + end if; + end process; + + PROC_CTRL_FLASH_ENABLE : process + begin + wait until rising_edge(clk_i); + if(spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"C") then + enable_cfg_flash <= spi_data_i(0); + end if; + end process; + + flash_go <= or_all(flash_go_tmp); + + + THE_FLASH_RAM : flashram + port map( + DataInA => ram_data_i, + DataInB => flashram_data_i, + AddressA => ram_addr_i, + AddressB => flashram_addr_i, + ClockA => clk_i, + ClockB => clk_26, + ClockEnA => '1', + ClockEnB => flashram_cen_i, + WrA => ram_write_i, + WrB => flashram_write_i, + ResetA => '0', + ResetB => flashram_reset, + QA => ram_data_o, + QB => flashram_data_o + ); --------------------------------------------------------------------------- -- Flash Controller ---------------------------------------------------------------------------- - -THE_FLASH : UFM_WB - port map( - clk_i => clk_26, - rst_n => flash_reset_n, - cmd => flash_command, - ufm_page => flash_page, - GO => flash_go, - BUSY => flash_busy, - ERR => flash_err, - mem_clk => open, - mem_we => flashram_write_i, - mem_ce => flashram_cen_i, - mem_addr => flashram_addr_i, - mem_wr_data => flashram_data_i, - mem_rd_data => flashram_data_o - ); - -PROC_DATA_COPY : process - variable count : integer range 0 to 31 := 0; - variable tmp : std_logic_vector(7 downto 0); -begin - wait until rising_edge(clk_i); - pwm_fsm_write <= '0'; - ram_fsm_write_i <= '0'; - case fsm_copydat is - when IDLE => - count := 0; - if spi_write_i(5) = '1' and spi_channel_i(7 downto 4) = x"1" then - fsm_copydat <= PWM_WRITE_GET_1; - ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4)); - fsm_job <= spi_channel_i(1 downto 0); - count := count + 1; - end if; - when PWM_WRITE_GET_1 => - ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4)); - count := count + 1; - fsm_copydat <= PWM_WRITE_GET_2; - when PWM_WRITE_GET_2 => - fsm_copydat <= PWM_WRITE; - tmp := ram_data_o; - when PWM_WRITE => - pwm_fsm_data_i <= tmp & ram_data_o; - pwm_fsm_write <= '1'; - pwm_fsm_addr <= fsm_job(0) & std_logic_vector(to_unsigned(count/2-1,3)); - - if(count < 15) then - fsm_copydat <= PWM_WRITE_GET_1; - else - fsm_copydat <= PWM_WAIT; - end if; - - ram_fsm_addr_i <= std_logic_vector(to_unsigned(count,4)); - count := count + 1; - - when PWM_WAIT => - fsm_copydat <= IDLE; - end case; - if onewire_reset = '1' then - fsm_copydat <= IDLE; - end if; -end process; - --------------------------------------------------------------------------- --- PWM ---------------------------------------------------------------------------- -THE_PWM_GEN : pwm_generator - port map( - CLK => clk_i, - DATA_IN => pwm_data_i, - DATA_OUT => pwm_data_o, - COMP_IN => compensate_i, - WRITE_IN => pwm_write_i, - ADDR_IN => pwm_addr_i, - PWM => pwm_i - ); - - - -PROC_PWM_DATA_MUX : process(fsm_copydat, spi_data_i, spi_write_i, spi_channel_i, - pwm_fsm_addr, pwm_fsm_data_i, pwm_fsm_write, - ram_fsm_addr_i, ram_fsm_data_i, ram_fsm_write_i) -begin - if(fsm_copydat = IDLE) then - pwm_data_i <= spi_data_i; - pwm_write_i <= spi_write_i(0); - pwm_addr_i <= spi_channel_i(3 downto 0); - ram_write_i <= spi_write_i(4); - ram_data_i <= spi_data_i(7 downto 0); - ram_addr_i <= spi_channel_i(3 downto 0); - else - pwm_data_i <= pwm_fsm_data_i; - pwm_write_i <= pwm_fsm_write; - pwm_addr_i <= pwm_fsm_addr; - ram_write_i <= ram_fsm_write_i; - ram_data_i <= ram_fsm_data_i; - ram_addr_i <= ram_fsm_addr_i; - end if; -end process; - - ---------------------------------------------------------------------------- --- Temperature Sensor ---------------------------------------------------------------------------- - -THE_ONEWIRE : trb_net_onewire - generic map( - USE_TEMPERATURE_READOUT => 1, - PARASITIC_MODE => c_NO, - CLK_PERIOD => 33 - ) - port map( - CLK => clk_26, - RESET => onewire_reset, - READOUT_ENABLE_IN => '1', - ONEWIRE => TEMP_LINE, - MONITOR_OUT => onewire_monitor, - --connection to id ram, according to memory map in TrbNetRegIO - DATA_OUT => id_data_i, - ADDR_OUT => id_addr_i, - WRITE_OUT=> id_write_i, - TEMP_OUT => temperature_i, - ID_OUT => open, - STAT => open - ); - -PROC_IDMEM : process begin - wait until rising_edge(clk_i); - if id_write_i = '1' then - idram(to_integer(unsigned(id_addr_i))) <= id_data_i; - else - idram(4) <= "0000" & temperature_i; - end if; - - if spi_write_i(1) = '1' then - onewire_reset <= spi_data_i(0); - end if; -end process; - -flash_reset_n <= not onewire_reset; + THE_FLASH : UFM_WB + port map( + clk_i => clk_26, + rst_n => flash_reset_n, + cmd => flash_command, + ufm_page => flash_page, + GO => flash_go, + BUSY => flash_busy, + ERR => flash_err, + mem_clk => open, + mem_we => flashram_write_i, + mem_ce => flashram_cen_i, + mem_addr => flashram_addr_i, + mem_wr_data => flashram_data_i, + mem_rd_data => flashram_data_o + ); + + --------------------------------------------------------------------------- -- I/O Register 0x20 ---------------------------------------------------------------------------- -THE_IO_REG_READ : process begin - wait until rising_edge(clk_i); - if spi_channel_i(4) = '0' then - case spi_channel_i(3 downto 0) is - when x"0" => spi_reg20_i <= input_enable; - when x"1" => spi_reg20_i <= inp_status; - when x"2" => spi_reg20_i <= x"0" & "000" & led_status(8) & leds(14) & leds(12) & leds(10) & leds(8) & leds(6) & leds(4) & leds(2) & leds(0) ; - when x"3" => spi_reg20_i <= x"00" & "000" & std_logic_vector(to_unsigned(inp_select,5)); - when x"4" => spi_reg20_i <= inp_invert; - when x"5" => spi_reg20_i <= inp_stretch; - when x"6" => spi_reg20_i <= comp_setting; - when x"7" => spi_reg20_i <= x"00" & discharge_disable; - when x"8" => spi_reg20_i <= x"00" & discharge_override; - when x"9" => spi_reg20_i <= x"00" & discharge_highz; - when x"a" => spi_reg20_i <= x"00" & delay_invert; - when x"f" => spi_reg20_i <= ffarr_data; - when others => null; - end case; - else - case spi_channel_i(3 downto 0) is - when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); - when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); - when x"2" => spi_reg20_i <= x"0000"; - when others => null; - end case; - end if; -end process; - -THE_IO_REG_WRITE : process begin - wait until rising_edge(clk_i); - if spi_write_i(2) = '1' then - case spi_channel_i(3 downto 0) is - when x"0" => input_enable <= spi_data_i; - when x"1" => null; - when x"2" => led_status <= spi_data_i(8 downto 0); - when x"3" => inp_select <= to_integer(unsigned(spi_data_i(4 downto 0))); - when x"4" => inp_invert <= spi_data_i; - when x"5" => inp_stretch <= spi_data_i; - when x"6" => comp_setting <= spi_data_i; - when x"7" => discharge_disable <= spi_data_i(7 downto 0); - when x"8" => discharge_override <= spi_data_i(7 downto 0); - when x"9" => discharge_highz <= spi_data_i(7 downto 0); - when x"a" => delay_invert <= spi_data_i(7 downto 0); - when others => null; - end case; - end if; -end process; - -inp_status <= INP_i when rising_edge(clk_i); -last_inp <= inp_status(15 downto 0) when rising_edge(clk_i); - -temperature_i_s <= temperature_i when rising_edge(clk_26); -comp_setting_s <= comp_setting when rising_edge(clk_26); -temp_calc_i <= signed(temperature_i_s) * signed(comp_setting_s) when rising_edge(clk_26); - -gen_comp: if TEMP_CORRECTION = 1 generate - compensate_i <= temp_calc_i(27 downto 12) when rising_edge(clk_26); -end generate; -gen_no_comp: if TEMP_CORRECTION = 0 generate - compensate_i <= (others => '0'); -end generate; - - ---------------------------------------------------------------------------- --- Delay generation ---------------------------------------------------------------------------- - - -gen_discharge : for i in 1 to 8 generate -DISCHARGE(i) <= 'Z' when discharge_highz(i) = '1' else - (DELAY_C_IN(i) and slow_input(i)) when discharge_disable(i) = '0' else - discharge_override(i) when discharge_disable(i) = '1'; - -DELAY_C_OUT(i) <= (fast_input(i) or slow_input(i)) xor delay_invert(i); -end generate; - -fast_input <= inp_gated(14) & inp_gated(12) & inp_gated(10) & inp_gated(8) & inp_gated(6) & inp_gated(4) & inp_gated(2) & inp_gated(0); -slow_input <= inp_gated(15) & inp_gated(13) & inp_gated(11) & inp_gated(9) & inp_gated(7) & inp_gated(5) & inp_gated(3) & inp_gated(1); - - ---------------------------------------------------------------------------- --- LED blinking when activity on inputs --------------------------------------------------------------------------- -PROC_TIMER : process begin - wait until rising_edge(clk_i); - timer <= timer + 1; - leds <= (last_inp xor inp_status(15 downto 0)) or leds or last_leds; - if timer = 0 then - leds <= not inp_status(15 downto 0); - last_leds <= x"0000"; - end if; -end process; + THE_IO_REG_READ : process + begin + wait until rising_edge(clk_i); + if spi_channel_i(4) = '0' then + case spi_channel_i(3 downto 0) is + when x"0" => spi_reg20_i <= x"00" & b"000" & leds; + when x"1" => spi_reg20_i <= x"0" & adc_csb_reg; + when others => null; + end case; + else + case spi_channel_i(3 downto 0) is + when x"0" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME,16)); + when x"1" => spi_reg20_i <= std_logic_vector(to_unsigned(VERSION_NUMBER_TIME/2**16,16)); + when x"2" => spi_reg20_i <= x"0000"; + when others => null; + end case; + end if; + end process; + + THE_IO_REG_WRITE : process + begin + wait until rising_edge(clk_i); + if spi_write_i(2) = '1' then + case spi_channel_i(3 downto 0) is + when x"0" => leds <= spi_data_i(4 downto 0); + when x"1" => adc_csb_reg <= spi_data_i(11 downto 0); + when others => null; + end case; + end if; + end process; --------------------------------------------------------------------------- -- Rest of the I/O --------------------------------------------------------------------------- -inp_gated <= (INP_i xor inp_invert) and not input_enable; -CON <= inp_gated or (inp_stretched and inp_stretch); - - -inp_hold <= (inp_gated or inp_hold) and not inp_hold_reg; -inp_hold_reg <= inp_hold when rising_edge(clk_i); -last_inp_hold_reg <= inp_hold_reg when rising_edge(clk_i); -inp_stretched <= inp_hold_reg or last_inp_hold_reg or inp_hold; - - - - - -SPARE_OUTPUT : process(INP_i, inp_select, inp_or, inp_long_or, inp_long_reg, last_inp_long_reg) - begin - if inp_select < 16 then - SPARE_LVDS <= INP_i(inp_select); - elsif inp_select < 24 then - SPARE_LVDS <= inp_or; - else - SPARE_LVDS <= inp_long_reg or last_inp_long_reg or inp_long_or ; - end if; - end process; - -inp_or <= or_all((INP_i xor inp_invert) and not input_enable); -inp_long_or <= (inp_or or inp_long_or) and not inp_long_reg; -inp_long_reg <= inp_long_or when rising_edge(clk_i); -last_inp_long_reg <= inp_long_reg when rising_edge(clk_i); - - -TEST_LINE <= (others => '0'); - - -gen_leds : for i in 1 to 8 generate - LED(i) <= not leds((i-1)*2) when led_status(8) = '1' else not led_status(i-1); -end generate; end architecture; - diff --git a/adc_addon/adc_addon_constraints.lpf b/adc_addon/adc_addon_constraints.lpf index ea598b7..cc28d0e 100644 --- a/adc_addon/adc_addon_constraints.lpf +++ b/adc_addon/adc_addon_constraints.lpf @@ -1,209 +1,3 @@ -BLOCK RESETPATHS ; -BLOCK ASYNCPATHS ; -BLOCK RD_DURING_WR_PATHS ; - -################################################################# -# Basic Settings -################################################################# - -SYSCONFIG MCCLK_FREQ = 133.00 JTAG_PORT = ENABLE; -FREQUENCY NET clk_i 133 MHz; -FREQUENCY NET clk_i_inferred_clock 133 MHz; -# -# FREQUENCY PORT CLK_PCLK_RIGHT 200 MHz; -# FREQUENCY PORT CLK_PCLK_LEFT 200 MHz; -# FREQUENCY PORT CLK_GPLL_RIGHT 200 MHz; -# FREQUENCY PORT CLK_GPLL_LEFT 125 MHz; - -MULTICYCLE FROM PORT "SPI_*" 20.000000 ns ; -MULTICYCLE TO PORT "SPI_*" 20.000000 ns ; - -################################################################# -# I/O -################################################################# -LOCATE COMP "CON_1" SITE "A4"; -LOCATE COMP "CON_2" SITE "A5"; -LOCATE COMP "CON_3" SITE "A3"; -LOCATE COMP "CON_4" SITE "D6"; -LOCATE COMP "CON_5" SITE "B7"; -LOCATE COMP "CON_6" SITE "F7"; -LOCATE COMP "CON_7" SITE "C8"; -LOCATE COMP "CON_8" SITE "D8"; -LOCATE COMP "CON_9" SITE "F8"; -LOCATE COMP "CON_10" SITE "B9"; -LOCATE COMP "CON_11" SITE "F9"; -LOCATE COMP "CON_12" SITE "D10"; -LOCATE COMP "CON_13" SITE "A11"; -LOCATE COMP "CON_14" SITE "B11"; -LOCATE COMP "CON_15" SITE "B13"; -LOCATE COMP "CON_16" SITE "C12"; -DEFINE PORT GROUP "CON_group" "CON*" ; -IOBUF GROUP "CON_group" IO_TYPE=LVDS25; - -LOCATE COMP "INP_1" SITE "T2"; #FAST1 -LOCATE COMP "INP_2" SITE "T3"; #SLOW1 -LOCATE COMP "INP_3" SITE "P4"; #FAST2 -LOCATE COMP "INP_4" SITE "R5"; #SLOW2 -LOCATE COMP "INP_5" SITE "T5"; #FAST3 -LOCATE COMP "INP_6" SITE "P6"; #SLOW3 -LOCATE COMP "INP_7" SITE "R7"; #FAST4 -LOCATE COMP "INP_8" SITE "N6"; #SLOW4 -LOCATE COMP "INP_9" SITE "M6"; #FAST5 -LOCATE COMP "INP_10" SITE "M7"; #SLOW5 -LOCATE COMP "INP_11" SITE "T7"; #FAST6 -LOCATE COMP "INP_12" SITE "P8"; #SLOW6 -LOCATE COMP "INP_13" SITE "N8"; #FAST7 -LOCATE COMP "INP_14" SITE "T9"; #SLOW7 -LOCATE COMP "INP_15" SITE "R9"; #FAST8 -LOCATE COMP "INP_16" SITE "M8"; #SLOW8 -DEFINE PORT GROUP "INP_group" "INP*" ; -IOBUF GROUP "INP_group" IO_TYPE=LVDS25; - - -LOCATE COMP "PWM_1" SITE "R1"; -LOCATE COMP "PWM_2" SITE "P1"; -LOCATE COMP "PWM_3" SITE "N3"; -LOCATE COMP "PWM_4" SITE "N1"; -LOCATE COMP "PWM_5" SITE "M3"; -LOCATE COMP "PWM_6" SITE "M1"; -LOCATE COMP "PWM_7" SITE "L1"; -LOCATE COMP "PWM_8" SITE "K4"; -LOCATE COMP "PWM_9" SITE "H6"; -LOCATE COMP "PWM_10" SITE "G2"; -LOCATE COMP "PWM_11" SITE "F1"; -LOCATE COMP "PWM_12" SITE "E2"; -LOCATE COMP "PWM_13" SITE "E1"; -LOCATE COMP "PWM_14" SITE "D1"; -LOCATE COMP "PWM_15" SITE "C2"; -LOCATE COMP "PWM_16" SITE "B1"; -DEFINE PORT GROUP "PWM_group" "PWM*" ; -IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW; - - -LOCATE COMP "DISCHARGE_1" SITE "G11"; -LOCATE COMP "DISCHARGE_2" SITE "H12"; -LOCATE COMP "DISCHARGE_3" SITE "J12"; -LOCATE COMP "DISCHARGE_4" SITE "H13"; -LOCATE COMP "DISCHARGE_5" SITE "H14"; -LOCATE COMP "DISCHARGE_6" SITE "H15"; -LOCATE COMP "DISCHARGE_7" SITE "H16"; -LOCATE COMP "DISCHARGE_8" SITE "G16"; -DEFINE PORT GROUP "DISCHARGE_group" "DISCHARGE*" ; -IOBUF GROUP "DISCHARGE_group" IO_TYPE=LVCMOS33 DRIVE=12 SLEWRATE=SLOW; - - -LOCATE COMP "LED_1" SITE "G1"; -LOCATE COMP "LED_2" SITE "H2"; -LOCATE COMP "LED_3" SITE "H4"; -LOCATE COMP "LED_4" SITE "J6"; -LOCATE COMP "LED_5" SITE "H3"; -LOCATE COMP "LED_6" SITE "H1"; -LOCATE COMP "LED_7" SITE "J1"; -LOCATE COMP "LED_8" SITE "J3"; -DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW; - - -LOCATE COMP "TEST_LINE_0" SITE "F14"; -LOCATE COMP "TEST_LINE_1" SITE "F16"; -LOCATE COMP "TEST_LINE_2" SITE "F15"; -LOCATE COMP "TEST_LINE_3" SITE "E16"; -LOCATE COMP "TEST_LINE_4" SITE "E15"; -LOCATE COMP "TEST_LINE_5" SITE "D16"; -LOCATE COMP "TEST_LINE_6" SITE "D15"; -LOCATE COMP "TEST_LINE_7" SITE "C16"; -LOCATE COMP "TEST_LINE_8" SITE "C15"; -LOCATE COMP "TEST_LINE_9" SITE "B16"; -LOCATE COMP "TEST_LINE_10" SITE "E14"; -LOCATE COMP "TEST_LINE_11" SITE "D14"; -LOCATE COMP "TEST_LINE_12" SITE "F13"; -LOCATE COMP "TEST_LINE_13" SITE "G12"; -DEFINE PORT GROUP "TEST_group" "TEST*" ; -IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS33 DRIVE=8; - - -LOCATE COMP "SPI_CLK" SITE "T15"; -LOCATE COMP "SPI_CS" SITE "P12"; -LOCATE COMP "SPI_IN" SITE "R12"; -LOCATE COMP "SPI_OUT" SITE "B14"; - -IOBUF PORT "SPI_CLK" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "SPI_CS" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "SPI_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "SPI_OUT" IO_TYPE=LVDS25; - -LOCATE COMP "TEMP_LINE" SITE "L12"; -IOBUF PORT "TEMP_LINE" IO_TYPE=LVCMOS33 PULLMODE=UP; - -LOCATE COMP "SPARE_LVDS" SITE "C4"; -IOBUF PORT "SPARE_LVDS" IO_TYPE=LVDS25; - - -LOCATE COMP "DELAY_C_IN_8" SITE "G14"; #"DL_BR_08_C_0" -LOCATE COMP "DELAY_C_OUT_8" SITE "G15"; #"DL_BR_08_C_1" -LOCATE COMP "DELAY_C_IN_7" SITE "J14"; #"DL_BR_10_C_0" -LOCATE COMP "DELAY_C_OUT_7" SITE "J16"; #"DL_BR_10_C_1" -LOCATE COMP "DELAY_C_IN_6" SITE "J15"; #"DL_BR_13_C_0" -LOCATE COMP "DELAY_C_OUT_6" SITE "K16"; #"DL_BR_13_C_1" -LOCATE COMP "DELAY_C_IN_5" SITE "L14"; #"DL_BR_15_C_0" -LOCATE COMP "DELAY_C_OUT_5" SITE "L16"; #"DL_BR_15_C_1" -LOCATE COMP "DELAY_C_IN_4" SITE "L15"; #"DL_BR_16_C_0" -LOCATE COMP "DELAY_C_OUT_4" SITE "M16"; #"DL_BR_16_C_1" -LOCATE COMP "DELAY_C_IN_3" SITE "N15"; #"DL_BR_18_C_2" -LOCATE COMP "DELAY_C_OUT_3" SITE "P16"; #"DL_BR_18_C_3" -LOCATE COMP "DELAY_C_IN_2" SITE "N14"; #"DL_BR_19_C_0" -LOCATE COMP "DELAY_C_OUT_2" SITE "N16"; #"DL_BR_19_C_1" -LOCATE COMP "DELAY_C_IN_1" SITE "P15"; #"DL_BR_20_C_0" -LOCATE COMP "DELAY_C_OUT_1" SITE "R16"; #"DL_BR_20_C_1" -DEFINE PORT GROUP "DELAY_C_OUT_group" "DELAY_C_OUT*" ; -IOBUF GROUP "DELAY_C_OUT_group" IO_TYPE=LVCMOS33 DRIVE=24 PULLMODE=DOWN; - -DEFINE PORT GROUP "DELAY_C_IN_group" "DELAY_C_IN*" ; -IOBUF GROUP "DELAY_C_IN_group" IO_TYPE=LVCMOS33 ; - - - - -LOCATE COMP "DELAY_R_IN_6" SITE "F12"; #"DL_BR_06_0" -LOCATE COMP "DELAY_R_OUT_6" SITE "G13"; #"DL_BR_06_1" -LOCATE COMP "DELAY_R_IN_5" SITE "H11"; #"DL_BR_13_2" -LOCATE COMP "DELAY_R_OUT_5" SITE "J13"; #"DL_BR_13_3" -LOCATE COMP "DELAY_R_IN_4" SITE "K14"; #"DL_BR_14_0" -LOCATE COMP "DELAY_R_OUT_4" SITE "K15"; #"DL_BR_14_1" -LOCATE COMP "DELAY_R_IN_3" SITE "K12"; #"DL_BR_15_2" -LOCATE COMP "DELAY_R_OUT_3" SITE "K13"; #"DL_BR_15_3" -LOCATE COMP "DELAY_R_IN_2" SITE "K11"; #"DL_BR_16_2" -LOCATE COMP "DELAY_R_OUT_2" SITE "L13"; #"DL_BR_16_3" -LOCATE COMP "DELAY_R_IN_1" SITE "M14"; #"DL_BR_18_0" -LOCATE COMP "DELAY_R_OUT_1" SITE "M15"; #"DL_BR_18_1" - -LOCATE COMP "DELAY_L_IN_5" SITE "F4"; #"DL_BL_06_0" -LOCATE COMP "DELAY_L_OUT_5" SITE "G6"; #"DL_BL_06_1" -LOCATE COMP "DELAY_L_IN_4" SITE "J2"; #"DL_BL_13_0" -LOCATE COMP "DELAY_L_OUT_4" SITE "K1"; #"DL_BL_13_1" -LOCATE COMP "DELAY_L_IN_3" SITE "H5"; #"DL_BL_13_2" -LOCATE COMP "DELAY_L_OUT_3" SITE "J4"; #"DL_BL_13_3" -LOCATE COMP "DELAY_L_IN_2" SITE "K2"; #"DL_BL_14_0" -LOCATE COMP "DELAY_L_OUT_2" SITE "K3"; #"DL_BL_14_1" -LOCATE COMP "DELAY_L_IN_1" SITE "J5"; #"DL_BL_14_2" -LOCATE COMP "DELAY_L_OUT_1" SITE "K6"; #"DL_BL_14_3" - -LOCATE COMP "DELAY_B_IN_5" SITE "M10"; #"DL_BB_24_0" -LOCATE COMP "DELAY_B_OUT_5" SITE "N11"; #"DL_BB_24_1" -LOCATE COMP "DELAY_B_IN_4" SITE "P11"; #"DL_BB_24_2" -LOCATE COMP "DELAY_B_OUT_4" SITE "T11"; #"DL_BB_24_3" -LOCATE COMP "DELAY_B_IN_3" SITE "M11"; #"DL_BB_23_0" -LOCATE COMP "DELAY_B_OUT_3" SITE "N10"; #"DL_BB_23_1" -LOCATE COMP "DELAY_B_IN_2" SITE "P10"; #"DL_BB_23_2" -LOCATE COMP "DELAY_B_OUT_2" SITE "R10"; #"DL_BB_23_3" -LOCATE COMP "DELAY_B_IN_1" SITE "L10"; #"DL_BB_21_0" -LOCATE COMP "DELAY_B_OUT_1" SITE "M9"; #"DL_BB_21_1" - -DEFINE PORT GROUP "DELAY_C_OUT_group" "DELAY_*_OUT*" ; -IOBUF GROUP "DELAY_C_OUT_group" IO_TYPE=LVCMOS33 DRIVE=4 PULLMODE=DOWN; - -DEFINE PORT GROUP "DELAY_C_IN_group" "DELAY_*_IN*" ; -IOBUF GROUP "DELAY_C_IN_group" IO_TYPE=LVCMOS33 ; FREQUENCY NET clk_i_c 133 MHz; diff --git a/adc_addon/compile_adc_addon_gsi.pl b/adc_addon/compile_adc_addon_gsi.pl index cb8606e..c0be560 100755 --- a/adc_addon/compile_adc_addon_gsi.pl +++ b/adc_addon/compile_adc_addon_gsi.pl @@ -49,7 +49,7 @@ $ENV{'LM_LICENSE_FILE'}=$lm_license_file_for_synplify; my $FAMILYNAME="MACHXO2"; my $DEVICENAME="LCMXO2-4000HC"; -my $PACKAGE="FTBGA256"; +my $PACKAGE="CSBGA132"; my $SPEEDGRADE="6"; my $WORKDIR = "workdir"; diff --git a/pinout/adc_addon.lpf b/pinout/adc_addon.lpf index 89841ba..0c340f4 100644 --- a/pinout/adc_addon.lpf +++ b/pinout/adc_addon.lpf @@ -21,186 +21,12 @@ MULTICYCLE TO PORT "SPI_*" 20.000000 ns ; ################################################################# # I/O ################################################################# -LOCATE COMP "CON_1" SITE "A4"; -LOCATE COMP "CON_2" SITE "A5"; -LOCATE COMP "CON_3" SITE "A3"; -LOCATE COMP "CON_4" SITE "D6"; -LOCATE COMP "CON_5" SITE "B7"; -LOCATE COMP "CON_6" SITE "F7"; -LOCATE COMP "CON_7" SITE "C8"; -LOCATE COMP "CON_8" SITE "D8"; -LOCATE COMP "CON_9" SITE "F8"; -LOCATE COMP "CON_10" SITE "B9"; -LOCATE COMP "CON_11" SITE "F9"; -LOCATE COMP "CON_12" SITE "D10"; -LOCATE COMP "CON_13" SITE "A11"; -LOCATE COMP "CON_14" SITE "B11"; -LOCATE COMP "CON_15" SITE "B13"; -LOCATE COMP "CON_16" SITE "C12"; -DEFINE PORT GROUP "CON_group" "CON*" ; -IOBUF GROUP "CON_group" IO_TYPE=LVDS25; -LOCATE COMP "INP_1" SITE "T2"; #FAST1 -LOCATE COMP "INP_2" SITE "T3"; #SLOW1 -LOCATE COMP "INP_3" SITE "P4"; #FAST2 -LOCATE COMP "INP_4" SITE "R5"; #SLOW2 -LOCATE COMP "INP_5" SITE "T5"; #FAST3 -LOCATE COMP "INP_6" SITE "P6"; #SLOW3 -LOCATE COMP "INP_7" SITE "R7"; #FAST4 -LOCATE COMP "INP_8" SITE "N6"; #SLOW4 -LOCATE COMP "INP_9" SITE "M6"; #FAST5 -LOCATE COMP "INP_10" SITE "M7"; #SLOW5 -LOCATE COMP "INP_11" SITE "T7"; #FAST6 -LOCATE COMP "INP_12" SITE "P8"; #SLOW6 -LOCATE COMP "INP_13" SITE "N8"; #FAST7 -LOCATE COMP "INP_14" SITE "T9"; #SLOW7 -LOCATE COMP "INP_15" SITE "R9"; #FAST8 -LOCATE COMP "INP_16" SITE "M8"; #SLOW8 -DEFINE PORT GROUP "INP_group" "INP*" ; -IOBUF GROUP "INP_group" IO_TYPE=LVDS25; +LOCATE COMP "LED_WHITE" SITE "D1"; +LOCATE COMP "LED_RED" SITE "E1"; +LOCATE COMP "LED_GREEN" SITE "E2"; +LOCATE COMP "LED_YELLOW" SITE "E3"; +LOCATE COMP "LED_ORANGE" SITE "F2"; +DEFINE PORT GROUP "LED_group" "LED*"; +IOBUF GROUP "LED_group" IO_TYPE=LVCMOS33; - -LOCATE COMP "PWM_1" SITE "R1"; -LOCATE COMP "PWM_2" SITE "P1"; -LOCATE COMP "PWM_3" SITE "N3"; -LOCATE COMP "PWM_4" SITE "N1"; -LOCATE COMP "PWM_5" SITE "M3"; -LOCATE COMP "PWM_6" SITE "M1"; -LOCATE COMP "PWM_7" SITE "L1"; -LOCATE COMP "PWM_8" SITE "K4"; -LOCATE COMP "PWM_9" SITE "H6"; -LOCATE COMP "PWM_10" SITE "G2"; -LOCATE COMP "PWM_11" SITE "F1"; -LOCATE COMP "PWM_12" SITE "E2"; -LOCATE COMP "PWM_13" SITE "E1"; -LOCATE COMP "PWM_14" SITE "D1"; -LOCATE COMP "PWM_15" SITE "C2"; -LOCATE COMP "PWM_16" SITE "B1"; -DEFINE PORT GROUP "PWM_group" "PWM*" ; -IOBUF GROUP "PWM_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW; - - -LOCATE COMP "DISCHARGE_1" SITE "G11"; -LOCATE COMP "DISCHARGE_2" SITE "H12"; -LOCATE COMP "DISCHARGE_3" SITE "J12"; -LOCATE COMP "DISCHARGE_4" SITE "H13"; -LOCATE COMP "DISCHARGE_5" SITE "H14"; -LOCATE COMP "DISCHARGE_6" SITE "H15"; -LOCATE COMP "DISCHARGE_7" SITE "H16"; -LOCATE COMP "DISCHARGE_8" SITE "G16"; -DEFINE PORT GROUP "DISCHARGE_group" "DISCHARGE*" ; -IOBUF GROUP "DISCHARGE_group" IO_TYPE=LVCMOS33 DRIVE=12 SLEWRATE=SLOW; - - -LOCATE COMP "LED_1" SITE "G1"; -LOCATE COMP "LED_2" SITE "H2"; -LOCATE COMP "LED_3" SITE "H4"; -LOCATE COMP "LED_4" SITE "J6"; -LOCATE COMP "LED_5" SITE "H3"; -LOCATE COMP "LED_6" SITE "H1"; -LOCATE COMP "LED_7" SITE "J1"; -LOCATE COMP "LED_8" SITE "J3"; -DEFINE PORT GROUP "LED_group" "LED*" ; -IOBUF GROUP "LED_group" IO_TYPE=LVCMOS33 DRIVE=4 SLEWRATE=SLOW; - - -LOCATE COMP "TEST_LINE_0" SITE "F14"; -LOCATE COMP "TEST_LINE_1" SITE "F16"; -LOCATE COMP "TEST_LINE_2" SITE "F15"; -LOCATE COMP "TEST_LINE_3" SITE "E16"; -LOCATE COMP "TEST_LINE_4" SITE "E15"; -LOCATE COMP "TEST_LINE_5" SITE "D16"; -LOCATE COMP "TEST_LINE_6" SITE "D15"; -LOCATE COMP "TEST_LINE_7" SITE "C16"; -LOCATE COMP "TEST_LINE_8" SITE "C15"; -LOCATE COMP "TEST_LINE_9" SITE "B16"; -LOCATE COMP "TEST_LINE_10" SITE "E14"; -LOCATE COMP "TEST_LINE_11" SITE "D14"; -LOCATE COMP "TEST_LINE_12" SITE "F13"; -LOCATE COMP "TEST_LINE_13" SITE "G12"; -DEFINE PORT GROUP "TEST_group" "TEST*" ; -IOBUF GROUP "TEST_group" IO_TYPE=LVCMOS33 DRIVE=8; - - -LOCATE COMP "SPI_CLK" SITE "T15"; -LOCATE COMP "SPI_CS" SITE "P12"; -LOCATE COMP "SPI_IN" SITE "R12"; -LOCATE COMP "SPI_OUT" SITE "B14"; - -IOBUF PORT "SPI_CLK" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "SPI_CS" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "SPI_IN" IO_TYPE=LVDS25 DIFFRESISTOR=100; -IOBUF PORT "SPI_OUT" IO_TYPE=LVDS25; - -LOCATE COMP "TEMP_LINE" SITE "L12"; -IOBUF PORT "TEMP_LINE" IO_TYPE=LVCMOS33 PULLMODE=UP; - -LOCATE COMP "SPARE_LVDS" SITE "C4"; -IOBUF PORT "SPARE_LVDS" IO_TYPE=LVDS25; - - -LOCATE COMP "DELAY_C_IN_8" SITE "G14"; #"DL_BR_08_C_0" -LOCATE COMP "DELAY_C_OUT_8" SITE "G15"; #"DL_BR_08_C_1" -LOCATE COMP "DELAY_C_IN_7" SITE "J14"; #"DL_BR_10_C_0" -LOCATE COMP "DELAY_C_OUT_7" SITE "J16"; #"DL_BR_10_C_1" -LOCATE COMP "DELAY_C_IN_6" SITE "J15"; #"DL_BR_13_C_0" -LOCATE COMP "DELAY_C_OUT_6" SITE "K16"; #"DL_BR_13_C_1" -LOCATE COMP "DELAY_C_IN_5" SITE "L14"; #"DL_BR_15_C_0" -LOCATE COMP "DELAY_C_OUT_5" SITE "L16"; #"DL_BR_15_C_1" -LOCATE COMP "DELAY_C_IN_4" SITE "L15"; #"DL_BR_16_C_0" -LOCATE COMP "DELAY_C_OUT_4" SITE "M16"; #"DL_BR_16_C_1" -LOCATE COMP "DELAY_C_IN_3" SITE "N15"; #"DL_BR_18_C_2" -LOCATE COMP "DELAY_C_OUT_3" SITE "P16"; #"DL_BR_18_C_3" -LOCATE COMP "DELAY_C_IN_2" SITE "N14"; #"DL_BR_19_C_0" -LOCATE COMP "DELAY_C_OUT_2" SITE "N16"; #"DL_BR_19_C_1" -LOCATE COMP "DELAY_C_IN_1" SITE "P15"; #"DL_BR_20_C_0" -LOCATE COMP "DELAY_C_OUT_1" SITE "R16"; #"DL_BR_20_C_1" -DEFINE PORT GROUP "DELAY_C_OUT_group" "DELAY_C_OUT*" ; -IOBUF GROUP "DELAY_C_OUT_group" IO_TYPE=LVCMOS33 DRIVE=24 PULLMODE=DOWN; - -DEFINE PORT GROUP "DELAY_C_IN_group" "DELAY_C_IN*" ; -IOBUF GROUP "DELAY_C_IN_group" IO_TYPE=LVCMOS33 ; - - - - -LOCATE COMP "DELAY_R_IN_6" SITE "F12"; #"DL_BR_06_0" -LOCATE COMP "DELAY_R_OUT_6" SITE "G13"; #"DL_BR_06_1" -LOCATE COMP "DELAY_R_IN_5" SITE "H11"; #"DL_BR_13_2" -LOCATE COMP "DELAY_R_OUT_5" SITE "J13"; #"DL_BR_13_3" -LOCATE COMP "DELAY_R_IN_4" SITE "K14"; #"DL_BR_14_0" -LOCATE COMP "DELAY_R_OUT_4" SITE "K15"; #"DL_BR_14_1" -LOCATE COMP "DELAY_R_IN_3" SITE "K12"; #"DL_BR_15_2" -LOCATE COMP "DELAY_R_OUT_3" SITE "K13"; #"DL_BR_15_3" -LOCATE COMP "DELAY_R_IN_2" SITE "K11"; #"DL_BR_16_2" -LOCATE COMP "DELAY_R_OUT_2" SITE "L13"; #"DL_BR_16_3" -LOCATE COMP "DELAY_R_IN_1" SITE "M14"; #"DL_BR_18_0" -LOCATE COMP "DELAY_R_OUT_1" SITE "M15"; #"DL_BR_18_1" - -LOCATE COMP "DELAY_L_IN_5" SITE "F4"; #"DL_BL_06_0" -LOCATE COMP "DELAY_L_OUT_5" SITE "G6"; #"DL_BL_06_1" -LOCATE COMP "DELAY_L_IN_4" SITE "J2"; #"DL_BL_13_0" -LOCATE COMP "DELAY_L_OUT_4" SITE "K1"; #"DL_BL_13_1" -LOCATE COMP "DELAY_L_IN_3" SITE "H5"; #"DL_BL_13_2" -LOCATE COMP "DELAY_L_OUT_3" SITE "J4"; #"DL_BL_13_3" -LOCATE COMP "DELAY_L_IN_2" SITE "K2"; #"DL_BL_14_0" -LOCATE COMP "DELAY_L_OUT_2" SITE "K3"; #"DL_BL_14_1" -LOCATE COMP "DELAY_L_IN_1" SITE "J5"; #"DL_BL_14_2" -LOCATE COMP "DELAY_L_OUT_1" SITE "K6"; #"DL_BL_14_3" - -LOCATE COMP "DELAY_B_IN_5" SITE "M10"; #"DL_BB_24_0" -LOCATE COMP "DELAY_B_OUT_5" SITE "N11"; #"DL_BB_24_1" -LOCATE COMP "DELAY_B_IN_4" SITE "P11"; #"DL_BB_24_2" -LOCATE COMP "DELAY_B_OUT_4" SITE "T11"; #"DL_BB_24_3" -LOCATE COMP "DELAY_B_IN_3" SITE "M11"; #"DL_BB_23_0" -LOCATE COMP "DELAY_B_OUT_3" SITE "N10"; #"DL_BB_23_1" -LOCATE COMP "DELAY_B_IN_2" SITE "P10"; #"DL_BB_23_2" -LOCATE COMP "DELAY_B_OUT_2" SITE "R10"; #"DL_BB_23_3" -LOCATE COMP "DELAY_B_IN_1" SITE "L10"; #"DL_BB_21_0" -LOCATE COMP "DELAY_B_OUT_1" SITE "M9"; #"DL_BB_21_1" - -DEFINE PORT GROUP "DELAY_C_OUT_group" "DELAY_*_OUT*" ; -IOBUF GROUP "DELAY_C_OUT_group" IO_TYPE=LVCMOS33 DRIVE=4 PULLMODE=DOWN; - -DEFINE PORT GROUP "DELAY_C_IN_group" "DELAY_*_IN*" ; -IOBUF GROUP "DELAY_C_IN_group" IO_TYPE=LVCMOS33 ; -- 2.43.0