From 54cabb7d3470d61d58aafc4fce439973e169fe00 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Fri, 22 Dec 2017 17:07:11 +0100 Subject: [PATCH] Update PLL200-200 feedback for less skew --- cores/pll_in200_out200.ipx | 8 ++++---- cores/pll_in200_out200.lpc | 8 ++++---- cores/pll_in200_out200.vhd | 11 ++++++----- cts/config.vhd | 4 ++-- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/cores/pll_in200_out200.ipx b/cores/pll_in200_out200.ipx index 72bd5a3..1a04856 100644 --- a/cores/pll_in200_out200.ipx +++ b/cores/pll_in200_out200.ipx @@ -1,8 +1,8 @@ - + - - - + + + diff --git a/cores/pll_in200_out200.lpc b/cores/pll_in200_out200.lpc index 4440411..9261469 100644 --- a/cores/pll_in200_out200.lpc +++ b/cores/pll_in200_out200.lpc @@ -16,8 +16,8 @@ CoreRevision=5.8 ModuleName=pll_in200_out200 SourceFormat=VHDL ParameterFileVersion=1.0 -Date=11/08/2017 -Time=16:20:47 +Date=12/18/2017 +Time=16:27:33 [Parameters] Verilog=0 @@ -38,7 +38,7 @@ OP_Tol=0.0 OFrq=200.000000 DutyTrimP=Rising DelayMultP=0 -fb_mode=CLKOP +fb_mode=Internal Mult=1 Phase=0.0 Duty=8 @@ -66,4 +66,4 @@ ClkOKBp=0 enClkOK2=0 [Command] -cmd_line= -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw +cmd_line= -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw diff --git a/cores/pll_in200_out200.vhd b/cores/pll_in200_out200.vhd index 030239e..f576e91 100644 --- a/cores/pll_in200_out200.vhd +++ b/cores/pll_in200_out200.vhd @@ -1,8 +1,8 @@ -- VHDL netlist generated by SCUBA Diamond (64-bit) 3.9.1.119 -- Module Version: 5.7 ---/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode CLOCKTREE -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw +--/d/jspc29/lattice/diamond/3.9_x64/ispfpga/bin/lin64/scuba -w -n pll_in200_out200 -lang vhdl -synth synplify -arch ep5c00 -type pll -fin 200 -phase_cntl STATIC -bypasss -fclkop 200 -fclkop_tol 0.0 -fb_mode INTERNAL -phaseadj 0.0 -duty 8 -fclkok 100 -fclkok_tol 0.0 -clkoki 0 -norst -noclkok2 -bw --- Wed Nov 8 16:20:47 2017 +-- Mon Dec 18 16:27:33 2017 library IEEE; use IEEE.std_logic_1164.all; @@ -25,6 +25,7 @@ architecture Structure of pll_in200_out200 is -- internal signal declarations signal CLKOS_t: std_logic; signal CLKOP_t: std_logic; + signal CLKFB_t: std_logic; signal scuba_vlo: std_logic; -- local component declarations @@ -70,21 +71,21 @@ begin port map (Z=>scuba_vlo); PLLInst_0: EHXPLLF - generic map (FEEDBK_PATH=> "CLKOP", CLKOK_BYPASS=> "DISABLED", + generic map (FEEDBK_PATH=> "INTERNAL", CLKOK_BYPASS=> "DISABLED", CLKOS_BYPASS=> "ENABLED", CLKOP_BYPASS=> "DISABLED", CLKOK_INPUT=> "CLKOP", DELAY_PWD=> "DISABLED", DELAY_VAL=> 0, CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "RISING", CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "RISING", PHASE_DELAY_CNTL=> "STATIC", DUTY=> 8, PHASEADJ=> "0.0", CLKOK_DIV=> 2, CLKOP_DIV=> 4, CLKFB_DIV=> 1, CLKI_DIV=> 1, FIN=> "200.000000") - port map (CLKI=>CLK, CLKFB=>CLKOP_t, RST=>scuba_vlo, + port map (CLKI=>CLK, CLKFB=>CLKFB_t, RST=>scuba_vlo, RSTK=>scuba_vlo, WRDEL=>scuba_vlo, DRPAI3=>scuba_vlo, DRPAI2=>scuba_vlo, DRPAI1=>scuba_vlo, DRPAI0=>scuba_vlo, DFPAI3=>scuba_vlo, DFPAI2=>scuba_vlo, DFPAI1=>scuba_vlo, DFPAI0=>scuba_vlo, FDA3=>scuba_vlo, FDA2=>scuba_vlo, FDA1=>scuba_vlo, FDA0=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>CLKOS_t, CLKOK=>CLKOK, CLKOK2=>open, LOCK=>LOCK, - CLKINTFB=>open); + CLKINTFB=>CLKFB_t); CLKOS <= CLKOS_t; CLKOP <= CLKOP_t; diff --git a/cts/config.vhd b/cts/config.vhd index 8a4c63b..544db10 100644 --- a/cts/config.vhd +++ b/cts/config.vhd @@ -49,8 +49,8 @@ package config is -- 0: KEL on board -- 1: Canadian constant NUM_TDC_MODULES : integer range 1 to 4 := 1; -- number of tdc modules to implement - constant NUM_TDC_CHANNELS : integer range 1 to 65 := 9; -- number of tdc channels per module - constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 3; --the nearest power of two, for convenience reasons + constant NUM_TDC_CHANNELS : integer range 1 to 65 := 11; -- number of tdc channels per module + constant NUM_TDC_CHANNELS_POWER2 : integer range 0 to 6 := 4; --the nearest power of two, for convenience reasons constant DOUBLE_EDGE_TYPE : integer range 0 to 3 := 3; --double edge type: 0, 1, 2, 3 -- 0: single edge only, -- 1: same channel, -- 2.43.0