From 54d1c41641438786cdd18299e94548b61e79cd44 Mon Sep 17 00:00:00 2001 From: Andreas Neiser Date: Mon, 9 Mar 2015 08:19:31 +0100 Subject: [PATCH] Multicycle for debug state signal --- ADC/trb3_periph_adc_constraints.lpf | 1 + 1 file changed, 1 insertion(+) diff --git a/ADC/trb3_periph_adc_constraints.lpf b/ADC/trb3_periph_adc_constraints.lpf index 6d7446d..b29b186 100644 --- a/ADC/trb3_periph_adc_constraints.lpf +++ b/ADC/trb3_periph_adc_constraints.lpf @@ -93,6 +93,7 @@ USE PRIMARY NET "CLK_PCLK_RIGHT_c"; MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/CONF_adc*" 4 X; MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_sys*" TO CELL "gen_reallogic*THE_ADC/gen_readout_cfd*gen_processors*THE_ADC_PROC/busy_in_adc*" 2 X; +MULTICYCLE FROM CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_q_*" TO CELL "gen_reallogic*THE_ADC/THE_ADC_*/state_qq_*" 2 X; # we define everything doubled to make it work with all lattice/synplify versions # due to _ vs . notation of generate statements args... -- 2.43.0