From 5565fc9e81f4a9a9686dc74ea0ad897e111ece0c Mon Sep 17 00:00:00 2001 From: Adrian Weber Date: Mon, 1 Feb 2021 15:55:05 +0100 Subject: [PATCH] Increase number of connected boards for calib from 12 to 16. New feature: bit 20 of config register Select or deselect the calibration of channel 0 of local TDC (e.g. on combiner in CBM RICH) only with trigger 0xD. This is needed as the trigger signal is correlated to the on board clock --- combiner_cts/code_EBR/Calibration.vhd | 44 ++++++++++++++++----------- combiner_cts/code_EBR/read_cnt.vhd | 40 ++++++++++++++++++++---- 2 files changed, 60 insertions(+), 24 deletions(-) diff --git a/combiner_cts/code_EBR/Calibration.vhd b/combiner_cts/code_EBR/Calibration.vhd index 77a04c3..5870c2f 100644 --- a/combiner_cts/code_EBR/Calibration.vhd +++ b/combiner_cts/code_EBR/Calibration.vhd @@ -23,22 +23,23 @@ entity TDC_Calibration is USE_DATA_FINISHED : integer range 0 to 1 := c_NO; USE_BUSY_RELEASE : integer range 0 to 1 := c_NO ); port ( - CLK : in std_logic; - RESET : in std_logic; - DIN : in std_logic_vector(31 downto 0); - DIN_TYPE : in std_logic_vector( 3 downto 0); - DIN_READY : in std_logic; - DIN_STAT : in std_logic_vector((31*IS_COMBINER) downto 0); - FPGA_in : in std_logic_vector(15 downto 0); - TRIGG_TYPE : in std_logic_vector( 3 downto 0); - DOUT : out std_logic_vector(31 downto 0); - DOUT_TYPE : out std_logic_vector( 3 downto 0); - DOUT_READY : out std_logic; - DOUT_STAT : out std_logic_vector((31*IS_COMBINER) downto 0); - BUS_RX : in CTRLBUS_RX; - BUS_TX : out CTRLBUS_TX; - DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); - DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) + CLK : in std_logic; + RESET : in std_logic; + DIN : in std_logic_vector(31 downto 0); + DIN_TYPE : in std_logic_vector( 3 downto 0); + DIN_READY : in std_logic; + DIN_STAT : in std_logic_vector((31*IS_COMBINER) downto 0); + FPGA_in : in std_logic_vector(15 downto 0); + TRIGG_TYPE : in std_logic_vector( 3 downto 0); + MY_ADDRESS_IN : in std_logic_vector(15 downto 0); + DOUT : out std_logic_vector(31 downto 0); + DOUT_TYPE : out std_logic_vector( 3 downto 0); + DOUT_READY : out std_logic; + DOUT_STAT : out std_logic_vector((31*IS_COMBINER) downto 0); + BUS_RX : in CTRLBUS_RX; + BUS_TX : out CTRLBUS_TX; + DIN_info : in std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0); + DOUT_info : out std_logic_vector(( 31*USE_STAT_BITS + USE_DATA_WRITE + USE_DATA_FINISHED + USE_BUSY_RELEASE) downto 0) ); end TDC_Calibration; @@ -141,6 +142,7 @@ architecture TDC_Calibration_arch of TDC_Calibration is signal BUS_Trig_type : std_logic_vector( 3 downto 0):="0000"; signal BUS_stop_LimitGen_ch0 : std_logic := '0'; signal BUS_Trig_type_ch0 : std_logic_vector( 3 downto 0):="0000"; + signal BUS_locCh0_only0D : std_logic := '0'; -- local TDC channel0 should only gen. Limits with 0xD signal stop_Limits_r : std_logic := '0'; signal stp_Lmt_read_cnt : std_logic := '0'; @@ -220,6 +222,7 @@ begin elsif BUS_RX.addr(11 downto 0) >= x"000" and BUS_RX.addr(11 downto 0) < x"010" then --standard debugg case BUS_RX.addr(11 downto 0) is when x"000" => + BUS_locCh0_only0D <= BUS_RX.data(20); BUS_Trig_type_ch0 <= BUS_RX.data(19 downto 16); BUS_stop_LimitGen_ch0 <= BUS_RX.data(12); BUS_Trig_type <= BUS_RX.data(11 downto 8); @@ -245,7 +248,8 @@ begin BUS_TX.ack <= '1'; if BUS_RX.addr(11 downto 4) = x"00" then case BUS_RX.addr(3 downto 0) is - when x"0" => BUS_TX.data(31 downto 20) <= (others => '0'); + when x"0" => BUS_TX.data(31 downto 21) <= (others => '0'); + BUS_TX.data(20) <= BUS_locCh0_only0D; BUS_TX.data(19 downto 16) <= BUS_Trig_type_ch0; BUS_TX.data(15 downto 13) <= (others => '0'); BUS_TX.data(12) <= BUS_stop_LimitGen_ch0; @@ -264,7 +268,9 @@ begin BUS_TX.data( 9 downto 0) <= Bus_min; when x"5" => BUS_TX.data(31 downto 10) <= (others => '0'); BUS_TX.data( 9 downto 0) <= Bus_max; - when x"6" => BUS_TX.data <= std_logic_vector(docal_debug_in); + when x"6" => BUS_TX.data(31 downto 16) <= (others => '0'); + BUS_TX.data(15 downto 0) <= MY_ADDRESS_IN; + --BUS_TX.data <= std_logic_vector(docal_debug_in); when x"7" => BUS_TX.data <= std_logic_vector(docal_debug_out); when x"8" => BUS_TX.data(11 downto 8) <= FPGA_Lim; BUS_TX.data(7) <= '0'; @@ -396,6 +402,8 @@ begin BUS_Trig_type => BUS_Trig_type, BUS_stp_Lmt_ch0 => BUS_stop_LimitGen_ch0, BUS_Trig_type_ch0 => BUS_Trig_type_ch0, + BUS_locCh0_only0D => BUS_locCh0_only0D, + MY_ADDRESS_IN => MY_ADDRESS_IN, chnl => chnl_read_cnt, FPGA_out => FPGA_o_cnt, FPGA_in => FPGA_in, diff --git a/combiner_cts/code_EBR/read_cnt.vhd b/combiner_cts/code_EBR/read_cnt.vhd index 4128adf..4b41224 100644 --- a/combiner_cts/code_EBR/read_cnt.vhd +++ b/combiner_cts/code_EBR/read_cnt.vhd @@ -16,7 +16,9 @@ entity read_cnt is BUS_stp_Lmt : in std_logic; BUS_Trig_type : in std_logic_vector( 3 downto 0); BUS_stp_Lmt_ch0 : in std_logic; - BUS_Trig_type_ch0 : in std_logic_vector( 3 downto 0); + BUS_Trig_type_ch0 : in std_logic_vector( 3 downto 0); + BUS_locCh0_only0D : in std_logic; + MY_ADDRESS_IN : in std_logic_vector(15 downto 0); DIN : in std_logic_vector(31 downto 0); DIN_ready : in std_logic; DIN_type : in std_logic_vector( 3 downto 0); @@ -69,6 +71,7 @@ begin --channel 0 if (DIN(28 downto 22) = "0000000") then + -- stop calibration for channel 0 if (ch0_onoff(FPGA_i) = '0') then Do_Cal <= '0'; @@ -77,7 +80,19 @@ begin stop_Limit <= '1'; if ((Trigger_type = BUS_Trig_type_ch0 ) or (BUS_Trig_type_ch0 = "0000")) then stop_Limit <= BUS_stp_Lmt_ch0; - end if; + end if; + + -- Select local TDC data (part of CTS data in datastream) and stop limit generation for channel 0 + -- in case no 0xD trigger is active + if (FPGA_num(FPGA_i) = MY_ADDRESS_IN) and (BUS_locCh0_only0D = '1') then + --if (BUS_locCh0_only0D = '1') then + if Trigger_type = x"d" then + stop_Limit <= '0'; + else + stop_Limit <= '1'; + end if; + end if; + end if; else @@ -96,7 +111,7 @@ begin THE_FPGA_num : process(CLK) variable position : std_logic_vector( 3 downto 0); - variable save : std_logic_vector(11 downto 0) := X"000"; + variable save : std_logic_vector(15 downto 0) := X"0000"; begin position := x"f"; @@ -113,8 +128,9 @@ begin end if; end loop; - if save(11 downto 4) = x"00" then + if save(15 downto 4) = x"000" then if save(3 downto 0) = x"0" then + -- no corresp. FPGA found, add new entry to list FPGA_i <= cnt; FPGA_num(cnt) <= FPGA_in; cnt <= cnt + 1; @@ -129,7 +145,7 @@ begin else --ERROR end if; - elsif save(11 downto 8) = x"0" and save(3 downto 0) = x"0" then + elsif save(15 downto 8) = x"00" and save(3 downto 0) = x"0" then if save(4) = '1' then FPGA_i <= 4; elsif save(5) = '1' then @@ -141,7 +157,7 @@ begin else --ERROR end if; - elsif save(7 downto 0) = x"00" then + elsif save(15 downto 12) = x"0" and save(7 downto 0) = x"00" then if save(8) = '1' then FPGA_i <= 8; elsif save(9) = '1' then @@ -153,6 +169,18 @@ begin else --ERROR end if; + elsif save(11 downto 0) = x"000" then + if save(12) = '1' then + FPGA_i <= 12; + elsif save(13) = '1' then + FPGA_i <= 13; + elsif save(14) = '1' then + FPGA_i <= 14; + elsif save(15) = '1' then + FPGA_i <= 15; + else + --ERROR + end if; else --ERROR end if; -- 2.43.0