From 564ab059ed22e455dd253af540db1a003b99c352 Mon Sep 17 00:00:00 2001 From: Florian Marx Date: Fri, 20 Jul 2018 10:26:51 +0200 Subject: [PATCH] forgot to add merge file --- trigger_merge.vhd | 60 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) create mode 100644 trigger_merge.vhd diff --git a/trigger_merge.vhd b/trigger_merge.vhd new file mode 100644 index 0000000..c586a09 --- /dev/null +++ b/trigger_merge.vhd @@ -0,0 +1,60 @@ +library ieee; + use ieee.std_logic_1164.all; + use ieee.numeric_std.all; + +library work; + use work.trb_net_std.all; + + +entity trg_merge is + port( + clk_in : in std_logic; + signals : in std_logic_vector(31 downto 0); + reg_inhalt : in std_logic_vector(31 downto 0); + processed_signal : out std_logic + ); +end trg_merge; + + + + + +architecture behave of trg_merge is + +signal merged_signal : std_logic_vector(31 downto 0); +signal merged_signal_int : integer range 0 to 1022; + + + +begin +merged_signal_int <= to_integer(unsigned(merged_signal(31 downto 0))); + +-- PROC_combineChannels: process begin +-- wait until rising_edge(clk_in); +-- for i in 0 to 31 loop +-- if signals(i)='1' and reg_inhalt(i)='1' then +-- merged_signal(i) <= '1'; +-- else +-- merged_signal(i) <= '0'; +-- end if; +-- if merged_signal_int > 0 then -- +-- processed_signal <= '1'; +-- end if; +-- end loop; +-- +-- end process; +PROC_combineChannels: process begin +wait until rising_edge(clk_in); +for i in 0 to 31 loop + if signals(i)='1' and reg_inhalt(i)='1' then + processed_signal <= '1'; + else + processed_signal <= '0'; + end if; +end loop; + +end process; + + + +end behave; -- 2.43.0