From 564d73a1336b95f8b7bd46295d179444aca8dc99 Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Tue, 3 Apr 2018 13:52:13 +0200 Subject: [PATCH] Add new calibration PLL for DiRich 3 --- .../PLL/pll_in3125_out50/pll_in3125_out50.lpc | 93 ++++ .../PLL/pll_in3125_out50/pll_in3125_out50.sbx | 430 ++++++++++++++++++ .../PLL/pll_in3125_out50/pll_in3125_out50.vhd | 71 +++ 3 files changed, 594 insertions(+) create mode 100644 base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.lpc create mode 100644 base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.sbx create mode 100644 base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd diff --git a/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.lpc b/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.lpc new file mode 100644 index 0000000..5e4a934 --- /dev/null +++ b/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.lpc @@ -0,0 +1,93 @@ +[Device] +Family=ecp5um +PartType=LFE5UM-85F +PartName=LFE5UM-85F-8BG756C +SpeedGrade=8 +Package=CABGA756 +OperatingCondition=COM +Status=P + +[IP] +VendorName=Lattice Semiconductor Corporation +CoreType=LPM +CoreStatus=Demo +CoreName=PLL +CoreRevision=5.8 +ModuleName=pll_in3125_out50 +SourceFormat=vhdl +ParameterFileVersion=1.0 +Date=04/03/2018 +Time=13:51:04 + +[Parameters] +Verilog=0 +VHDL=1 +EDIF=1 +Destination=Synplicity +Expression=BusA(0 to 7) +Order=Big Endian [MSB:LSB] +IO=0 +CLKI_FREQ=312.5 +CLKI_DIV=25 +ENABLE_HBW=DISABLED +REFERENCE=0 +IOBUF=LVDS +CLKOP_FREQ=50 +CLKOP_TOL=0.0 +CLKOP_DIV=13 +CLKOP_ACTUAL_FREQ=50.000000 +CLKOP_MUXA=DISABLED +CLKOS_Enable=DISABLED +CLKOS_FREQ=100.00 +CLKOS_TOL=0.0 +CLKOS_DIV=1 +CLKOS_ACTUAL_FREQ= +CLKOS_MUXB=DISABLED +CLKOS2_Enable=DISABLED +CLKOS2_FREQ=100.00 +CLKOS2_TOL=0.0 +CLKOS2_DIV=1 +CLKOS2_ACTUAL_FREQ= +CLKOS2_MUXC=DISABLED +CLKOS3_Enable=DISABLED +CLKOS3_FREQ=100.00 +CLKOS3_TOL=0.0 +CLKOS3_DIV=1 +CLKOS3_ACTUAL_FREQ= +CLKOS3_MUXD=DISABLED +FEEDBK_PATH=CLKOP +CLKFB_DIV=4 +FRACN_ENABLE=DISABLED +FRACN_DIV= +VCO_RATE=650.000 +PLL_BW=1.543 +CLKOP_DPHASE=0 +CLKOP_APHASE=0.00 +CLKOP_TRIM_POL=Rising +CLKOP_TRIM_DELAY=0 +CLKOS_DPHASE=0 +CLKOS_APHASE=0.00 +CLKOS_TRIM_POL=Rising +CLKOS_TRIM_DELAY=0 +CLKOS2_DPHASE=0 +CLKOS2_APHASE=0.00 +CLKOS2_TRIM_POL=Rising +CLKOS2_TRIM_DELAY=0 +CLKOS3_DPHASE=0 +CLKOS3_APHASE=0.00 +CLKOS3_TRIM_POL=Rising +CLKOS3_TRIM_DELAY=0 +CLKSEL_ENA=DISABLED +DPHASE_SOURCE=STATIC +ENABLE_CLKOP=DISABLED +ENABLE_CLKOS=DISABLED +ENABLE_CLKOS2=DISABLED +ENABLE_CLKOS3=DISABLED +STDBY_ENABLE=DISABLED +PLLRST_ENA=DISABLED +PLL_LOCK_MODE=DISABLED +PLL_LOCK_STK=DISABLED +PLL_USE_SMI=DISABLED + +[Command] +cmd_line= -w -n pll_in3125_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 312.5 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 diff --git a/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.sbx b/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.sbx new file mode 100644 index 0000000..83737d0 --- /dev/null +++ b/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.sbx @@ -0,0 +1,430 @@ + + + + Lattice Semiconductor Corporation + LEGACY + PLL + 5.8 + + + Diamond_Simulation + simulation + + ./pll_in3125_out50.vhd + vhdlSource + + + + Diamond_Synthesis + synthesis + + ./pll_in3125_out50.vhd + vhdlSource + + + + + + Configuration + none + ${sbp_path}/generate_core.tcl + CONFIG + + + Generation + none + ${sbp_path}/${instance}/generate_core.tcl + GENERATE + + + + + + + + LFE5UM-85F-8BG756C + synplify + 2018-04-03.13:51:09 + 2018-04-03.13:51:09 + 3.10.1.112 + VHDL + + false + false + false + false + false + false + false + false + false + false + LPM + PRIMARY + PRIMARY + false + false + + + + + + Family + ecp5um + + + OperatingCondition + COM + + + Package + CABGA756 + + + PartName + LFE5UM-85F-8BG756C + + + PartType + LFE5UM-85F + + + SpeedGrade + 8 + + + Status + P + + + + CoreName + PLL + + + CoreRevision + 5.8 + + + CoreStatus + Demo + + + CoreType + LPM + + + Date + 04/03/2018 + + + ModuleName + pll_in3125_out50 + + + ParameterFileVersion + 1.0 + + + SourceFormat + vhdl + + + Time + 13:51:04 + + + VendorName + Lattice Semiconductor Corporation + + + + CLKFB_DIV + 4 + + + CLKI_DIV + 25 + + + CLKI_FREQ + 312.5 + + + CLKOP_ACTUAL_FREQ + 50.000000 + + + CLKOP_APHASE + 0.00 + + + CLKOP_DIV + 13 + + + CLKOP_DPHASE + 0 + + + CLKOP_FREQ + 50 + + + CLKOP_MUXA + DISABLED + + + CLKOP_TOL + 0.0 + + + CLKOP_TRIM_DELAY + 0 + + + CLKOP_TRIM_POL + Rising + + + CLKOS2_ACTUAL_FREQ + + + + CLKOS2_APHASE + 0.00 + + + CLKOS2_DIV + 1 + + + CLKOS2_DPHASE + 0 + + + CLKOS2_Enable + DISABLED + + + CLKOS2_FREQ + 100.00 + + + CLKOS2_MUXC + DISABLED + + + CLKOS2_TOL + 0.0 + + + CLKOS2_TRIM_DELAY + 0 + + + CLKOS2_TRIM_POL + Rising + + + CLKOS3_ACTUAL_FREQ + + + + CLKOS3_APHASE + 0.00 + + + CLKOS3_DIV + 1 + + + CLKOS3_DPHASE + 0 + + + CLKOS3_Enable + DISABLED + + + CLKOS3_FREQ + 100.00 + + + CLKOS3_MUXD + DISABLED + + + CLKOS3_TOL + 0.0 + + + CLKOS3_TRIM_DELAY + 0 + + + CLKOS3_TRIM_POL + Rising + + + CLKOS_ACTUAL_FREQ + + + + CLKOS_APHASE + 0.00 + + + CLKOS_DIV + 1 + + + CLKOS_DPHASE + 0 + + + CLKOS_Enable + DISABLED + + + CLKOS_FREQ + 100.00 + + + CLKOS_MUXB + DISABLED + + + CLKOS_TOL + 0.0 + + + CLKOS_TRIM_DELAY + 0 + + + CLKOS_TRIM_POL + Rising + + + CLKSEL_ENA + DISABLED + + + DPHASE_SOURCE + STATIC + + + Destination + Synplicity + + + EDIF + 1 + + + ENABLE_CLKOP + DISABLED + + + ENABLE_CLKOS + DISABLED + + + ENABLE_CLKOS2 + DISABLED + + + ENABLE_CLKOS3 + DISABLED + + + ENABLE_HBW + DISABLED + + + Expression + BusA(0 to 7) + + + FEEDBK_PATH + CLKOP + + + FRACN_DIV + + + + FRACN_ENABLE + DISABLED + + + IO + 0 + + + IOBUF + LVDS + + + Order + Big Endian [MSB:LSB] + + + PLLRST_ENA + DISABLED + + + PLL_BW + 1.543 + + + PLL_LOCK_MODE + DISABLED + + + PLL_LOCK_STK + DISABLED + + + PLL_USE_SMI + DISABLED + + + REFERENCE + 0 + + + STDBY_ENABLE + DISABLED + + + VCO_RATE + 650.000 + + + VHDL + 1 + + + Verilog + 0 + + + + cmd_line + -w -n pll_in3125_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 312.5 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 + + + + + + + LATTICE + LOCAL + pll_in3125_out50 + 1.0 + + + + diff --git a/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd b/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd new file mode 100644 index 0000000..30e9761 --- /dev/null +++ b/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.vhd @@ -0,0 +1,71 @@ +-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.1.112 +-- Module Version: 5.7 +--/d/jspc29/lattice/diamond/3.10_x64/ispfpga/bin/lin64/scuba -w -n pll_in3125_out50 -lang vhdl -synth synplify -bus_exp 7 -bb -arch sa5p00m -type pll -fin 312.5 -fclkop 50 -fclkop_tol 0.0 -phase_cntl STATIC -fb_mode 1 -fdc /d/jspc22/trb/git/tdc/base/cores/ecp5/PLL/pll_in3125_out50/pll_in3125_out50.fdc + +-- Tue Apr 3 13:51:09 2018 + +library IEEE; +use IEEE.std_logic_1164.all; +library ecp5um; +use ecp5um.components.all; + +entity pll_in3125_out50 is + port ( + CLKI: in std_logic; + CLKOP: out std_logic); +end pll_in3125_out50; + +architecture Structure of pll_in3125_out50 is + + -- internal signal declarations + signal REFCLK: std_logic; + signal LOCK: std_logic; + signal CLKOP_t: std_logic; + signal scuba_vhi: std_logic; + signal scuba_vlo: std_logic; + + attribute FREQUENCY_PIN_CLKOP : string; + attribute FREQUENCY_PIN_CLKI : string; + attribute ICP_CURRENT : string; + attribute LPF_RESISTOR : string; + attribute FREQUENCY_PIN_CLKOP of PLLInst_0 : label is "50.000000"; + attribute FREQUENCY_PIN_CLKI of PLLInst_0 : label is "312.500000"; + attribute ICP_CURRENT of PLLInst_0 : label is "6"; + attribute LPF_RESISTOR of PLLInst_0 : label is "16"; + attribute syn_keep : boolean; + attribute NGD_DRC_MASK : integer; + attribute NGD_DRC_MASK of Structure : architecture is 1; + +begin + -- component instantiation statements + scuba_vhi_inst: VHI + port map (Z=>scuba_vhi); + + scuba_vlo_inst: VLO + port map (Z=>scuba_vlo); + + PLLInst_0: EHXPLLL + generic map (PLLRST_ENA=> "DISABLED", INTFB_WAKE=> "DISABLED", + STDBY_ENABLE=> "DISABLED", DPHASE_SOURCE=> "DISABLED", + CLKOS3_FPHASE=> 0, CLKOS3_CPHASE=> 0, CLKOS2_FPHASE=> 0, + CLKOS2_CPHASE=> 0, CLKOS_FPHASE=> 0, CLKOS_CPHASE=> 0, + CLKOP_FPHASE=> 0, CLKOP_CPHASE=> 12, PLL_LOCK_MODE=> 0, + CLKOS_TRIM_DELAY=> 0, CLKOS_TRIM_POL=> "FALLING", + CLKOP_TRIM_DELAY=> 0, CLKOP_TRIM_POL=> "FALLING", + OUTDIVIDER_MUXD=> "DIVD", CLKOS3_ENABLE=> "DISABLED", + OUTDIVIDER_MUXC=> "DIVC", CLKOS2_ENABLE=> "DISABLED", + OUTDIVIDER_MUXB=> "DIVB", CLKOS_ENABLE=> "DISABLED", + OUTDIVIDER_MUXA=> "DIVA", CLKOP_ENABLE=> "ENABLED", CLKOS3_DIV=> 1, + CLKOS2_DIV=> 1, CLKOS_DIV=> 1, CLKOP_DIV=> 13, CLKFB_DIV=> 4, + CLKI_DIV=> 25, FEEDBK_PATH=> "CLKOP") + port map (CLKI=>CLKI, CLKFB=>CLKOP_t, PHASESEL1=>scuba_vlo, + PHASESEL0=>scuba_vlo, PHASEDIR=>scuba_vlo, + PHASESTEP=>scuba_vlo, PHASELOADREG=>scuba_vlo, + STDBY=>scuba_vlo, PLLWAKESYNC=>scuba_vlo, RST=>scuba_vlo, + ENCLKOP=>scuba_vlo, ENCLKOS=>scuba_vlo, ENCLKOS2=>scuba_vlo, + ENCLKOS3=>scuba_vlo, CLKOP=>CLKOP_t, CLKOS=>open, + CLKOS2=>open, CLKOS3=>open, LOCK=>LOCK, INTLOCK=>open, + REFCLK=>REFCLK, CLKINTFB=>open); + + CLKOP <= CLKOP_t; +end Structure; -- 2.43.0