From 566261466980c4730798a46bfa448a95bca52df0 Mon Sep 17 00:00:00 2001 From: hadaq Date: Tue, 27 Mar 2007 09:25:56 +0000 Subject: [PATCH] new version of API, Ingo --- trb_net_active_api.vhd | 205 ++++++++++++++++++++++++++++++++--------- trb_net_fifo.vhd | 4 +- trb_net_iobuf.vhd | 13 ++- 3 files changed, 173 insertions(+), 49 deletions(-) diff --git a/trb_net_active_api.vhd b/trb_net_active_api.vhd index 33617ee..1c45c8d 100644 --- a/trb_net_active_api.vhd +++ b/trb_net_active_api.vhd @@ -12,10 +12,10 @@ use work.trb_net_std.all; entity trb_net_active_api is - generic (FIFO_TO_INT_DEPTH : integer := 3; -- Depth of the FIFO, 2^(n+1), + generic (FIFO_TO_INT_DEPTH : integer := 0; -- Depth of the FIFO, 2^(n+1), -- for the direction to -- internal world - FIFO_TO_APL_DEPTH : integer := 3; -- direction to application + FIFO_TO_APL_DEPTH : integer := 0; -- direction to application FIFO_TERM_BUFFER_DEPTH : integer := 0); -- fifo for auto-answering of -- the master path, if set to 0 -- no buffer is used at all @@ -99,6 +99,24 @@ component trb_net_fifo is end component; +component trb_net_dummy_fifo is + generic (WIDTH : integer := 8); -- Depth of the FIFO, 2^(n+1) + + port (CLK : in std_logic; + RESET : in std_logic; + CLK_EN : in std_logic; + + DATA_IN : in std_logic_vector(WIDTH - 1 downto 0); -- Input data + WRITE_ENABLE_IN : in std_logic; + DATA_OUT : out std_logic_vector(WIDTH - 1 downto 0); -- Output data + READ_ENABLE_IN : in std_logic; + FULL_OUT : out std_logic; -- Full Flag + EMPTY_OUT : out std_logic; + DEPTH_OUT : out std_logic_vector(7 downto 0) + ); + + end component; + component trb_net_sbuf is generic (DATA_WIDTH : integer := 56); @@ -151,8 +169,11 @@ type TERM_BUFFER_STATE is (IDLE, RUNNING, SEND_TRAILER, MY_ERROR); signal current_state, next_state : API_STATE; signal tb_current_state, tb_next_state : TERM_BUFFER_STATE; -signal combined_header, registered_header, next_registered_header: std_logic_vector(47 downto 0); + signal combined_header: std_logic_vector(47 downto 0); --stored in sbuf +-- , registered_header, next_registered_header: std_logic_vector(47 downto 0); +--signal update_registered_header: std_logic; signal combined_trailer, registered_trailer, next_registered_trailer: std_logic_vector(47 downto 0); +signal update_registered_trailer: std_logic; signal tb_registered_trailer, tb_next_registered_trailer: std_logic_vector(47 downto 0); signal tb_registered_target, tb_next_registered_target: std_logic_vector(15 downto 0); @@ -165,8 +186,12 @@ signal next_APL_DATAREADY_OUT, reg_APL_DATAREADY_OUT: std_logic; signal next_APL_DATA_OUT, reg_APL_DATA_OUT: std_logic_vector(47 downto 0); signal next_APL_TYP_OUT, reg_APL_TYP_OUT: std_logic_vector(2 downto 0); +type OUTPUT_SELECT is (HDR, DAT, TRM); +signal out_select:OUTPUT_SELECT; + begin + CHECK_BUFFER3: if FIFO_TO_INT_DEPTH >0 generate FIFO_TO_INT: trb_net_fifo generic map ( WIDTH => 48, @@ -182,7 +207,24 @@ begin FULL_OUT => fifo_to_int_full, EMPTY_OUT => fifo_to_int_empty ); - + end generate CHECK_BUFFER3; + CHECK_BUFFER4: if FIFO_TO_INT_DEPTH =0 generate + FIFO_TO_INT: trb_net_dummy_fifo + generic map ( + WIDTH => 48) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_to_int_data_in, + WRITE_ENABLE_IN => fifo_to_int_write, + DATA_OUT => fifo_to_int_data_out, + READ_ENABLE_IN => fifo_to_int_read, + FULL_OUT => fifo_to_int_full, + EMPTY_OUT => fifo_to_int_empty + ); + end generate CHECK_BUFFER4; + CHECK_BUFFER5: if FIFO_TO_APL_DEPTH >0 generate FIFO_TO_APL: trb_net_fifo generic map ( WIDTH => 51, @@ -198,7 +240,25 @@ begin FULL_OUT => fifo_to_apl_full, EMPTY_OUT => fifo_to_apl_empty ); + end generate CHECK_BUFFER5; + CHECK_BUFFER6: if FIFO_TO_APL_DEPTH =0 generate + FIFO_TO_APL: trb_net_dummy_fifo + generic map ( + WIDTH => 51) + port map ( + CLK => CLK, + RESET => RESET, + CLK_EN => CLK_EN, + DATA_IN => fifo_to_apl_data_in, + WRITE_ENABLE_IN => fifo_to_apl_write, + DATA_OUT => fifo_to_apl_data_out, + READ_ENABLE_IN => fifo_to_apl_read, + FULL_OUT => fifo_to_apl_full, + EMPTY_OUT => fifo_to_apl_empty + ); + end generate CHECK_BUFFER6; + CHECK_BUFFER1: if FIFO_TERM_BUFFER_DEPTH >0 generate FIFO_TERM_BUFFER: trb_net_fifo generic map ( @@ -320,10 +380,27 @@ INIT_SBUF: trb_net_sbuf ); sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle - +next_registered_trailer <= combined_trailer; +--next_registered_header <= combined_header; +next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION); +next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION); + + process (out_select, combined_header, registered_trailer) + begin + if out_select = HDR then + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_header; + elsif out_select = TRM then + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; + else + next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; + next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + end if; + end process; -- combinatorial part of state machine STATE_COMB : process(current_state, APL_SEND_IN, combined_header, INT_INIT_READ_IN, - APL_WRITE_IN, fifo_to_int_empty, next_registered_header, registered_header, + APL_WRITE_IN, fifo_to_int_empty, fifo_to_int_data_out, combined_trailer, next_registered_trailer, fifo_to_int_data_out, fifo_to_apl_empty, INT_REPLY_DATAREADY_IN, reg_INT_REPLY_READ_OUT,fifo_to_apl_read, @@ -331,18 +408,21 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle APL_READ_IN, sbuf_free, reg_APL_TYP_OUT) begin -- process next_state <= MY_ERROR; - next_registered_header <= registered_header; +-- next_registered_header <= registered_header; +-- update_registered_header <= '0'; next_INT_INIT_DATAREADY_OUT <= '0'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= (others => '0'); - next_registered_trailer <= registered_trailer; + out_select <= DAT; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_ILLEGAL; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= (others => '0'); +-- next_registered_trailer <= registered_trailer; + update_registered_trailer <= '0'; fifo_to_int_read <= '0'; next_INT_REPLY_READ_OUT <= '0'; fifo_to_apl_write <= '0'; - next_APL_DATAREADY_OUT <= '0'; - next_APL_DATA_OUT <= (others => '0'); - next_APL_TYP_OUT <= TYPE_ILLEGAL; + next_APL_DATAREADY_OUT <= '0'; +-- next_APL_DATA_OUT <= (others => '0'); +-- next_APL_TYP_OUT <= TYPE_ILLEGAL; fifo_to_apl_read <= '0'; ------------------------------------------------------------------------------- -- IDLE @@ -350,18 +430,21 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle if current_state = IDLE then if APL_SEND_IN = '1' then if APL_SHORT_TRANSFER_IN = '1' and APL_WRITE_IN = '0' and fifo_to_int_empty = '1' then - next_registered_header <= (others => '0'); + --next_registered_header <= (others => '0'); next_state <= SEND_SHORT; -- no next data word, waiting for -- falling edge of APL_SEND_IN - next_registered_trailer <= combined_trailer; -- trailer will be +-- update_registered_trailer <= '1'; + --next_registered_trailer <= combined_trailer; -- trailer will be -- constructed with -- raising edge !! next_INT_INIT_DATAREADY_OUT <= '0'; else -- normal transfer, prepare the header - next_registered_header <= combined_header; + --next_registered_header <= combined_header; +-- update_registered_header <= '1'; next_state <= SEND_HEADER; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_header; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_HDR; + out_select <= HDR; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_header; next_INT_INIT_DATAREADY_OUT <= '1'; end if; -- next word will be a header else @@ -375,10 +458,12 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle if APL_SEND_IN = '0' then -- terminate the transfer next_state <= SEND_TRAILER; next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; + out_select <= TRM; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; else - next_registered_trailer <= combined_trailer; --update trailer when APL_SEND_ + update_registered_trailer <= '1'; + --next_registered_trailer <= combined_trailer; --update trailer when APL_SEND_ --IN longer then one --CLK cycle end if; @@ -392,8 +477,9 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle next_INT_INIT_DATAREADY_OUT <= '0'; else next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + out_select <= DAT; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty else @@ -406,18 +492,22 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle if APL_SEND_IN = '0' then -- terminate the transfer if fifo_to_int_empty = '1' then -- immediate stop next_state <= SEND_TRAILER; - next_registered_trailer <= combined_trailer; + update_registered_trailer <= '1'; + --next_registered_trailer <= combined_trailer; next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_trailer; + out_select <= TRM; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= combined_trailer; else next_state <= SHUTDOWN; - next_registered_trailer <= combined_trailer; + update_registered_trailer <= '1'; + --next_registered_trailer <= combined_trailer; if sbuf_free = '1' then -- data words have to be prepared next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + out_select <= DAT; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty = '0' end if; @@ -426,8 +516,9 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle if fifo_to_int_empty = '0' and sbuf_free = '1' then -- data words have to be prepared next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + out_select <= DAT; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; fifo_to_int_read <= '1'; end if; -- fifo_to_int_empty = '0' end if; @@ -439,15 +530,17 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle if fifo_to_int_empty = '0' and sbuf_free = '1' then -- data words have to be prepared next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; + out_select <= DAT; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_DAT; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= fifo_to_int_data_out; fifo_to_int_read <= '1'; elsif sbuf_free = '1' then -- we are done next_state <= SEND_TRAILER; next_INT_INIT_DATAREADY_OUT <= '1'; - next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; - next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; + out_select <= TRM; +-- next_INT_INIT_DATA_OUT(TYPE_POSITION) <= TYPE_TRM; +-- next_INT_INIT_DATA_OUT(DWORD_POSITION) <= registered_trailer; end if; ------------------------------------------------------------------------------- -- SEND_TRAILER @@ -476,8 +569,8 @@ sbuf_free <= sbuf_next_READ or INT_INIT_READ_IN; --sbuf killed in next cycle -- part 2: connection to apl if (fifo_to_apl_empty = '0') then next_APL_DATAREADY_OUT <= '1'; - next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION); - next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION); +-- next_APL_DATA_OUT <= fifo_to_apl_data_out(DWORD_POSITION); +-- next_APL_TYP_OUT <= fifo_to_apl_data_out(TYPE_POSITION); end if; -- read/no read if reg_APL_DATAREADY_OUT = '1' and APL_READ_IN = '1' then @@ -561,8 +654,8 @@ CLK_REG: process(CLK) -- reg_APL_TYP_OUT <= (others => '0'); current_state <= IDLE; tb_current_state <= IDLE; - registered_header <= (others => '0'); - registered_trailer <= (others => '0'); +-- registered_header <= (others => '0'); +-- registered_trailer <= (others => '0'); tb_registered_trailer <= (others => '0'); tb_registered_target <= ILLEGAL_ADRESS; elsif CLK_EN = '1' then @@ -575,8 +668,8 @@ CLK_REG: process(CLK) -- reg_APL_TYP_OUT <= next_APL_TYP_OUT; current_state <= next_state; tb_current_state <= tb_next_state; - registered_header <= next_registered_header; - registered_trailer <= next_registered_trailer; +-- registered_header <= next_registered_header; +-- registered_trailer <= next_registered_trailer; tb_registered_trailer <= tb_next_registered_trailer; tb_registered_target <= tb_next_registered_target; @@ -590,12 +683,38 @@ CLK_REG: process(CLK) -- reg_APL_TYP_OUT <= reg_APL_TYP_OUT; current_state <= current_state; tb_current_state <= tb_current_state; - registered_header <= registered_header; - registered_trailer <= registered_trailer; +-- registered_header <= registered_header; +-- registered_trailer <= registered_trailer; tb_registered_trailer <= tb_registered_trailer; tb_registered_target <= tb_registered_target; end if; end if; end process; + + REG3 : process(CLK) + begin + if rising_edge(CLK) then + if RESET = '1' then + registered_trailer <= (others => '0'); + elsif update_registered_trailer = '1' then + registered_trailer <= next_registered_trailer; + else + registered_trailer <= registered_trailer; + end if; + end if; + end process; + +-- REG4 : process(CLK) +-- begin +-- if rising_edge(CLK) then +-- if RESET = '1' then +-- registered_header <= (others => '0'); +-- elsif update_registered_header = '1' then +-- registered_header <= next_registered_header; +-- else +-- registered_header <= registered_header; +-- end if; +-- end if; +-- end process; end trb_net_active_api_arch; diff --git a/trb_net_fifo.vhd b/trb_net_fifo.vhd index b0d2813..ade63ea 100644 --- a/trb_net_fifo.vhd +++ b/trb_net_fifo.vhd @@ -12,8 +12,8 @@ USE ieee.std_logic_arith.ALL; entity trb_net_fifo is - generic (WIDTH : integer := 8; -- FIFO word width - DEPTH : integer := 4); -- Depth of the FIFO, 2^(n+1) + generic (WIDTH : integer := 51; -- FIFO word width + DEPTH : integer := 3); -- Depth of the FIFO, 2^(n+1) port (CLK : in std_logic; RESET : in std_logic; diff --git a/trb_net_iobuf.vhd b/trb_net_iobuf.vhd index 13c3692..61c48c4 100644 --- a/trb_net_iobuf.vhd +++ b/trb_net_iobuf.vhd @@ -319,6 +319,11 @@ architecture trb_net_iobuf_arch of trb_net_iobuf is STAT_LOCKED(0) <= INIT_IS_LOCKED; STAT_LOCKED(1) <= REPLY_IS_LOCKED; STAT_LOCKED(31 downto 2) <= (others => '0'); + + REPLYOBUF_ctrl_locked(15 downto 2) <= (others => '0'); + REPLYIBUF_ctrl_locked(15 downto 2) <= (others => '0'); + INITOBUF_ctrl_locked(15 downto 2) <= (others => '0'); + INITIBUF_ctrl_locked(15 downto 2) <= (others => '0'); -- comb part of the locking control comb_locked : process (INIT_IS_LOCKED, REPLY_IS_LOCKED, INITIBUF_stat_locked, @@ -328,10 +333,10 @@ comb_locked : process (INIT_IS_LOCKED, REPLY_IS_LOCKED, INITIBUF_stat_locked, begin -- process next_INIT_IS_LOCKED <= INIT_IS_LOCKED; next_REPLY_IS_LOCKED <= REPLY_IS_LOCKED; - REPLYOBUF_ctrl_locked <= (others => '0'); - REPLYIBUF_ctrl_locked <= (others => '0'); - INITOBUF_ctrl_locked <= (others => '0'); - INITIBUF_ctrl_locked <= (others => '0'); + REPLYOBUF_ctrl_locked(1 downto 0) <= (others => '0'); + REPLYIBUF_ctrl_locked(1 downto 0) <= (others => '0'); + INITOBUF_ctrl_locked(1 downto 0) <= (others => '0'); + INITIBUF_ctrl_locked(1 downto 0) <= (others => '0'); if REPLY_IS_LOCKED = '1' then -- listen to INITOBUF -- 2.43.0