From 5690799c9a50c9d915b4a6fe774dba2c19d55450 Mon Sep 17 00:00:00 2001 From: hadaq Date: Fri, 10 Aug 2012 08:56:12 +0000 Subject: [PATCH] *** empty log message *** --- tdc_releases/tdc_v0.3/Channel.vhd | 262 +++++--------------- tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd | 19 +- tdc_releases/tdc_v0.3/Reference_channel.vhd | 250 ++++--------------- tdc_releases/tdc_v0.3/TDC.vhd | 106 ++++---- 4 files changed, 183 insertions(+), 454 deletions(-) diff --git a/tdc_releases/tdc_v0.3/Channel.vhd b/tdc_releases/tdc_v0.3/Channel.vhd index d1fc565..b65da68 100644 --- a/tdc_releases/tdc_v0.3/Channel.vhd +++ b/tdc_releases/tdc_v0.3/Channel.vhd @@ -4,10 +4,16 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + entity Channel is generic ( - CHANNEL_ID : integer range 0 to 64); + CHANNEL_ID : integer range 1 to 64); port ( RESET_WR : in std_logic; RESET_RD : in std_logic; @@ -23,90 +29,16 @@ entity Channel is COARSE_COUNTER_IN : in std_logic_vector(10 downto 0); -- LOST_HIT_NUMBER : out std_logic_vector(23 downto 0); - MEASUREMENT_NUMBER : out std_logic_vector(23 downto 0); + HIT_DETECT_NUMBER : out std_logic_vector(23 downto 0); ENCODER_START_NUMBER : out std_logic_vector(23 downto 0); + FIFO_WR_NUMBER : out std_logic_vector(23 downto 0); -- - Channel_DEBUG_01 : out std_logic_vector(31 downto 0) + Channel_DEBUG : out std_logic_vector(31 downto 0) ); end Channel; architecture Channel of Channel is - -------------------------------------------------------------------------------- --- Component Declarations -------------------------------------------------------------------------------- - - component Adder_304 - port ( - CLK : in std_logic; - RESET : in std_logic; - DataA : in std_logic_vector(303 downto 0); - DataB : in std_logic_vector(303 downto 0); - ClkEn : in std_logic; - Result : out std_logic_vector(303 downto 0)); - end component; --- - component Encoder_304_Bit - port ( - RESET : in std_logic; - CLK : in std_logic; - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); --- BUSY_OUT : out std_logic; - ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - end component; --- - component FIFO_32x32_OutReg - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; --- - --component FIFO_32x512_OutReg - -- port ( - -- Data : in std_logic_vector(31 downto 0); - -- WrClock : in std_logic; - -- RdClock : in std_logic; - -- WrEn : in std_logic; - -- RdEn : in std_logic; - -- Reset : in std_logic; - -- RPReset : in std_logic; - -- Q : out std_logic_vector(31 downto 0); - -- Empty : out std_logic; - -- Full : out std_logic); - --end component; --- - component edge_to_pulse - port ( - clock : in std_logic; - en_clk : in std_logic; - signal_in : in std_logic; - pulse : out std_logic); - end component; --- - component signal_sync - generic ( - WIDTH : integer; - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic_vector(WIDTH-1 downto 0); - D_OUT : out std_logic_vector(WIDTH-1 downto 0)); - end component; ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- @@ -142,10 +74,13 @@ architecture Channel of Channel is ------------------------------------------------------------------------------- -- Debug Signals ------------------------------------------------------------------------------- - signal measurement_cntr : std_logic_vector(23 downto 0); - signal measurement_reg : std_logic_vector(23 downto 0); + + signal hit_detect_cntr : std_logic_vector(23 downto 0); + signal hit_detect_cntr_reg : std_logic_vector(23 downto 0); signal encoder_start_cntr : std_logic_vector(23 downto 0); signal encoder_start_cntr_reg : std_logic_vector(23 downto 0); + signal fifo_wr_cntr : std_logic_vector(23 downto 0); + signal fifo_wr_cntr_reg : std_logic_vector(23 downto 0); signal encoder_debug_i : std_logic_vector(31 downto 0); ------------------------------------------------------------------------------- @@ -166,28 +101,6 @@ begin hit_in_i <= HIT_IN; hit_buf <= not hit_in_i; - ----purpose: Registers the hit signal - --Hit_Register : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- hit_reg <= '0'; - -- else - -- hit_reg <= hit_in_i; - -- end if; - -- end if; - --end process Hit_Register; - - ----purpose: Toggles between rising and falling edges - --Toggle_Edge_Detection : process (hit_reg, hit_in_i) - --begin - -- if hit_reg = '1' then - -- hit_buf <= not hit_in_i; - -- else - -- hit_buf <= hit_in_i; - -- end if; - --end process Toggle_Edge_Detection; - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition FC : Adder_304 port map ( @@ -195,46 +108,11 @@ begin RESET => RESET_WR, DataA => data_a_i, DataB => data_b_i, - ClkEn => '1', --ff_array_en_i, + ClkEn => '1', --ff_array_en_i, Result => result_i); data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf; - --FF_Array_Enable : process (hit_detect_i, release_delay_line_i) - --begin - -- if hit_detect_i = '1' then - -- ff_array_en_i <= '0'; - -- elsif release_delay_line_i = '1' then - -- ff_array_en_i <= '1'; - -- end if; - --end process FF_Array_Enable; - - ----purpose: Enables the signal for delay line releasing - --Release_DL : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- release_delay_line_i <= '0'; - -- elsif hit_detect_2reg = '1' then - -- release_delay_line_i <= '1'; - -- else - -- release_delay_line_i <= '0'; - -- end if; - -- end if; - --end process Release_DL; - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) single transition - --FC : Adder_304 - -- port map ( - -- CLK => CLK_WR, - -- RESET => RESET_WR, - -- DataA => data_a_i, - -- DataB => data_b_i, - -- ClkEn => '1', - -- Result => result_i); - --data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; - --data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i; - --purpose: Registers the hit detection bit Hit_Detect_Register : process (CLK_WR, RESET_WR) begin @@ -277,19 +155,7 @@ begin if rising_edge(CLK_WR) then if RESET_WR = '1' then encoder_start_i <= '0'; - --hit_time_edge_type_i <= '1'; - --hit_time_rising_i <= (others => '0'); - --hit_time_falling_i <= (others => '0'); hit_time_stamp_i <= (others => '0'); - --elsif hit_detect_i = '1' then - -- encoder_start_i <= '1'; - --hit_time_edge_type_i <= not hit_time_edge_type_i; - --if hit_time_edge_type_i = '1' then - -- hit_time_rising_i <= coarse_cntr_i-1; - --else - -- hit_time_falling_i <= coarse_cntr_i-1; - --end if; - --hit_time_stamp_i <= coarse_cntr_i-1; elsif hit_detect_reg = '1' then encoder_start_i <= '1'; hit_time_stamp_i <= coarse_cntr_i-2; @@ -305,7 +171,7 @@ begin RESET => RESET_WR, CLK => CLK_WR, START_IN => encoder_start_i, - THERMOCODE_IN => result_reg, --result_i, + THERMOCODE_IN => result_reg, --result_i, FINISHED_OUT => fifo_wr_en_i, BINARY_CODE_OUT => fine_counter_i, ENCODER_DEBUG => encoder_debug_i); @@ -324,49 +190,13 @@ begin Full => fifo_full_i, AlmostFull => fifo_almost_full_i); - --FIFO : FIFO_32x512_OutReg - -- port map ( - -- Data => fifo_data_in_i, - -- WrClock => CLK_WR, - -- RdClock => CLK_RD, - -- WrEn => fifo_wr_en_i, - -- RdEn => fifo_rd_en_i, - -- Reset => RESET_RD, - -- RPReset => RESET_RD, - -- Q => fifo_data_out_i, - -- Empty => fifo_empty_i, - -- Full => fifo_full_i); fifo_data_in_i(31) <= '1'; -- data marker - fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits + fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits fifo_data_in_i(28 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 7); -- channel number fifo_data_in_i(21 downto 12) <= fine_counter_i; -- fine time from the encoder fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge fifo_data_in_i(10 downto 0) <= hit_time_stamp_i; -- hit time stamp - --Toggle_Edge_Type : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- edge_type_i <= '1'; - -- elsif fifo_wr_en_i = '1' then - -- edge_type_i <= not edge_type_i; - -- end if; - -- end if; - --end process Toggle_Edge_Type; - - --Toggle_Edge_Hit_Time : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- hit_time_stamp_i <= (others => '0'); - -- elsif edge_type_i = '1' then - -- hit_time_stamp_i <= hit_time_rising_i; - -- else - -- hit_time_stamp_i <= hit_time_falling_i; - -- end if; - -- end if; - --end process Toggle_Edge_Hit_Time; - Register_Outputs : process (CLK_RD, RESET_RD) begin if rising_edge(CLK_RD) then @@ -442,7 +272,33 @@ begin ------------------------------------------------------------------------------- -- DEBUG ------------------------------------------------------------------------------- - --purpose: Counts the written hits + --purpose: Counts the detected hits + Hit_Detect_Counter : process (CLK_WR) + begin + if rising_edge(CLK_WR) then + if RESET_WR = '1' then + hit_detect_cntr <= (others => '0'); + elsif hit_pulse = '1' then + hit_detect_cntr <= hit_detect_cntr + 1; + end if; + end if; + end process Hit_Detect_Counter; + + --purpose: Synchronises the hit detect counter to the slowcontrol clock + Hit_Detect_Sync : signal_sync + generic map ( + WIDTH => 24, + DEPTH => 3) + port map ( + RESET => RESET_RD, + CLK0 => CLK_WR, + CLK1 => CLK_RD, + D_IN => hit_detect_cntr, + D_OUT => hit_detect_cntr_reg); + + HIT_DETECT_NUMBER <= hit_detect_cntr_reg; + + --purpose: Counts the encoder start times Encoder_Start_Counter : process (CLK_WR) begin if rising_edge(CLK_WR) then @@ -454,7 +310,7 @@ begin end if; end process Encoder_Start_Counter; - --purpose: Synchronises the measurement counter to the slowcontrol clock + --purpose: Synchronises the encoder start counter to the slowcontrol clock Encoder_Start_Sync : signal_sync generic map ( WIDTH => 24, @@ -469,19 +325,19 @@ begin ENCODER_START_NUMBER <= encoder_start_cntr_reg; --purpose: Counts the written hits - Measurement_Counter : process (CLK_WR) + FIFO_WR_Counter : process (CLK_WR) begin if rising_edge(CLK_WR) then if RESET_WR = '1' then - measurement_cntr <= (others => '0'); + fifo_wr_cntr <= (others => '0'); elsif fifo_wr_en_i = '1' then - measurement_cntr <= measurement_cntr + 1; + fifo_wr_cntr <= fifo_wr_cntr + 1; end if; end if; - end process Measurement_Counter; + end process FIFO_WR_Counter; - --purpose: Synchronises the measurement counter to the slowcontrol clock - Measurement_Sync : signal_sync + --purpose: Synchronises the fifo wr counter to the slowcontrol clock + FIFO_WR_Sync : signal_sync generic map ( WIDTH => 24, DEPTH => 3) @@ -489,15 +345,15 @@ begin RESET => RESET_RD, CLK0 => CLK_WR, CLK1 => CLK_RD, - D_IN => measurement_cntr, - D_OUT => measurement_reg); + D_IN => fifo_wr_cntr, + D_OUT => fifo_wr_cntr_reg); - MEASUREMENT_NUMBER <= measurement_reg; + FIFO_WR_NUMBER <= fifo_wr_cntr_reg; - Channel_DEBUG_01(0) <= hit_pulse; - Channel_DEBUG_01(1) <= encoder_start_i; - Channel_DEBUG_01(2) <= fifo_wr_en_i; - Channel_DEBUG_01(11 downto 3) <= encoder_debug_i(8 downto 0); + --Channel_DEBUG_01(0) <= hit_pulse; + --Channel_DEBUG_01(1) <= encoder_start_i; + --Channel_DEBUG_01(2) <= fifo_wr_en_i; + --Channel_DEBUG_01(11 downto 3) <= encoder_debug_i(8 downto 0); ------------------------------------------------------------------------------- end Channel; diff --git a/tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd b/tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd index ca9789b..a582bbd 100644 --- a/tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd +++ b/tdc_releases/tdc_v0.3/Encoder_304_Bit.vhd @@ -4,7 +4,7 @@ -- File : Encoder_304_Bit.vhd -- Author : Cahit Ugur -- Created : 2011-11-28 --- Last update: 2012-05-08 +-- Last update: 2012-08-02 ------------------------------------------------------------------------------- -- Description: Encoder for 304 bits ------------------------------------------------------------------------------- @@ -18,6 +18,12 @@ use ieee.std_logic_unsigned.all; use ieee.std_logic_1164.all; use ieee.numeric_std.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + -- synopsys translate_off library ecp3; use ecp3.components.all; @@ -48,16 +54,7 @@ architecture behavioral of Encoder_304_Bit is Z : out std_ulogic); end component; - component ROM_Encoder - port ( - Address : in std_logic_vector(9 downto 0); - OutClock : in std_logic; - OutClockEn : in std_logic; - Reset : in std_logic; - Q : out std_logic_vector(7 downto 0)); - end component; - -------------------------------------------------------------------------------- +----------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- signal P_lut : std_logic_vector(37 downto 0); diff --git a/tdc_releases/tdc_v0.3/Reference_channel.vhd b/tdc_releases/tdc_v0.3/Reference_channel.vhd index 346ca4e..bc97f91 100644 --- a/tdc_releases/tdc_v0.3/Reference_channel.vhd +++ b/tdc_releases/tdc_v0.3/Reference_channel.vhd @@ -4,10 +4,16 @@ use ieee.std_logic_1164.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; +library work; +use work.trb_net_std.all; +use work.trb_net_components.all; +use work.trb3_components.all; +use work.version.all; + entity Reference_Channel is generic ( - CHANNEL_ID : integer range 0 to 15); + CHANNEL_ID : integer range 0 to 0); port ( RESET_WR : in std_logic; RESET_RD : in std_logic; @@ -31,107 +37,39 @@ entity Reference_Channel is end Reference_Channel; architecture Reference_Channel of Reference_Channel is - -------------------------------------------------------------------------------- --- Component Declarations -------------------------------------------------------------------------------- - - component Adder_304 - port ( - CLK : in std_logic; - RESET : in std_logic; - DataA : in std_logic_vector(303 downto 0); - DataB : in std_logic_vector(303 downto 0); - ClkEn : in std_logic; - Result : out std_logic_vector(303 downto 0)); - end component; --- - component Encoder_304_Bit - port ( - RESET : in std_logic; - CLK : in std_logic; - START_IN : in std_logic; - THERMOCODE_IN : in std_logic_vector(303 downto 0); - FINISHED_OUT : out std_logic; - BINARY_CODE_OUT : out std_logic_vector(9 downto 0); - ENCODER_DEBUG : out std_logic_vector(31 downto 0)); - end component; --- - component FIFO_32x32_OutReg - port ( - Data : in std_logic_vector(31 downto 0); - WrClock : in std_logic; - RdClock : in std_logic; - WrEn : in std_logic; - RdEn : in std_logic; - Reset : in std_logic; - RPReset : in std_logic; - Q : out std_logic_vector(31 downto 0); - Empty : out std_logic; - Full : out std_logic; - AlmostFull : out std_logic); - end component; --- - --component FIFO_32x512_OutReg - -- port ( - -- Data : in std_logic_vector(31 downto 0); - -- WrClock : in std_logic; - -- RdClock : in std_logic; - -- WrEn : in std_logic; - -- RdEn : in std_logic; - -- Reset : in std_logic; - -- RPReset : in std_logic; - -- Q : out std_logic_vector(31 downto 0); - -- Empty : out std_logic; - -- Full : out std_logic); - --end component; --- - component bit_sync - generic ( - DEPTH : integer); - port ( - RESET : in std_logic; - CLK0 : in std_logic; - CLK1 : in std_logic; - D_IN : in std_logic; - D_OUT : out std_logic); - end component; - -------------------------------------------------------------------------------- - ------------------------------------------------------------------------------- -- Signal Declarations ------------------------------------------------------------------------------- - signal data_a_i : std_logic_vector(303 downto 0); - signal data_b_i : std_logic_vector(303 downto 0); - signal result_i : std_logic_vector(303 downto 0); - signal result_reg : std_logic_vector(303 downto 0); - signal hit_in_i : std_logic; - signal hit_buf : std_logic; - signal hit_detect_i : std_logic; - signal hit_detect_reg : std_logic; - signal hit_detect_2reg : std_logic; - signal release_delay_line_i : std_logic; - signal result_2_reg : std_logic; - signal coarse_cntr_i : std_logic_vector(10 downto 0); - signal hit_time_stamp_i : std_logic_vector(10 downto 0); - signal fine_counter_i : std_logic_vector(9 downto 0); - signal fine_counter_reg : std_logic_vector(9 downto 0); - signal encoder_start_i : std_logic; - signal encoder_finished_i : std_logic; - signal encoder_debug_i : std_logic_vector(31 downto 0); - signal fifo_data_out_i : std_logic_vector(31 downto 0); - signal fifo_data_in_i : std_logic_vector(31 downto 0); - signal fifo_empty_i : std_logic; - signal fifo_full_i : std_logic; - signal fifo_almost_full_i : std_logic; - signal fifo_wr_en_i : std_logic; - signal fifo_rd_en_i : std_logic; - signal valid_tmg_trg_i : std_logic; - signal multi_tmg_trg_i : std_logic; - signal spike_detected_i : std_logic; - signal ff_array_en_i : std_logic := '1'; + signal data_a_i : std_logic_vector(303 downto 0); + signal data_b_i : std_logic_vector(303 downto 0); + signal result_i : std_logic_vector(303 downto 0); + signal result_reg : std_logic_vector(303 downto 0); + signal hit_in_i : std_logic; + signal hit_buf : std_logic; + signal hit_detect_i : std_logic; + signal hit_detect_reg : std_logic; + signal hit_detect_2reg : std_logic; + signal dl_release_i : std_logic; + signal result_2_reg : std_logic; + signal coarse_cntr_i : std_logic_vector(10 downto 0); + signal hit_time_stamp_i : std_logic_vector(10 downto 0); + signal fine_counter_i : std_logic_vector(9 downto 0); + signal fine_counter_reg : std_logic_vector(9 downto 0); + signal encoder_start_i : std_logic; + signal encoder_finished_i : std_logic; + signal encoder_debug_i : std_logic_vector(31 downto 0); + signal fifo_data_out_i : std_logic_vector(31 downto 0); + signal fifo_data_in_i : std_logic_vector(31 downto 0); + signal fifo_empty_i : std_logic; + signal fifo_full_i : std_logic; + signal fifo_almost_full_i : std_logic; + signal fifo_wr_en_i : std_logic; + signal fifo_rd_en_i : std_logic; + signal valid_tmg_trg_i : std_logic; + signal multi_tmg_trg_i : std_logic; + signal spike_detected_i : std_logic; + signal ff_array_en_i : std_logic := '1'; type FSM is (IDLE, LOOK_FOR_VALIDITY, ENCODER_FINISHED, WAIT_FOR_FALLING_EDGE); signal FSM_CURRENT, FSM_NEXT : FSM; @@ -139,11 +77,14 @@ architecture Reference_Channel of Reference_Channel is signal fsm_debug_i : std_logic_vector(3 downto 0); signal fsm_debug_fsm : std_logic_vector(3 downto 0); - attribute syn_keep : boolean; - attribute syn_keep of hit_buf : signal is true; - attribute syn_keep of hit_in_i : signal is true; - attribute NOMERGE : string; - attribute NOMERGE of hit_buf : signal is "true"; + attribute syn_keep : boolean; + attribute syn_keep of hit_buf : signal is true; + attribute syn_keep of hit_in_i : signal is true; + attribute syn_keep of ff_array_en_i : signal is true; + attribute NOMERGE : string; + attribute NOMERGE of hit_buf : signal is "true"; + attribute NOMERGE of hit_in_i : signal is "true"; + attribute NOMERGE of ff_array_en_i : signal is "true"; ------------------------------------------------------------------------------- @@ -151,32 +92,10 @@ begin fifo_rd_en_i <= READ_EN_IN; coarse_cntr_i <= COARSE_COUNTER_IN; - hit_in_i <= HIT_IN; - hit_buf <= not hit_in_i; +-- hit_in_i <= HIT_IN; + hit_buf <= not HIT_IN; - ----purpose: Registers the hit signal - --Hit_Register : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- hit_reg <= '0'; - -- else - -- hit_reg <= hit_in_i; - -- end if; - -- end if; - --end process Hit_Register; - - ----purpose: Toggles between rising and falling edges - --Toggle_Edge_Detection : process (hit_reg, hit_in_i) - --begin - -- if hit_reg = '1' then - -- hit_buf <= not hit_in_i; - -- else - -- hit_buf <= hit_in_i; - -- end if; - --end process Toggle_Edge_Detection; - - --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) + --purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) double transition FC : Adder_304 port map ( CLK => CLK_WR, @@ -188,42 +107,6 @@ begin data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF" & x"7FFFFFF"; data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000" & not(hit_buf) & x"000000" & "00" & hit_buf; - --FF_Array_Enable : process (hit_detect_i, release_delay_line_i) - --begin - -- if hit_detect_i = '1' then - -- ff_array_en_i <= '0'; - -- elsif release_delay_line_i = '1' then - -- ff_array_en_i <= '1'; - -- end if; - --end process FF_Array_Enable; - - ----purpose: Enables the signal for delay line releasing - --Release_DL : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- release_delay_line_i <= '0'; - -- elsif hit_detect_2reg = '1' then - -- release_delay_line_i <= '1'; - -- else - -- release_delay_line_i <= '0'; - -- end if; - -- end if; - --end process Release_DL; - - ----purpose: Tapped Delay Line 304 (Carry Chain) with wave launcher (21) single transition - --FC : Adder_304 - -- port map ( - -- CLK => CLK_WR, - -- RESET => RESET_WR, - -- DataA => data_a_i, - -- DataB => data_b_i, - -- ClkEn => '1', - -- Result => result_i); - --data_a_i <= x"FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF"; - --data_b_i <= x"000000000000000000000000000000000000000000000000000000000000000000000000000" & "000" & hit_in_i; - - --purpose: Registers the 2nd bit of the carry chain Hit_Detect_Register : process (CLK_WR, RESET_WR) begin @@ -232,20 +115,18 @@ begin result_2_reg <= '0'; hit_detect_reg <= '0'; hit_detect_2reg <= '0'; --- result_29_reg <= '0'; else result_2_reg <= result_i(2); hit_detect_reg <= hit_detect_i; hit_detect_2reg <= hit_detect_reg; --- result_29_reg <= result_i(30); end if; end if; end process Hit_Detect_Register; --purpose: Detects the hit - Hit_Detect : process (result_2_reg, result_i) --result_29_reg + Hit_Detect : process (result_2_reg, result_i) begin - hit_detect_i <= ((not result_2_reg) and result_i(2)); -- or (result_29_reg and not(result_i(29))); + hit_detect_i <= ((not result_2_reg) and result_i(2)); end process Hit_Detect; --purpose: Double Synchroniser @@ -254,14 +135,12 @@ begin if rising_edge(CLK_WR) then if RESET_WR = '1' then result_reg <= (others => '1'); - elsif hit_detect_i = '1' then --or hit_trig_reset_i = '1' then + elsif hit_detect_i = '1' then result_reg <= result_i; end if; end if; end process Double_Syncroniser; --- Channel_DEBUG_01(0) <= result_reg(303); - --purpose: Start Encoder and captures the time stamp of the hit Start_Encoder : process (CLK_WR) begin @@ -315,38 +194,13 @@ begin Empty => fifo_empty_i, Full => fifo_full_i, AlmostFull => fifo_almost_full_i); - - --FIFO : FIFO_32x512_OutReg - -- port map ( - -- Data => fifo_data_in_i, - -- WrClock => CLK_WR, - -- RdClock => CLK_RD, - -- WrEn => fifo_wr_en_i, - -- RdEn => fifo_rd_en_i, - -- Reset => RESET_RD, - -- RPReset => RESET_RD, - -- Q => fifo_data_out_i, - -- Empty => fifo_empty_i, - -- Full => fifo_full_i); - fifo_data_in_i(31) <= '1'; -- data marker - fifo_data_in_i(30 downto 28) <= "000"; -- reserved bits - fifo_data_in_i(27 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 6); -- channel number + fifo_data_in_i(30 downto 29) <= "00"; -- reserved bits + fifo_data_in_i(28 downto 22) <= conv_std_logic_vector(CHANNEL_ID, 7); -- channel number fifo_data_in_i(21 downto 12) <= fine_counter_reg; -- fine time from the encoder fifo_data_in_i(11) <= '1'; --edge_type_i; -- rising '1' or falling '0' edge fifo_data_in_i(10 downto 0) <= hit_time_stamp_i; -- hit time stamp - --Toggle_Edge_Type : process (CLK_WR, RESET_WR) - --begin - -- if rising_edge(CLK_WR) then - -- if RESET_WR = '1' then - -- edge_type_i <= '1'; - -- elsif fifo_wr_en_i = '1' then - -- edge_type_i <= not edge_type_i; - -- end if; - -- end if; - --end process Toggle_Edge_Type; - Register_Outputs : process (CLK_RD, RESET_RD) begin if rising_edge(CLK_RD) then diff --git a/tdc_releases/tdc_v0.3/TDC.vhd b/tdc_releases/tdc_v0.3/TDC.vhd index d48840a..1f414c8 100644 --- a/tdc_releases/tdc_v0.3/TDC.vhd +++ b/tdc_releases/tdc_v0.3/TDC.vhd @@ -19,7 +19,7 @@ use work.version.all; entity TDC is generic ( - CHANNEL_NUMBER : integer range 1 to 65; + CHANNEL_NUMBER : integer range 2 to 65; STATUS_REG_NR : integer range 0 to 6; CONTROL_REG_NR : integer range 0 to 6); port ( @@ -151,6 +151,7 @@ architecture TDC of TDC is -- 0: triggerless signal readout_trigger_mode_200 : std_logic := '1'; -- trigger mode signal synchronised to the coarse counter clk signal logic_anal_control : std_logic_vector(3 downto 0); + signal debug_mode_en_i : std_logic; -- Statistics Signals type statistics_array_12 is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(11 downto 0); @@ -181,25 +182,30 @@ architecture TDC of TDC is signal wait_time : std_logic_vector(23 downto 0); signal empty_channels : std_logic_vector(CHANNEL_NUMBER-1 downto 0); signal total_empty_channel : std_logic_vector(23 downto 0); - signal channel_lost_hits : statistics_array_24; - signal channel_measurement : statistics_array_24; + signal channel_lost_hit_number : statistics_array_24; + signal channel_hit_detect_number : statistics_array_24; signal channel_encoder_start_number : statistics_array_24; + signal channel_fifo_wr_number : statistics_array_24; signal stop_status_i : std_logic; -- Test signals - signal ref_debug_i : std_logic_vector(31 downto 0); + signal ref_debug_i : std_logic_vector(31 downto 0); type channel_debug_array is array (1 to CHANNEL_NUMBER-1) of std_logic_vector(31 downto 0); - signal channel_debug_01_i : channel_debug_array; + signal channel_debug_i : channel_debug_array; ------------------------------------------------------------------------------- begin ------------------------------------------------------------------------------- -- Slow control signals ------------------------------------------------------------------------------- - ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); - trigger_win_en <= CONTROL_REG_IN(1*32+31); + logic_anal_control <= CONTROL_REG_IN(3 downto 0) when rising_edge(CLK_READOUT); + debug_mode_en_i <= CONTROL_REG_IN(4); readout_trigger_mode <= CONTROL_REG_IN(12); - logic_anal_control <= CONTROL_REG_IN(3 downto 0); + + trigger_win_en <= CONTROL_REG_IN(1*32+31); + + ch_en_i <= CONTROL_REG_IN(3*32+31 downto 2*32+0); + ------------------------------------------------------------------------------- -- The Reset Signal Genaration (Synchronous with the fine time clock) ------------------------------------------------------------------------------- @@ -257,10 +263,11 @@ begin FIFO_FULL_OUT => channel_full_i(i), FIFO_ALMOST_FULL_OUT => channel_almost_full_i(i), COARSE_COUNTER_IN => coarse_cnt, - LOST_HIT_NUMBER => channel_lost_hits(i), - MEASUREMENT_NUMBER => channel_measurement(i), + LOST_HIT_NUMBER => channel_lost_hit_number(i), + HIT_DETECT_NUMBER => channel_hit_detect_number(i), ENCODER_START_NUMBER => channel_encoder_start_number(i), - Channel_DEBUG_01 => channel_debug_01_i(i)); + FIFO_WR_NUMBER => channel_fifo_wr_number(i), + Channel_DEBUG => channel_debug_i(i)); end generate GEN_Channels; channel_data_i(CHANNEL_NUMBER) <= x"FFFFFFFF"; @@ -535,6 +542,7 @@ begin when 10 => data_out_reg <= "010" & "01010" & wait_time; stop_status_i <= '1'; when 11 => data_out_reg <= "010" & "01011" & total_empty_channel; + i := -1; when others => null; end case; data_wr_reg <= '1'; @@ -565,11 +573,11 @@ begin begin if rising_edge(CLK_READOUT) then if RESET = '1' then - channel_data_reg <= (others => x"00000000"); - channel_empty_reg <= (others => '0'); + channel_data_reg <= (others => x"00000000"); + channel_empty_reg <= (others => '0'); else - channel_data_reg <= channel_data_i; - channel_empty_reg <= channel_empty_i; + channel_data_reg <= channel_data_i; + channel_empty_reg <= channel_empty_i; end if; end if; end process Delay_Channel_Data; @@ -624,7 +632,7 @@ begin FSM_PROC : process (FSM_CURRENT, VALID_TIMING_TRG_IN, VALID_NOTIMING_TRG_IN, trg_win_end_i, fifo_nr_next, fifo_nr, channel_empty_reg, TRG_DATA_VALID_IN, INVALID_TRG_IN, TMGTRG_TIMEOUT_IN, - TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i) + TRG_TYPE_IN, SPURIOUS_TRG_IN, stop_status_i, debug_mode_en_i) begin start_trg_win_cnt_fsm <= '0'; @@ -641,6 +649,7 @@ begin wait_fsm <= '0'; wr_status_fsm <= '0'; fsm_debug_fsm <= x"00"; + FSM_NEXT <= IDLE; case (FSM_CURRENT) is when IDLE => @@ -655,7 +664,8 @@ begin end if; wr_header_fsm <= '1'; elsif INVALID_TRG_IN = '1' then - FSM_NEXT <= SEND_TRG_RELEASE_A; + FSM_NEXT <= SEND_TRG_RELEASE_A; + data_finished_fsm <= '1'; else FSM_NEXT <= IDLE; end if; @@ -691,8 +701,12 @@ begin when APPLY_MASK => if fifo_nr_next = CHANNEL_NUMBER then - FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; - data_finished_fsm <= '1'; + if debug_mode_en_i = '1' then + FSM_NEXT <= SEND_STATUS; + else + FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; + data_finished_fsm <= '1'; + end if; else FSM_NEXT <= RD_CHANNEL_A; rd_en_fsm(fifo_nr) <= '1'; @@ -752,7 +766,11 @@ begin -- when SEND_STATUS => -- here the status of the TDC should be sent if stop_status_i = '1' then - FSM_NEXT <= SEND_TRG_RELEASE_A; + if debug_mode_en_i = '1' then + FSM_NEXT <= WAIT_FOR_LVL1_TRG_A; + else + FSM_NEXT <= SEND_TRG_RELEASE_A; + end if; data_finished_fsm <= '1'; else FSM_NEXT <= SEND_STATUS; @@ -789,11 +807,8 @@ begin trailer_error_bits <= (others => '0'); -- trailer_error_bits (0) <= wrong_readout_i; -- if there is a wrong readout because of a spurious timing trigger. - -- Information bits sent after a status trigger - -- <= lost_hits_nr_i; -- total number of lost hits. - - fifo_full_i <= or_all(channel_full_i); - fifo_almost_full_i <= or_all(channel_almost_full_i); + fifo_full_i <= or_all(channel_full_i) when rising_edge(CLK_READOUT); + fifo_almost_full_i <= or_all(channel_almost_full_i) when rising_edge(CLK_READOUT); ------------------------------------------------------------------------------- -- Debug and statistics words @@ -1026,6 +1041,9 @@ begin logic_analyser_reg(8) <= REFERENCE_TIME; logic_analyser_reg(9) <= data_wr_reg; logic_analyser_reg(15 downto 10) <= data_out_reg(27 downto 22); + + elsif logic_anal_control = x"4" then -- channel debugging + logic_analyser_reg <= channel_debug_i(1)(15 downto 0); end if; end if; end process REG_LOGIC_ANALYSER_OUTPUT; @@ -1036,11 +1054,9 @@ begin ------------------------------------------------------------------------------- -- Register 0x80 - TDC_DEBUG(7 downto 0) <= fsm_debug_reg; --- --- TDC_DEBUG(15 downto 8) <= --- --- TDC_DEBUG(23 downto 16) <= + TDC_DEBUG(7 downto 0) <= fsm_debug_reg; + TDC_DEBUG(15 downto 8) <= std_logic_vector(to_unsigned(CHANNEL_NUMBER-1, 8)); + TDC_DEBUG(16) <= REFERENCE_TIME when rising_edge(CLK_READOUT); -- -- TDC_DEBUG(27 downto 24) <= -- @@ -1088,22 +1104,28 @@ begin -- Register 0x8f TDC_DEBUG(15*32+23 downto 15*32+0) <= release_number; --- Register 0x90 - TDC_DEBUG(16*32+23 downto 16*32+0) <= channel_lost_hits(1); + --Register 0x90 + -- TDC_DEBUG(16*32+23 downto 16*32+0) <= channel_lost_hit_number(1); + + --Register 0x91 + -- TDC_DEBUG(17*32+23 downto 17*32+0) <= channel_hit_detect_number(1); + + --Register 0x92 + -- TDC_DEBUG(18*32+23 downto 18*32+0) <= channel_encoder_start_number(1); --- Register 0x91 - TDC_DEBUG(17*32+23 downto 17*32+0) <= channel_measurement(1); + --Register 0x93 + -- TDC_DEBUG(19*32+23 downto 19*32+0) <= channel_fifo_wr_number(1); --- Register 0x92 - TDC_DEBUG(18*32+23 downto 18*32+0) <= channel_encoder_start_number(1); +---- Register 0x94 +-- TDC_DEBUG(20*32+23 downto 20*32+0) <= channel_lost_hit_number(2); --- Register 0x93 - TDC_DEBUG(19*32+23 downto 19*32+0) <= channel_lost_hits(2); +---- Register 0x95 +-- TDC_DEBUG(21*32+23 downto 21*32+0) <= channel_hit_detect_number(2); --- Register 0x94 - TDC_DEBUG(20*32+23 downto 20*32+0) <= channel_measurement(2); +---- Register 0x96 +-- TDC_DEBUG(22*32+23 downto 22*32+0) <= channel_encoder_start_number(2); --- Register 0x95 - TDC_DEBUG(21*32+23 downto 21*32+0) <= channel_encoder_start_number(2); +---- Register 0x97 +-- TDC_DEBUG(23*32+23 downto 23*32+0) <= channel_fifo_wr_number(2); end TDC; -- 2.43.0