From 56d416abb04e8669d29927d43de7657ba31db036 Mon Sep 17 00:00:00 2001
From: Ingo Froehlich <ingo@nomail.fake>
Date: Tue, 5 Sep 2017 14:30:19 +0200
Subject: [PATCH] bidirectional uart, IF

---
 default/logicbox.vhd | 44 ++++++++++++++++++++++++++++----------------
 1 file changed, 28 insertions(+), 16 deletions(-)

diff --git a/default/logicbox.vhd b/default/logicbox.vhd
index bfe059b..1229532 100644
--- a/default/logicbox.vhd
+++ b/default/logicbox.vhd
@@ -15,17 +15,17 @@ entity logicbox is
     INPUT  : in  std_logic_vector(3 downto 0);
     OUTPUT : out std_logic_vector(3 downto 0);
 	
-	LED    : inout std_logic_vector(3 downto 0);
-	
-	STATUSI  : in  std_logic;
-	STATUSO  : in  std_logic;
-	CONTROLI : out std_logic;
-	CONTROLO : out std_logic;
-	
-	RX_OUT : out std_logic;
-	TX_IN  : in  std_logic;
-	CBUS   : in  std_logic
-	);
+    LED    : inout std_logic_vector(3 downto 0);
+    
+    STATUSI  : in  std_logic;
+    STATUSO  : in  std_logic;
+    CONTROLI : out std_logic;
+    CONTROLO : out std_logic;
+    
+    RX_OUT : out std_logic;
+    TX_IN  : in  std_logic;
+    CBUS   : in  std_logic
+    );
 end entity;
 
 architecture arch of logicbox is
@@ -47,6 +47,7 @@ architecture arch of logicbox is
   signal uart_read_out  : std_logic := '0';
   signal uart_write_out : std_logic := '0';
   signal uart_ready_in  : std_logic;
+  signal uart_busy_out  : std_logic;
   
   signal uart_rx_data : std_logic_vector(31 downto 0);
   signal uart_tx_data : std_logic_vector(31 downto 0);
@@ -54,6 +55,7 @@ architecture arch of logicbox is
   signal bus_read     : std_logic := '0';
   signal bus_write    : std_logic := '0';
   signal bus_ready    : std_logic; 
+  signal bus_busy     : std_logic;
   
   signal input_i         : std_logic_vector(3 downto 0);
   signal input_selected  : std_logic_vector(3 downto 0); 
@@ -67,7 +69,9 @@ architecture arch of logicbox is
   signal sed_error : std_logic;
   signal sed_debug : std_logic_vector(31 downto 0);
   signal controlsed_i : std_logic_vector(3 downto 0);
-
+  signal testreg1, testreg2 : std_logic_vector(31 downto 0);
+  
+  
   --PULSER
   -------------------------------------  
   signal pulser       : std_logic;
@@ -281,7 +285,7 @@ THE_UART : entity work.uart_sctrl
     WRITE_OUT => uart_write_out,
     READ_OUT  => uart_read_out,
     READY_IN  => uart_ready_in,
-    --READY_IN  => '1',
+    BUSY_OUT  => uart_busy_out,
     
     DEBUG     => open
     );
@@ -323,13 +327,15 @@ THE_FLASH_CONTROLLER : entity generic_flash_ctrl
     SPI_WRITE_IN  => uart_write_out,
     SPI_READ_IN   => uart_read_out,
     SPI_READY_OUT => uart_ready_in,
+    SPI_BUSY_IN   => uart_busy_out,
 
     LOC_DATA_OUT  => uart_rx_data,
     LOC_DATA_IN   => uart_tx_data,
     LOC_ADDR_OUT  => uart_addr,
     LOC_WRITE_OUT => bus_write,
     LOC_READ_OUT  => bus_read,
-    LOC_READY_IN  => bus_ready
+    LOC_READY_IN  => bus_ready,
+    LOC_BUSY_OUT  => bus_busy
 
   );
 
@@ -355,7 +361,10 @@ PROC_REGS : process begin
       
       when x"20" => uart_tx_data <= x"0" & std_logic_vector(pulser_periodlength);
       when x"21" => uart_tx_data <= x"0" & std_logic_vector(pulser_pulslength);
-      
+
+      when x"ff" => uart_tx_data <= testreg1;              
+      when x"fe" => uart_tx_data <= testreg2;                    
+                    
       when others =>null;
     end case;
     
@@ -383,7 +392,10 @@ PROC_REGS : process begin
       when x"21" => pulser_pulslength <= uart_rx_data(27 downto 0);
       
       when x"ee" => controlsed_i <= uart_rx_data(3 downto 0);
-      
+
+      when x"ff" => testreg1 <= uart_rx_data(31 downto 0);
+      when x"fe" => testreg2 <= uart_rx_data(31 downto 0);
+                    
       when others => null;
     end case;
   end if;
-- 
2.43.0