From 574f82e4e88c790b734b669c341d626c946cc507 Mon Sep 17 00:00:00 2001 From: hadaq Date: Mon, 8 Nov 2010 15:25:38 +0000 Subject: [PATCH] update --- cts.tex | 88 +++++++++++++++++++++++++++++++++++++++++++-------------- 1 file changed, 67 insertions(+), 21 deletions(-) diff --git a/cts.tex b/cts.tex index a8209ef..c51eff7 100644 --- a/cts.tex +++ b/cts.tex @@ -6,6 +6,10 @@ The schematics of the new CTS AddOn can be found in \cite{CTS}. %\subsection{Memory Map} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% +Register adddresses from 0xA000 to 0xA0ef is scm fpga (1) +Register adddresses from 0xA0f0 to 0xA0ff is ecp2m fpga (2) +Register adddresses from 0xA100 to 0xA100 + 10*Number of samples per beam structure (currently 50) is from scm fpga (1) + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CTS Control Registers} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -20,13 +24,17 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} \item[Bit 7] Disable Shower pedestals update (generated once during each spill off) \item[Bit 8] Enable Shower calibration trigger \item[Bit 9] Enable test trigger 0xE - \item[Bit 14] Enable beam inhibit + \item[Bit 14] Enable beam inhibit for generation of Shower trigger - look into beam inhibit signal settings register xxx + \item[Bit 15] Enable beam inhibit to make system silent(only cal trigger are accepted) when there is no beam - look into beam inhibit signal settings register xxx \item[Bit 16] Enable TOF/RPC to be a Start signal + \item[Bit 23 -- 20] Set width for VETO signal used for anticoincidence logic - $value * 1.25\,ns$ + \item[Bit 28] Select source for beam structure A - 0 Start, 1 RPC/TOF + \item[Bit 29] Select source for beam structure B - 0 Start, 1 RPC/TOF + \item[Bit 30] When set to '1' it generates RICH special APV trigger (double pulse on RICH connector) - edge sensitive 0 -> 1 \item[Bit 31] Enable trigger line test, this works together with self trigger (set the requried frequency) \end{description} \item [0xA0C1] LVL1/LVL2 trigger settings: \begin{description} - \item[Bit 7 -- 0] How many lvl1 events wait to send lvl2 trigger \item[Bit 16 -- 12] Delay (to the fastes trigger) of MDCB (MDC 3/4) trigger = value * 20 ns \item[Bit 21 -- 17] Delay of MDCA (MDC 1/2) trigger = value * 20 ns \item[Bit 31 -- 28] LVL1 trigger width, when value < 7 then width = 105 + Value*5 ns else width = Value*5ns @@ -41,20 +49,23 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} \item 126 - 108 empty \item 127 - start signal used for anticoincidence logic (after OR) \item 128 - veto signal used for anticoincidence logic (after Width S.) - \item 129 - antycoincidence signal - + \item 129 - antycoincidence signal \end{description} \item[Bit 15 -- 8] Selects the output signal for LVDS OUT(5) (the same values as for LVDS OUT(4)) - \item[Bit 23 -- 16] Data version set into the data stream from the CTS (see CTS data structure chapter) + \item[Bit 31 -- 28] Data version set into the data stream from the CTS (see CTS data structure chapter) \end{description} \item [0xA0C4 -- 0xA0C3] Enable inputs (order as on the Fig.\ref{cts_logic}) - \item [0xA0C6 -- 0xA0C5] TS gating disable - \item [0xA0C8 -- 0xA0C7] Enable outputs + \item [0xA0C5] TS gating disable + \item [0xA0C6] Global time offset for 8 START channels used for beam structure + \item [0xA0C7] Enable outputs + \item [0xA0C8] Sample period for 8 START channels - $value*100ns$ for individual start beam structure \item [0xA0D0 -- 0xA0C9] Downscale registers - $2^{value}$ - \item [0xA0E7 -- 0xA0E5] Large delay registers - $value * 5\,ns$ \item [0xA0D8 -- 0xA0D1] Delay registers - $value * 1,25\,ns$ - \item [0xA0EC -- 0xA0E8] Width registers - $5 + value * 4\,ns$ - + \item [0xA0D9] -- time offset for beam structrure A (after BEAM START signal) + \item [0xA0DA] -- time offset for beam structrure B (after BEAM START signal) + \item [0xA0DB] -- Sample period for beam structrure A - $value*100ns$ + \item [0xA0DC] -- Sample period for beam structrure B - $value*100ns$ + \item [0xA0DD] -- Length of the beam itself after this time the beam inhibit signal is set till next START BEAM signal - $value*100ns$ \item [0xA0E3] Self trigger \begin{description} \item[Bit 27 -- 0] When 0 the internal triggering is disabled, when different than 0 the internal trigger is enabled and $frequency = 1/Value*10ns $ @@ -64,18 +75,20 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} \item[Bit 6 -- 0] LVL1 trigger information(6 -- 0) \item[Bit 13 -- 8] LVL1 trigger information(13 -- 8) \end{description} - \item [0xA0E7 -- 0xA0E5] Large delays - value * 5ns + \item [0xA0E7 -- 0xA0E5] Large delay registers - $value * 5\,ns$ + \item [0xA0EC -- 0xA0E8] Width registers - $5 + value * 4\,ns$ +% \item[Bit 23 -- 16] Threshold for the rate detection in $1\,us$ time, when number of hits equals the threshold (or more) the per 1sec marker is set +% \item[Bit 31 -- 24] Threshold for the rate detection in $100\,ns$ time, when number of hits equals the threshold (or more) the per 1sec marker is set \item [0xA0F0] LVL2 EB IP table and downscale factor for removing not needed data \begin{description} \item[Bit 15 -- 0] When writing to this register EB is chosen to be a receiver e.g. : 0x8103 then EB15,EB8,EB1 and EB0 is selected -% \item[Bit 23 -- 16] Threshold for the rate detection in $1\,us$ time, when number of hits equals the threshold (or more) the per 1sec marker is set -% \item[Bit 31 -- 24] Threshold for the rate detection in $100\,ns$ time, when number of hits equals the threshold (or more) the per 1sec marker is set - \item[Bit 31 -- 16] When 0 all headers and trailers from TRB TDCs are transported , when different then the value is downsacling factor (counted per event) for transporting headers and trailers (bit 14 of the LVL1 trigger information). + \item[Bit 31 -- 16] When 0 all headers and trailers from TRB TDCs are transported , when different then the value is downsacling factor (counted per event) for transporting headers and trailers (bit 17 of the LVL1 trigger information). \end{description} \item [0xA0F1] LVL2 - events per EB \begin{description} \item[Bit 23 -- 0] Number of events per EB \end{description} + \item [0xA0F2] Mask for making busy based on LVL1 inforamtion sent back from the endpoints (when set to 1 and if lvl1 info is also 1 the busy will be created) \end{description} %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% @@ -189,9 +202,34 @@ For all registers described in this subsection refer to the Fig.\ref{cts_logic} % \item[Bit 7 -- 0] If one of the bits is set then per $1\,us$ amount of hits excceeded given threshold (0xA0E1(23 -- 16)) (LSB corresponds to the input 0 of the start) % \item[Bit 23 -- 16] If one of the bits is set then per $100\,ns$ amount of hits excceeded given threshold (0xA0E1(31 -- 24)) (LSB corresponds to the input 0 of the start) % \end{description} + \item[0xA0F8] -- Status of LVL2 logic placed on ECP2M FPGA + \begin{description} + \item[15 -- 0] LVL2 trigger number + \item[19 -- 16] LVL2 trigger buffer counter 3 -- 0 + \item[29--20] lvl1 triggers number -- lvl2 triggers numebr + \item[30] LVL2 -> LVL1 back pressure busy (when LVL2 trigger fifo goes almost full) + \item[31] Loccaly created LVL2 busy based on IPU TRBnet busy + \end{description} + \item[0xA0F9] -- LVL1 information sent back from the endpoints + \item[0xA0FA] + \begin{description} + \item[0] There is a lvl1 busy based on LVL1 informatio sent back from the endpoints + \end{description} + \item[0xA131 - 0xA100] - beam structure A + \item[0xA163 - 0xA132] - beam structure B + \item[0xA195 - 0xA164] - Start structure inout 1 + \item[0xA1C7 - 0xA96] - Start structure input 2 + \item[0xA164 - 0xA132] - Start structure input 3 + \item[0xA164 - 0xA132] - Start structure input 4 + \item[0xA164 - 0xA132] - Start structure input 5 + \item[0xA164 - 0xA132] - Start structure input 6 + \item[0xA164 - 0xA132] - Start structure input 7 \end{description} + + + %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% \subsection{CTS Data structure} @@ -225,16 +263,17 @@ When there is MDC calibration trigger CTS sends also scalers information. \item[bit 12] PT 2 \item[bit 13] PT 3 \item[bit 14] PT 4 - \item[bit 31 -- 15] All 0 + \item[bit 15] PT 5 + \item[bit 16] PT 6 + \item[bit 17] PT 7 + \item[bit 18] PT 8 + \item[bit 31 -- 19] All 0 \end{description} \item[5 Latches] All 0 -\item[6 - XX] The rest of the data is just copy of all R and RW registers (maximally up to the address 0xA0EF) +\item[6 - XX] The rest of the data is just copy of all RW and R (for the scalers it is a copy of hits per second) registers (maximally up to the address 0xA0EF) \begin{description} - \item[6] Register from 0xA000 address - \item[7] Register from 0xA001 address .... - \item[6+Numeber of read registers - 1] last read register (currently 0xA051) - \item[6+Numeber of read registers] first rw register (0xA0C0) - \item[6+Numeber of read registers + Number of read write registers] last rw register (currently 0xA0EC) + \item[6+RW registers(48)-1 -- 6] Register from 0xA0C0 address to 0xA0EC + \item[6+RW registers(48)+R registers(81)-1 -- 6+RW registers(48)] Register from 0xA000 address to 0xA051 \end{description} \end{description} @@ -255,3 +294,10 @@ When there is MDC calibration trigger CTS sends also scalers information. \label{fig:ctstopview} \end{figure} +\begin{figure} + \centering + \includegraphics[width=1\textwidth]{beamcts.pdf} + \caption{ CTS - registers for the beam structure usage and beam inhibit signal} + \label{fig:ctsbeam} +\end{figure} + -- 2.43.0