From 57524b8a33c583321f1dfd4829ff788ccc22ca6e Mon Sep 17 00:00:00 2001 From: Jan Michel Date: Wed, 9 Dec 2015 18:45:31 +0100 Subject: [PATCH] adding debug UART to CTS project. I/O on TEST_LINE(31..30) = J6 pin 4+5 --- base/trb3_central_cts.lpf | 2 +- cts/config_cbmtof.vhd | 1 + cts/trb3_central.prj | 7 +++++ cts/trb3_central.vhd | 65 ++++++++++++++++++++++++++++++++------- 4 files changed, 63 insertions(+), 12 deletions(-) diff --git a/base/trb3_central_cts.lpf b/base/trb3_central_cts.lpf index 0c6ec46..72f976c 100644 --- a/base/trb3_central_cts.lpf +++ b/base/trb3_central_cts.lpf @@ -514,7 +514,7 @@ LOCATE COMP "TEST_LINE_24" SITE "K6"; # "TEST_LINE_30" LOCATE COMP "TEST_LINE_25" SITE "K5"; # "TEST_LINE_31" DEFINE PORT GROUP "TEST_LINE_group" "TEST_LINE*" ; -IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN DRIVE=8; +IOBUF GROUP "TEST_LINE_group" IO_TYPE=LVCMOS25 PULLMODE=DOWN; ################################################################# # Misc diff --git a/cts/config_cbmtof.vhd b/cts/config_cbmtof.vhd index fb84984..21c3280 100644 --- a/cts/config_cbmtof.vhd +++ b/cts/config_cbmtof.vhd @@ -95,6 +95,7 @@ package config is (0,0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0)); constant HARDWARE_INFO_ARR : hw_info_t := (x"9000CEE0",x"9000CEE2"); + constant CLOCK_FREQUENCY : integer := 100; constant INTERNAL_NUM : integer; constant INTERFACE_NUM : integer; constant IS_UPLINK : hub_ct; diff --git a/cts/trb3_central.prj b/cts/trb3_central.prj index b9c299d..fc2db73 100644 --- a/cts/trb3_central.prj +++ b/cts/trb3_central.prj @@ -87,6 +87,13 @@ add_file -vhdl -lib work "../base/code/trigger_clock_manager.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_protocols.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/trb_net_gbe_components.vhd" +add_file -vhdl -lib work "../../trb3sc/code/debuguart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_rec.vhd" +add_file -vhdl -lib work "../../trbnet/special/uart_trans.vhd" +add_file -vhdl -lib work "../../trbnet/lattice/ecp3/fifo/fifo_9x2k_oreg.vhd" + + #GbE add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_wrapper.vhd" add_file -vhdl -lib work "../../trbnet/gbe_trb/base/gbe_logic_wrapper.vhd" diff --git a/cts/trb3_central.vhd b/cts/trb3_central.vhd index 7914d27..e11cdfe 100644 --- a/cts/trb3_central.vhd +++ b/cts/trb3_central.vhd @@ -143,7 +143,7 @@ entity trb3_central is LED_YELLOW : out std_logic; --Test Connectors - TEST_LINE : out std_logic_vector(31 downto 0) + TEST_LINE : inout std_logic_vector(31 downto 0) ); @@ -330,6 +330,16 @@ architecture trb3_central_arch of trb3_central is signal regio_write_ack_in : std_logic; signal regio_unknown_addr_in : std_logic; signal regio_timeout_out : std_logic; + + signal bus_debug_tx_in : CTRLBUS_TX; + signal bus_debug_rx_out : CTRLBUS_RX; + signal debug_active : std_logic; + signal handler_addr : std_logic_vector(15 downto 0); + signal handler_data_out : std_logic_vector(31 downto 0); + signal handler_read : std_logic; + signal handler_write : std_logic; + signal handler_timeout : std_logic; + signal spictrl_read_en : std_logic; signal spictrl_write_en : std_logic; @@ -1260,13 +1270,13 @@ begin FIXED_DELAY => 100, NUMBER_OF_GBE_LINKS => 4, - LINKS_ACTIVE => "1100", + LINKS_ACTIVE => "1000", - LINK_HAS_READOUT => "1100", + LINK_HAS_READOUT => "1000", LINK_HAS_SLOWCTRL => "1000", - LINK_HAS_DHCP => "1100", - LINK_HAS_ARP => "1100", - LINK_HAS_PING => "1100" + LINK_HAS_DHCP => "1000", + LINK_HAS_ARP => "1000", + LINK_HAS_PING => "1000" ) port map( @@ -1439,11 +1449,11 @@ begin CLK => clk_100_i, RESET => reset_i, - DAT_ADDR_IN => regio_addr_out, - DAT_DATA_IN => regio_data_out, + DAT_ADDR_IN => handler_addr, + DAT_DATA_IN => handler_data_out, DAT_DATA_OUT => regio_data_in, - DAT_READ_ENABLE_IN => regio_read_enable_out, - DAT_WRITE_ENABLE_IN => regio_write_enable_out, + DAT_READ_ENABLE_IN => handler_read, + DAT_WRITE_ENABLE_IN => handler_read, DAT_TIMEOUT_IN => regio_timeout_out, DAT_DATAREADY_OUT => regio_dataready_in, DAT_WRITE_ACK_OUT => regio_write_ack_in, @@ -1997,9 +2007,42 @@ begin LED_RED <= debug(2) when INCLUDE_CBMNET = c_NO else cbm_link_active_i; LED_YELLOW <= link_ok; + +--------------------------------------------------------------------------- +-- Debugging UART +--------------------------------------------------------------------------- + THE_DEBUG : entity work.debuguart + port map( + CLK => clk_100_i, + RESET => reset_i, + + RX_IN => TEST_LINE(30), + TX_OUT => TEST_LINE(31), + + DEBUG_ACTIVE => debug_active, + + BUS_DEBUG_TX => bus_debug_tx_in, + BUS_DEBUG_RX => bus_debug_rx_out, + + STATUS => open + + ); + + handler_addr <= bus_debug_rx_out.addr when debug_active = '1' else regio_addr_out; + handler_data_out <= bus_debug_rx_out.data when debug_active = '1' else regio_data_out; + handler_read <= bus_debug_rx_out.read when debug_active = '1' else regio_read_enable_out; + handler_write <= bus_debug_rx_out.write when debug_active = '1' else regio_write_enable_out; + + bus_debug_tx_in.data <= regio_data_in; + bus_debug_tx_in.ack <= regio_dataready_in or regio_write_ack_in; + bus_debug_tx_in.nack <= regio_no_more_data_in; + bus_debug_tx_in.unknown <= regio_unknown_addr_in; + + + --------------------------------------------------------------------------- -- Test Connector --------------------------------------------------------------------------- - TEST_LINE <= (others => '0'); + TEST_LINE(29 downto 0) <= (others => '0'); end architecture; -- 2.43.0